Module Definition
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Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl.u_hw_sel 100.00 100.00 100.00



Module Instance : tb.dut.u_ctrl.u_hw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 assign mubi_int = mubi; 49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 if (!rst_ni) begin 56 unused_logic <= MuBi4False; 57 end else begin 58 unused_logic <= mubi_i; 59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 1/1 assign mubi_out = mubi_int; Tests: T1 T2 T3  83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 23384982 23226339 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23384982 23226339 0 0
T1 2525 2470 0 0
T2 3174 3121 0 0
T3 1155 1063 0 0
T4 6014 5946 0 0
T5 2453 2390 0 0
T6 3437 3292 0 0
T15 8336 8243 0 0
T16 2516 2418 0 0
T17 5476 5398 0 0
T18 5706 5652 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%