Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	96.58			96.58
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	97.26			97.26
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	97.95			97.95
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	97.95			97.95
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	97.95			97.95

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.58			96.58

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.58			96.58

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	292	292	100.00
Total Bits 0->1	146	146	100.00
Total Bits 1->0	146	146	100.00

Ports	4	4	100.00
Port Bits	292	292	100.00
Port Bits 0->1	146	146	100.00
Port Bits 1->0	146	146	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[7:0]	Yes	Yes	T175,T177,T178	Yes	T175,T177,T178	OUTPUT
err_o[1:0]	Yes	Yes	T174,T175,T176	Yes	T174,T175,T176	OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[5:3]	Yes	Yes	T174	Yes	T174	OUTPUT
syndrome_o[7:6]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T174	Yes	T174	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[1:0]	No	No		No		OUTPUT
syndrome_o[2]	Yes	Yes	*T179	Yes	T179	OUTPUT
syndrome_o[4:3]	No	No		No		OUTPUT
syndrome_o[5]	Yes	Yes	*T179	Yes	T179	OUTPUT
syndrome_o[6]	No	No		No		OUTPUT
syndrome_o[7]	Yes	Yes	T179	Yes	T179	OUTPUT
err_o[0]	Yes	Yes	*T179	Yes	T179	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[1:0]	No	No		No		OUTPUT
syndrome_o[4:2]	Yes	Yes	T176	Yes	T176	OUTPUT
syndrome_o[7:5]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T176	Yes	T176	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[1]	Yes	Yes	*T180	Yes	T180	OUTPUT
syndrome_o[2]	No	No		No		OUTPUT
syndrome_o[3]	Yes	Yes	*T180	Yes	T180	OUTPUT
syndrome_o[5:4]	No	No		No		OUTPUT
syndrome_o[6]	Yes	Yes	*T180	Yes	T180	OUTPUT
syndrome_o[7]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T180	Yes	T180	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[0]	Yes	Yes	*T178,*T181	Yes	T178,T181	OUTPUT
syndrome_o[5:1]	No	No		No		OUTPUT
syndrome_o[7:6]	Yes	Yes	T178,T181	Yes	T178,T181	OUTPUT
err_o[0]	Yes	Yes	*T178,*T181	Yes	T178,T181	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[1:0]	No	No		No		OUTPUT
syndrome_o[3:2]	Yes	Yes	T182	Yes	T182	OUTPUT
syndrome_o[4]	No	No		No		OUTPUT
syndrome_o[5]	Yes	Yes	*T182	Yes	T182	OUTPUT
syndrome_o[7:6]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T182	Yes	T182	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[0]	Yes	Yes	*T183	Yes	T183	OUTPUT
syndrome_o[3:1]	No	No		No		OUTPUT
syndrome_o[5:4]	Yes	Yes	T183	Yes	T183	OUTPUT
syndrome_o[7:6]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T183	Yes	T183	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	282	96.58
Total Bits 0->1	146	141	96.58
Total Bits 1->0	146	141	96.58

Ports	4	2	50.00
Port Bits	292	282	96.58
Port Bits 0->1	146	141	96.58
Port Bits 1->0	146	141	96.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[0]	Yes	Yes	*T177	Yes	T177	OUTPUT
syndrome_o[3:1]	No	No		No		OUTPUT
syndrome_o[6:4]	Yes	Yes	T177	Yes	T177	OUTPUT
syndrome_o[7]	No	No		No		OUTPUT
err_o[0]	No	No		No		OUTPUT
err_o[1]	Yes	Yes	T177	Yes	T177	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	284	97.26
Total Bits 0->1	146	142	97.26
Total Bits 1->0	146	142	97.26

Ports	4	2	50.00
Port Bits	292	284	97.26
Port Bits 0->1	146	142	97.26
Port Bits 1->0	146	142	97.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[1:0]	Yes	Yes	T184,*T185	Yes	T184,T185	OUTPUT
syndrome_o[2]	No	No		No		OUTPUT
syndrome_o[3]	Yes	Yes	*T185	Yes	T185	OUTPUT
syndrome_o[4]	No	No		No		OUTPUT
syndrome_o[6:5]	Yes	Yes	*T184,*T185	Yes	T184,T185	OUTPUT
syndrome_o[7]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T184,*T185	Yes	T184,T185	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	286	97.95
Total Bits 0->1	146	143	97.95
Total Bits 1->0	146	143	97.95

Ports	4	2	50.00
Port Bits	292	286	97.95
Port Bits 0->1	146	143	97.95
Port Bits 1->0	146	143	97.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[1:0]	Yes	Yes	T175,*T186,*T187	Yes	T175,T186,T187	OUTPUT
syndrome_o[2]	No	No		No		OUTPUT
syndrome_o[6:3]	Yes	Yes	*T187,*T175,*T186	Yes	T187,T175,T186	OUTPUT
syndrome_o[7]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T175,*T186,*T187	Yes	T175,T186,T187	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	292	286	97.95
Total Bits 0->1	146	143	97.95
Total Bits 1->0	146	143	97.95

Ports	4	3	75.00
Port Bits	292	286	97.95
Port Bits 0->1	146	143	97.95
Port Bits 1->0	146	143	97.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[0]	Yes	Yes	*T188	Yes	T188	OUTPUT
syndrome_o[1]	No	No		No		OUTPUT
syndrome_o[3:2]	Yes	Yes	*T178,T184	Yes	T178,T184	OUTPUT
syndrome_o[4]	No	No		No		OUTPUT
syndrome_o[5]	Yes	Yes	*T178	Yes	T178	OUTPUT
syndrome_o[6]	No	No		No		OUTPUT
syndrome_o[7]	Yes	Yes	T178,T184,T188	Yes	T178,T184,T188	OUTPUT
err_o[1:0]	Yes	Yes	T178,T184,T188	Yes	T178,T184,T188	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	286	97.95
Total Bits 0->1	146	143	97.95
Total Bits 1->0	146	143	97.95

Ports	4	2	50.00
Port Bits	292	286	97.95
Port Bits 0->1	146	143	97.95
Port Bits 1->0	146	143	97.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[5:1]	Yes	Yes	T176,*T182	Yes	T176,T182	OUTPUT
syndrome_o[6]	No	No		No		OUTPUT
syndrome_o[7]	Yes	Yes	T182	Yes	T182	OUTPUT
err_o[0]	Yes	Yes	*T176,*T182	Yes	T176,T182	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range