Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25074615	16338	0	0
attest_sw_binding_0_rd_A	25074615	2239	0	0
attest_sw_binding_1_rd_A	25074615	2081	0	0
attest_sw_binding_2_rd_A	25074615	2025	0	0
attest_sw_binding_3_rd_A	25074615	2132	0	0
attest_sw_binding_4_rd_A	25074615	2207	0	0
attest_sw_binding_5_rd_A	25074615	2179	0	0
attest_sw_binding_6_rd_A	25074615	2118	0	0
attest_sw_binding_7_rd_A	25074615	2073	0	0
intr_enable_rd_A	25074615	2664	0	0
key_version_rd_A	25074615	2154	0	0
max_creator_key_ver_regwen_rd_A	25074615	2264	0	0
max_owner_int_key_ver_regwen_rd_A	25074615	2250	0	0
max_owner_key_ver_regwen_rd_A	25074615	2270	0	0
reseed_interval_regwen_rd_A	25074615	1994	0	0
salt_0_rd_A	25074615	2127	0	0
salt_1_rd_A	25074615	2159	0	0
salt_2_rd_A	25074615	2133	0	0
salt_3_rd_A	25074615	2090	0	0
salt_4_rd_A	25074615	2090	0	0
salt_5_rd_A	25074615	2189	0	0
salt_6_rd_A	25074615	2153	0	0
salt_7_rd_A	25074615	2206	0	0
sealing_sw_binding_0_rd_A	25074615	2010	0	0
sealing_sw_binding_1_rd_A	25074615	2104	0	0
sealing_sw_binding_2_rd_A	25074615	2143	0	0
sealing_sw_binding_3_rd_A	25074615	2270	0	0
sealing_sw_binding_4_rd_A	25074615	2219	0	0
sealing_sw_binding_5_rd_A	25074615	2144	0	0
sealing_sw_binding_6_rd_A	25074615	2052	0	0
sealing_sw_binding_7_rd_A	25074615	2241	0	0
sideload_clear_rd_A	25074615	2173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	16338	0	0
T8	0	228	0	0
T9	0	1158	0	0
T20	7798	0	0	0
T31	13188	0	0	0
T68	19932	397	0	0
T74	5750	0	0	0
T75	1836	0	0	0
T76	40047	0	0	0
T77	3110	0	0	0
T79	0	202	0	0
T83	16805	0	0	0
T89	0	601	0	0
T90	0	30	0	0
T91	0	87	0	0
T93	0	40	0	0
T94	0	83	0	0
T95	6582	0	0	0
T96	5360	0	0	0
T99	0	121	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2239	0	0
T8	82317	67	0	0
T52	8319	0	0	0
T90	0	25	0	0
T91	0	12	0	0
T93	0	29	0	0
T94	0	34	0	0
T105	9957	0	0	0
T147	0	2	0	0
T149	0	52	0	0
T189	0	33	0	0
T190	0	57	0	0
T191	0	21	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2081	0	0
T8	82317	87	0	0
T52	8319	0	0	0
T90	0	27	0	0
T91	0	12	0	0
T93	0	10	0	0
T94	0	33	0	0
T105	9957	0	0	0
T147	0	13	0	0
T149	0	40	0	0
T189	0	23	0	0
T190	0	59	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T199	0	9	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2025	0	0
T8	82317	76	0	0
T52	8319	0	0	0
T90	0	31	0	0
T91	0	7	0	0
T93	0	14	0	0
T94	0	45	0	0
T105	9957	0	0	0
T147	0	7	0	0
T149	0	45	0	0
T189	0	33	0	0
T190	0	78	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	5	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2132	0	0
T8	82317	51	0	0
T52	8319	0	0	0
T90	0	29	0	0
T91	0	10	0	0
T93	0	17	0	0
T94	0	16	0	0
T105	9957	0	0	0
T149	0	38	0	0
T189	0	52	0	0
T190	0	76	0	0
T191	0	12	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	3	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2207	0	0
T8	82317	82	0	0
T52	8319	0	0	0
T90	0	12	0	0
T91	0	9	0	0
T93	0	30	0	0
T94	0	37	0	0
T105	9957	0	0	0
T147	0	2	0	0
T149	0	52	0	0
T189	0	28	0	0
T190	0	61	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	2	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2179	0	0
T8	82317	64	0	0
T52	8319	0	0	0
T90	0	24	0	0
T91	0	21	0	0
T93	0	20	0	0
T94	0	32	0	0
T105	9957	0	0	0
T147	0	4	0	0
T149	0	45	0	0
T189	0	32	0	0
T190	0	66	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	3	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2118	0	0
T8	82317	87	0	0
T52	8319	0	0	0
T90	0	13	0	0
T91	0	13	0	0
T93	0	27	0	0
T94	0	29	0	0
T105	9957	0	0	0
T147	0	9	0	0
T149	0	19	0	0
T189	0	41	0	0
T190	0	65	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	8	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2073	0	0
T8	82317	47	0	0
T52	8319	0	0	0
T90	0	15	0	0
T91	0	22	0	0
T93	0	9	0	0
T94	0	42	0	0
T105	9957	0	0	0
T147	0	12	0	0
T149	0	30	0	0
T189	0	8	0	0
T190	0	91	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2664	0	0
T8	0	58	0	0
T14	96684	0	0	0
T46	47875	0	0	0
T71	57149	30	0	0
T90	0	21	0	0
T91	0	20	0	0
T93	0	14	0	0
T94	0	26	0	0
T120	12049	0	0	0
T201	0	3	0	0
T202	0	5	0	0
T203	0	75	0	0
T204	0	53	0	0
T205	68197	0	0	0
T206	7512	0	0	0
T207	19169	0	0	0
T208	3036	0	0	0
T209	2341	0	0	0
T210	13374	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2154	0	0
T8	82317	65	0	0
T52	8319	0	0	0
T90	0	32	0	0
T91	0	10	0	0
T93	0	15	0	0
T94	0	20	0	0
T105	9957	0	0	0
T147	0	6	0	0
T149	0	25	0	0
T189	0	30	0	0
T190	0	49	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	8	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2264	0	0
T8	82317	70	0	0
T52	8319	0	0	0
T90	0	22	0	0
T91	0	16	0	0
T93	0	18	0	0
T94	0	33	0	0
T105	9957	0	0	0
T147	0	13	0	0
T149	0	39	0	0
T189	0	50	0	0
T190	0	63	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	4	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2250	0	0
T7	8050	0	0	0
T8	0	45	0	0
T45	2176	0	0	0
T65	14083	3	0	0
T90	0	25	0	0
T91	0	27	0	0
T93	0	17	0	0
T94	0	48	0	0
T103	3783	0	0	0
T122	6890	0	0	0
T147	0	8	0	0
T149	0	32	0	0
T189	0	51	0	0
T190	0	95	0	0
T211	8883	0	0	0
T212	7417	0	0	0
T213	19875	0	0	0
T214	13579	0	0	0
T215	25710	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2270	0	0
T8	82317	68	0	0
T52	8319	0	0	0
T90	0	13	0	0
T91	0	21	0	0
T93	0	19	0	0
T94	0	56	0	0
T105	9957	0	0	0
T147	0	2	0	0
T149	0	51	0	0
T189	0	28	0	0
T190	0	74	0	0
T191	0	20	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	1994	0	0
T8	82317	47	0	0
T52	8319	0	0	0
T90	0	22	0	0
T91	0	11	0	0
T93	0	21	0	0
T94	0	35	0	0
T105	9957	0	0	0
T147	0	10	0	0
T149	0	23	0	0
T189	0	36	0	0
T190	0	59	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	7	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2127	0	0
T8	82317	59	0	0
T52	8319	0	0	0
T90	0	20	0	0
T91	0	10	0	0
T93	0	16	0	0
T94	0	21	0	0
T105	9957	0	0	0
T147	0	9	0	0
T149	0	35	0	0
T189	0	4	0	0
T190	0	81	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	5	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2159	0	0
T8	82317	50	0	0
T52	8319	0	0	0
T90	0	26	0	0
T91	0	19	0	0
T93	0	7	0	0
T94	0	23	0	0
T105	9957	0	0	0
T147	0	7	0	0
T149	0	54	0	0
T189	0	43	0	0
T190	0	64	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	4	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2133	0	0
T8	82317	76	0	0
T52	8319	0	0	0
T90	0	23	0	0
T91	0	35	0	0
T93	0	11	0	0
T94	0	19	0	0
T105	9957	0	0	0
T147	0	9	0	0
T149	0	46	0	0
T189	0	29	0	0
T190	0	51	0	0
T191	0	10	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2090	0	0
T8	82317	56	0	0
T52	8319	0	0	0
T90	0	20	0	0
T91	0	24	0	0
T93	0	5	0	0
T94	0	28	0	0
T105	9957	0	0	0
T147	0	15	0	0
T149	0	66	0	0
T189	0	23	0	0
T190	0	59	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2090	0	0
T8	82317	33	0	0
T52	8319	0	0	0
T90	0	15	0	0
T91	0	15	0	0
T93	0	30	0	0
T94	0	49	0	0
T105	9957	0	0	0
T147	0	11	0	0
T149	0	37	0	0
T189	0	36	0	0
T190	0	81	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	7	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2189	0	0
T8	82317	74	0	0
T52	8319	0	0	0
T90	0	27	0	0
T91	0	18	0	0
T93	0	22	0	0
T94	0	36	0	0
T105	9957	0	0	0
T149	0	38	0	0
T189	0	35	0	0
T190	0	69	0	0
T191	0	17	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	12	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2153	0	0
T8	82317	56	0	0
T52	8319	0	0	0
T90	0	30	0	0
T91	0	10	0	0
T93	0	10	0	0
T94	0	44	0	0
T105	9957	0	0	0
T147	0	13	0	0
T149	0	43	0	0
T189	0	38	0	0
T190	0	76	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	2	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2206	0	0
T8	82317	43	0	0
T52	8319	0	0	0
T90	0	23	0	0
T91	0	9	0	0
T93	0	19	0	0
T94	0	57	0	0
T105	9957	0	0	0
T147	0	6	0	0
T149	0	25	0	0
T189	0	34	0	0
T190	0	76	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	2	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2010	0	0
T8	82317	55	0	0
T52	8319	0	0	0
T90	0	20	0	0
T91	0	19	0	0
T93	0	4	0	0
T94	0	29	0	0
T105	9957	0	0	0
T147	0	9	0	0
T149	0	44	0	0
T189	0	14	0	0
T190	0	42	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	3	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2104	0	0
T8	82317	62	0	0
T52	8319	0	0	0
T90	0	26	0	0
T91	0	8	0	0
T93	0	10	0	0
T94	0	13	0	0
T105	9957	0	0	0
T147	0	11	0	0
T149	0	37	0	0
T189	0	30	0	0
T190	0	50	0	0
T191	0	18	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2143	0	0
T8	82317	43	0	0
T52	8319	0	0	0
T90	0	20	0	0
T91	0	20	0	0
T93	0	2	0	0
T94	0	23	0	0
T105	9957	0	0	0
T147	0	14	0	0
T149	0	58	0	0
T189	0	19	0	0
T190	0	96	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	4	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2270	0	0
T8	82317	115	0	0
T52	8319	0	0	0
T90	0	34	0	0
T91	0	15	0	0
T93	0	6	0	0
T94	0	24	0	0
T105	9957	0	0	0
T147	0	12	0	0
T149	0	36	0	0
T189	0	46	0	0
T190	0	90	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T216	0	7	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2219	0	0
T8	82317	68	0	0
T52	8319	0	0	0
T90	0	27	0	0
T91	0	7	0	0
T93	0	17	0	0
T94	0	42	0	0
T105	9957	0	0	0
T147	0	9	0	0
T149	0	49	0	0
T189	0	34	0	0
T190	0	62	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	4	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2144	0	0
T8	82317	75	0	0
T52	8319	0	0	0
T90	0	37	0	0
T91	0	17	0	0
T93	0	10	0	0
T94	0	34	0	0
T105	9957	0	0	0
T147	0	10	0	0
T149	0	39	0	0
T189	0	21	0	0
T190	0	64	0	0
T191	0	31	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2052	0	0
T8	82317	38	0	0
T52	8319	0	0	0
T90	0	25	0	0
T91	0	13	0	0
T93	0	6	0	0
T94	0	24	0	0
T105	9957	0	0	0
T147	0	12	0	0
T149	0	23	0	0
T189	0	31	0	0
T190	0	43	0	0
T191	0	19	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2241	0	0
T8	82317	70	0	0
T52	8319	0	0	0
T90	0	16	0	0
T91	0	25	0	0
T93	0	4	0	0
T94	0	16	0	0
T105	9957	0	0	0
T147	0	5	0	0
T149	0	35	0	0
T189	0	12	0	0
T190	0	73	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	12	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25074615	2173	0	0
T8	82317	60	0	0
T52	8319	0	0	0
T90	0	19	0	0
T91	0	9	0	0
T93	0	14	0	0
T94	0	21	0	0
T105	9957	0	0	0
T147	0	8	0	0
T149	0	51	0	0
T189	0	27	0	0
T190	0	65	0	0
T192	14132	0	0	0
T193	5721	0	0	0
T194	10310	0	0	0
T195	8257	0	0	0
T196	5376	0	0	0
T197	5018	0	0	0
T198	95687	0	0	0
T200	0	4	0	0