Unified Coverage Report :: Module :: keymgr_input_checks

Module : keymgr_input_checks

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_input_checks.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_checks	100.00	100.00

---

Module Instance : tb.dut.u_checks

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_chk[0].u_key_pad	100.00	100.00					100.00
gen_key_chk[1].u_key_pad	100.00	100.00					100.00
u_creator_seed	100.00	100.00					100.00
u_devid	100.00	100.00					100.00
u_health_state	100.00	100.00					100.00
u_owner_seed	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_input_checks

	Line No.	Total	Covered	Percent
TOTAL		12	12	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ROUTINE	107	1	1	100.00

32                        logic [31:0] cur_max_key_version;
33         1/1            assign cur_max_key_version = max_key_versions_i[stage_sel_i];
           Tests:       T1 T2 T3 
34                      
35                        // key version must be smaller than or equal to max version
36         1/1            assign key_version_vld_o = key_version_i <= cur_max_key_version;
           Tests:       T1 T2 T3 
37                      
38                        // general data check
39                        logic [MaxWidth-1:0] creator_seed_padded, owner_seed_padded, devid_padded, health_state_padded;
40                      
41                        prim_msb_extend #(
42                          .InWidth(KeyWidth),
43                          .OutWidth(MaxWidth)
44                        ) u_creator_seed (
45                          .in_i(creator_seed_i),
46                          .out_o(creator_seed_padded)
47                        );
48                      
49                        prim_msb_extend #(
50                          .InWidth(KeyWidth),
51                          .OutWidth(MaxWidth)
52                        ) u_owner_seed (
53                          .in_i(owner_seed_i),
54                          .out_o(owner_seed_padded)
55                        );
56                      
57                        prim_msb_extend #(
58                          .InWidth(DevIdWidth),
59                          .OutWidth(MaxWidth)
60                        ) u_devid (
61                          .in_i(devid_i),
62                          .out_o(devid_padded)
63                        );
64                      
65                        prim_msb_extend #(
66                          .InWidth(HealthStateWidth),
67                          .OutWidth(MaxWidth)
68                        ) u_health_state (
69                          .in_i(health_state_i),
70                          .out_o(health_state_padded)
71                        );
72                      
73         1/1            assign creator_seed_vld_o = valid_chk(creator_seed_padded);
           Tests:       T1 T2 T3 
74         1/1            assign owner_seed_vld_o = valid_chk(owner_seed_padded);
           Tests:       T1 T2 T3 
75         1/1            assign devid_vld_o = valid_chk(devid_padded);
           Tests:       T1 T2 T3 
76         1/1            assign health_state_vld_o = valid_chk(health_state_padded);
           Tests:       T1 T2 T3 
77                      
78                        // key check
79                        logic unused_key_vld;
80         1/1            assign unused_key_vld = key_i.valid;
           Tests:       T1 T2 T3 
81                      
82                        localparam int KeyShares = KmacEnMasking ? Shares : 1;
83                        logic [KeyShares-1:0][MaxWidth-1:0] key_padded;
84                        logic [KeyShares-1:0] key_chk;
85                      
86                        for (genvar i = 0; i < KeyShares; i++) begin : gen_key_chk
87                          prim_msb_extend #(
88                            .InWidth(KeyWidth),
89                            .OutWidth(MaxWidth)
90                          ) u_key_pad (
91                            .in_i(key_i.key[i]),
92                            .out_o(key_padded[i])
93                          );
94                      
95         2/2              assign key_chk[i] = valid_chk(key_padded[i]);
           Tests:       T1 T2 T3  | T1 T2 T3 
96                        end
97                      
98         1/1            assign key_vld_o = &key_chk;
           Tests:       T1 T2 T3 
99                      
100                       // rom digest check
101        1/1            assign rom_digest_vld_o = rom_digest_i.valid &
           Tests:       T1 T2 T3 
102                                                 valid_chk(MaxWidth'(rom_digest_i.data));
103                     
104                       // checks for all 0's or all 1's of value
105                       function automatic logic valid_chk (logic [MaxWidth-1:0] value);
106                     
107        1/1              return |value & ~&value;
           Tests:       T1 T2 T3