Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2835135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

611767

1

T1

102

T2

214

T3

162

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3032632	1			T1	167		T2	426		T3	1615
values[0x0]	205412	1			T1	52		T2	63		T3	48
values[0x1]	208858	1			T1	53		T2	58		T3	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1949400	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1497502

1

T1

146

T2

273

T3

627

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10555	1			T1	2		T2	3		T17	3
valid_sources[0x01]	11446	1			T1	1		T2	4		T4	22
valid_sources[0x02]	10930	1			T1	1		T2	2		T17	14
valid_sources[0x03]	10516	1			T1	1		T2	2		T17	17
valid_sources[0x04]	10560	1			T1	1		T3	1		T17	10
valid_sources[0x05]	13732	1			T2	2		T3	6		T4	4
valid_sources[0x06]	10804	1			T2	1		T4	9		T15	1
valid_sources[0x07]	12450	1			T1	1		T4	4		T15	6
valid_sources[0x08]	12256	1			T1	1		T2	1		T3	18
valid_sources[0x09]	11895	1			T2	3		T3	27		T17	17
valid_sources[0x0a]	14002	1			T1	1		T2	7		T3	35
valid_sources[0x0b]	12208	1			T2	4		T4	5		T17	9
valid_sources[0x0c]	11209	1			T1	1		T2	1		T4	8
valid_sources[0x0d]	10498	1			T2	2		T17	4		T18	14
valid_sources[0x0e]	10882	1			T2	2		T17	4		T18	5
valid_sources[0x0f]	10608	1			T1	1		T2	1		T15	4
valid_sources[0x10]	18213	1			T1	2		T2	3		T3	3
valid_sources[0x11]	33265	1			T2	2		T17	11		T18	12
valid_sources[0x12]	12873	1			T1	4		T2	3		T3	15
valid_sources[0x13]	18310	1			T1	2		T2	1		T15	2
valid_sources[0x14]	12476	1			T2	1		T3	17		T17	10
valid_sources[0x15]	10552	1			T1	3		T2	2		T3	42
valid_sources[0x16]	12128	1			T2	1		T3	4		T17	4
valid_sources[0x17]	10925	1			T1	1		T2	3		T3	2
valid_sources[0x18]	10526	1			T2	3		T17	20		T18	4
valid_sources[0x19]	11127	1			T1	2		T2	4		T4	2
valid_sources[0x1a]	11006	1			T1	1		T2	4		T17	12
valid_sources[0x1b]	12074	1			T2	1		T17	13		T18	16
valid_sources[0x1c]	11111	1			T1	1		T3	2		T4	17
valid_sources[0x1d]	11990	1			T1	1		T2	3		T17	6
valid_sources[0x1e]	10754	1			T2	2		T17	5		T18	23
valid_sources[0x1f]	11625	1			T1	2		T2	2		T4	5
valid_sources[0x20]	11129	1			T1	1		T2	2		T4	6
valid_sources[0x21]	10763	1			T2	2		T4	4		T17	3
valid_sources[0x22]	29080	1			T1	3		T2	1		T15	8
valid_sources[0x23]	15272	1			T2	3		T15	21		T17	12
valid_sources[0x24]	12922	1			T4	10		T17	12		T18	25
valid_sources[0x25]	12245	1			T1	1		T2	2		T3	25
valid_sources[0x26]	11789	1			T3	1		T4	5		T15	8
valid_sources[0x27]	11610	1			T1	2		T2	3		T17	17
valid_sources[0x28]	10684	1			T1	2		T2	4		T15	10
valid_sources[0x29]	11457	1			T1	1		T15	5		T17	13
valid_sources[0x2a]	10960	1			T1	1		T3	12		T17	4
valid_sources[0x2b]	15984	1			T1	3		T2	1		T3	30
valid_sources[0x2c]	11072	1			T1	1		T2	2		T3	1
valid_sources[0x2d]	11768	1			T1	1		T2	2		T3	24
valid_sources[0x2e]	10596	1			T1	3		T2	4		T4	8
valid_sources[0x2f]	11985	1			T1	2		T2	1		T17	21
valid_sources[0x30]	10942	1			T2	1		T4	17		T17	8
valid_sources[0x31]	10892	1			T1	2		T3	17		T4	3
valid_sources[0x32]	11010	1			T1	4		T2	2		T4	7
valid_sources[0x33]	14016	1			T1	7		T2	1		T4	12
valid_sources[0x34]	10706	1			T2	5		T15	9		T17	12
valid_sources[0x35]	11340	1			T2	2		T17	6		T18	5
valid_sources[0x36]	11056	1			T1	1		T2	1		T17	3
valid_sources[0x37]	10910	1			T2	2		T4	13		T17	9
valid_sources[0x38]	23219	1			T1	1		T2	1		T4	25
valid_sources[0x39]	25687	1			T4	7		T15	2		T17	14
valid_sources[0x3a]	17195	1			T1	2		T2	1		T4	1
valid_sources[0x3b]	16649	1			T1	3		T2	1		T3	41
valid_sources[0x3c]	10698	1			T1	1		T2	2		T4	7
valid_sources[0x3d]	11501	1			T1	1		T15	8		T17	11
valid_sources[0x3e]	10419	1			T1	1		T2	3		T3	27
valid_sources[0x3f]	14261	1			T1	3		T2	4		T4	16
valid_sources[0x40]	12215	1			T1	1		T2	1		T4	1
valid_sources[0x41]	12570	1			T2	1		T17	7		T18	20
valid_sources[0x42]	12064	1			T1	1		T2	2		T15	2
valid_sources[0x43]	10824	1			T2	3		T4	11		T17	11
valid_sources[0x44]	12265	1			T2	2		T3	3		T17	3
valid_sources[0x45]	12209	1			T2	2		T4	5		T17	2
valid_sources[0x46]	10535	1			T1	1		T2	3		T17	9
valid_sources[0x47]	14151	1			T1	1		T17	6		T18	5
valid_sources[0x48]	10956	1			T1	1		T2	5		T3	32
valid_sources[0x49]	10325	1			T1	1		T2	2		T3	1
valid_sources[0x4a]	12475	1			T2	5		T4	5		T17	12
valid_sources[0x4b]	16949	1			T1	1		T2	2		T3	1
valid_sources[0x4c]	11202	1			T2	2		T3	2		T15	6
valid_sources[0x4d]	15934	1			T1	3		T2	4		T17	12
valid_sources[0x4e]	10778	1			T17	11		T18	26		T19	29
valid_sources[0x4f]	10868	1			T1	1		T2	3		T3	12
valid_sources[0x50]	10752	1			T2	2		T17	12		T18	12
valid_sources[0x51]	10602	1			T2	1		T4	9		T17	12
valid_sources[0x52]	15672	1			T1	3		T2	2		T3	1
valid_sources[0x53]	15520	1			T1	2		T17	7		T18	17
valid_sources[0x54]	20999	1			T1	4		T2	3		T4	4
valid_sources[0x55]	11914	1			T2	2		T3	20		T15	3
valid_sources[0x56]	16521	1			T1	1		T2	2		T15	1
valid_sources[0x57]	13060	1			T17	7		T18	18		T19	28
valid_sources[0x58]	17540	1			T1	1		T2	3		T15	9
valid_sources[0x59]	11535	1			T1	1		T2	3		T15	2
valid_sources[0x5a]	10397	1			T1	1		T2	5		T17	12
valid_sources[0x5b]	10772	1			T2	3		T4	1		T17	12
valid_sources[0x5c]	19753	1			T2	1		T4	4		T15	1
valid_sources[0x5d]	10781	1			T2	2		T17	8		T18	17
valid_sources[0x5e]	19281	1			T1	3		T2	2		T4	1
valid_sources[0x5f]	17944	1			T1	1		T2	1		T4	4
valid_sources[0x60]	13426	1			T1	1		T2	2		T4	7
valid_sources[0x61]	10891	1			T2	2		T17	14		T18	11
valid_sources[0x62]	10529	1			T1	1		T2	2		T4	4
valid_sources[0x63]	11129	1			T1	1		T2	5		T3	9
valid_sources[0x64]	10601	1			T3	28		T17	5		T18	7
valid_sources[0x65]	13199	1			T1	1		T2	4		T3	52
valid_sources[0x66]	10678	1			T1	1		T2	1		T17	15
valid_sources[0x67]	12530	1			T1	2		T2	4		T3	24
valid_sources[0x68]	14273	1			T2	3		T4	11		T15	1
valid_sources[0x69]	64015	1			T2	3		T4	1		T17	9
valid_sources[0x6a]	10719	1			T1	1		T2	2		T4	1
valid_sources[0x6b]	10565	1			T1	2		T2	1		T3	40
valid_sources[0x6c]	11705	1			T1	2		T2	2		T4	11
valid_sources[0x6d]	10364	1			T2	1		T17	7		T18	6
valid_sources[0x6e]	10402	1			T1	6		T2	3		T3	38
valid_sources[0x6f]	12816	1			T2	3		T4	14		T17	12
valid_sources[0x70]	24596	1			T2	4		T3	19		T15	4
valid_sources[0x71]	10478	1			T2	1		T3	2		T4	5
valid_sources[0x72]	12191	1			T1	5		T2	1		T16	829
valid_sources[0x73]	11512	1			T1	2		T2	3		T17	13
valid_sources[0x74]	16170	1			T1	3		T2	3		T15	5
valid_sources[0x75]	14494	1			T2	3		T3	5		T17	5
valid_sources[0x76]	12001	1			T1	1		T2	4		T17	5
valid_sources[0x77]	11005	1			T2	3		T17	6		T18	13
valid_sources[0x78]	13738	1			T1	1		T2	4		T17	16
valid_sources[0x79]	12173	1			T2	2		T3	1		T4	5
valid_sources[0x7a]	11062	1			T1	1		T2	3		T17	7
valid_sources[0x7b]	10805	1			T2	2		T3	6		T4	3
valid_sources[0x7c]	10755	1			T1	1		T2	2		T17	7
valid_sources[0x7d]	11045	1			T1	1		T2	3		T4	21
valid_sources[0x7e]	11585	1			T1	1		T2	1		T17	9
valid_sources[0x7f]	11564	1			T1	1		T2	4		T3	2
valid_sources[0x80]	27635	1			T1	2		T2	3		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

330860

1

T1

56

T2

176

T3

140

values[0x0]

all_enables

biggest_size

147540

1

T1

33

T2

24

T3

18

values[0x1]

all_enables

biggest_size

133367

1

T1

13

T2

14

T3

4