Toggle Coverage for Module :
prim_secded_inv_72_64_dec
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
292 |
292 |
100.00 |
Total Bits 0->1 |
146 |
146 |
100.00 |
Total Bits 1->0 |
146 |
146 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
292 |
292 |
100.00 |
Port Bits 0->1 |
146 |
146 |
100.00 |
Port Bits 1->0 |
146 |
146 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[7:0] |
Yes |
Yes |
T126,T181,T182 |
Yes |
T126,T181,T182 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T126,T179,T180 |
Yes |
T126,T179,T180 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
278 |
95.21 |
Total Bits 0->1 |
146 |
139 |
95.21 |
Total Bits 1->0 |
146 |
139 |
95.21 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
278 |
95.21 |
Port Bits 0->1 |
146 |
139 |
95.21 |
Port Bits 1->0 |
146 |
139 |
95.21 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[1] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[6:2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[2] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[6:3] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[4:1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[5] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[6] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
282 |
96.58 |
Total Bits 0->1 |
146 |
141 |
96.58 |
Total Bits 1->0 |
146 |
141 |
96.58 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
282 |
96.58 |
Port Bits 0->1 |
146 |
141 |
96.58 |
Port Bits 1->0 |
146 |
141 |
96.58 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[5:2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:6] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
282 |
96.58 |
Total Bits 0->1 |
146 |
141 |
96.58 |
Total Bits 1->0 |
146 |
141 |
96.58 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
282 |
96.58 |
Port Bits 0->1 |
146 |
141 |
96.58 |
Port Bits 1->0 |
146 |
141 |
96.58 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[4:2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[5] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[6] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
282 |
96.58 |
Total Bits 0->1 |
146 |
141 |
96.58 |
Total Bits 1->0 |
146 |
141 |
96.58 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
282 |
96.58 |
Port Bits 0->1 |
146 |
141 |
96.58 |
Port Bits 1->0 |
146 |
141 |
96.58 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[2:1] |
Yes |
Yes |
T126,*T183 |
Yes |
T126,T183 |
OUTPUT |
syndrome_o[5:3] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:6] |
Yes |
Yes |
T183,T126 |
Yes |
T183,T126 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126,*T183 |
Yes |
T126,T183 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
282 |
96.58 |
Total Bits 0->1 |
146 |
141 |
96.58 |
Total Bits 1->0 |
146 |
141 |
96.58 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
282 |
96.58 |
Port Bits 0->1 |
146 |
141 |
96.58 |
Port Bits 1->0 |
146 |
141 |
96.58 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[5:4] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[6] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[7] |
No |
No |
|
No |
|
OUTPUT |
err_o[0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
282 |
96.58 |
Total Bits 0->1 |
146 |
141 |
96.58 |
Total Bits 1->0 |
146 |
141 |
96.58 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
282 |
96.58 |
Port Bits 0->1 |
146 |
141 |
96.58 |
Port Bits 1->0 |
146 |
141 |
96.58 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T126,*T182 |
Yes |
T126,T182 |
OUTPUT |
syndrome_o[3:1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[4] |
Yes |
Yes |
*T126,*T182 |
Yes |
T126,T182 |
OUTPUT |
syndrome_o[5] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:6] |
Yes |
Yes |
T126,T182 |
Yes |
T126,T182 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126,*T182 |
Yes |
T126,T182 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
282 |
96.58 |
Total Bits 0->1 |
146 |
141 |
96.58 |
Total Bits 1->0 |
146 |
141 |
96.58 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
282 |
96.58 |
Port Bits 0->1 |
146 |
141 |
96.58 |
Port Bits 1->0 |
146 |
141 |
96.58 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[1] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[4:2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:5] |
Yes |
Yes |
T126,T179 |
Yes |
T126,T179 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126,*T179 |
Yes |
T126,T179 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
292 |
286 |
97.95 |
Total Bits 0->1 |
146 |
143 |
97.95 |
Total Bits 1->0 |
146 |
143 |
97.95 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
292 |
286 |
97.95 |
Port Bits 0->1 |
146 |
143 |
97.95 |
Port Bits 1->0 |
146 |
143 |
97.95 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3:2] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[4] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:5] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
292 |
286 |
97.95 |
Total Bits 0->1 |
146 |
143 |
97.95 |
Total Bits 1->0 |
146 |
143 |
97.95 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
292 |
286 |
97.95 |
Port Bits 0->1 |
146 |
143 |
97.95 |
Port Bits 1->0 |
146 |
143 |
97.95 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3:1] |
Yes |
Yes |
*T126,*T183 |
Yes |
T126,T183 |
OUTPUT |
syndrome_o[4] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[5] |
Yes |
Yes |
*T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[6] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T183 |
Yes |
T183 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T183,T126 |
Yes |
T183,T126 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
292 |
288 |
98.63 |
Total Bits 0->1 |
146 |
144 |
98.63 |
Total Bits 1->0 |
146 |
144 |
98.63 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
292 |
288 |
98.63 |
Port Bits 0->1 |
146 |
144 |
98.63 |
Port Bits 1->0 |
146 |
144 |
98.63 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T184 |
Yes |
T184 |
OUTPUT |
syndrome_o[1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3:2] |
Yes |
Yes |
T184,*T126 |
Yes |
T184,T126 |
OUTPUT |
syndrome_o[4] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:5] |
Yes |
Yes |
T126,T184 |
Yes |
T126,T184 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T184,T126 |
Yes |
T184,T126 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
288 |
98.63 |
Total Bits 0->1 |
146 |
144 |
98.63 |
Total Bits 1->0 |
146 |
144 |
98.63 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
288 |
98.63 |
Port Bits 0->1 |
146 |
144 |
98.63 |
Port Bits 1->0 |
146 |
144 |
98.63 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
syndrome_o[2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:3] |
Yes |
Yes |
T185,T126 |
Yes |
T185,T126 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126,*T185 |
Yes |
T126,T185 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
292 |
290 |
99.32 |
Total Bits 0->1 |
146 |
145 |
99.32 |
Total Bits 1->0 |
146 |
145 |
99.32 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
292 |
290 |
99.32 |
Port Bits 0->1 |
146 |
145 |
99.32 |
Port Bits 1->0 |
146 |
145 |
99.32 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[7:0] |
Yes |
Yes |
T126,T181,T186 |
Yes |
T126,T181,T186 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T126,*T180,*T181 |
Yes |
T126,T180,T181 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
292 |
290 |
99.32 |
Total Bits 0->1 |
146 |
145 |
99.32 |
Total Bits 1->0 |
146 |
145 |
99.32 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
292 |
290 |
99.32 |
Port Bits 0->1 |
146 |
145 |
99.32 |
Port Bits 1->0 |
146 |
145 |
99.32 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:1] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T126 |
Yes |
T126 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
292 |
292 |
100.00 |
Total Bits 0->1 |
146 |
146 |
100.00 |
Total Bits 1->0 |
146 |
146 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
292 |
292 |
100.00 |
Port Bits 0->1 |
146 |
146 |
100.00 |
Port Bits 1->0 |
146 |
146 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[7:0] |
Yes |
Yes |
T182,T187,T126 |
Yes |
T182,T187,T126 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T182,T187,T126 |
Yes |
T182,T187,T126 |
OUTPUT |