Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2638868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

625883

1

T1

134

T2

144

T3

145

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2839619	1			T1	380		T2	822		T3	420
values[0x0]	210523	1			T1	37		T2	44		T3	41
values[0x1]	214609	1			T1	44		T2	35		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1818245	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1446506

1

T1

217

T2

358

T3

247

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9316	1			T1	1		T4	19		T5	7
valid_sources[0x01]	13388	1			T1	1		T3	2		T4	20
valid_sources[0x02]	13149	1			T3	1		T4	11		T5	10
valid_sources[0x03]	10012	1			T1	2		T3	2		T4	5
valid_sources[0x04]	11010	1			T2	18		T3	2		T4	8
valid_sources[0x05]	10691	1			T3	3		T4	9		T5	1
valid_sources[0x06]	9837	1			T1	10		T3	1		T4	6
valid_sources[0x07]	14127	1			T1	7		T2	4		T3	3
valid_sources[0x08]	14052	1			T2	12		T3	1		T4	14
valid_sources[0x09]	10017	1			T2	11		T3	3		T4	24
valid_sources[0x0a]	18254	1			T1	8		T3	1		T4	8
valid_sources[0x0b]	9633	1			T1	8		T3	6		T4	6
valid_sources[0x0c]	9660	1			T1	3		T3	3		T4	14
valid_sources[0x0d]	12630	1			T2	5		T3	3		T4	11
valid_sources[0x0e]	15778	1			T3	1		T4	13		T5	1
valid_sources[0x0f]	9276	1			T2	4		T3	1		T4	4
valid_sources[0x10]	11552	1			T1	4		T2	22		T4	13
valid_sources[0x11]	11348	1			T1	2		T2	5		T3	2
valid_sources[0x12]	10567	1			T1	5		T3	2		T4	8
valid_sources[0x13]	9539	1			T3	2		T4	11		T5	12
valid_sources[0x14]	9435	1			T1	1		T3	3		T4	9
valid_sources[0x15]	10846	1			T3	1		T4	14		T5	6
valid_sources[0x16]	9483	1			T2	24		T3	2		T4	5
valid_sources[0x17]	10802	1			T1	1		T2	4		T3	1
valid_sources[0x18]	10493	1			T2	5		T4	12		T5	3
valid_sources[0x19]	14214	1			T1	3		T3	4		T4	11
valid_sources[0x1a]	10297	1			T1	2		T3	3		T4	13
valid_sources[0x1b]	10779	1			T3	5		T4	4		T5	3
valid_sources[0x1c]	9614	1			T3	3		T4	14		T5	1
valid_sources[0x1d]	13994	1			T4	13		T16	6		T18	17
valid_sources[0x1e]	11424	1			T2	6		T3	1		T4	15
valid_sources[0x1f]	10958	1			T3	5		T4	12		T5	7
valid_sources[0x20]	9737	1			T1	1		T3	1		T4	5
valid_sources[0x21]	15214	1			T1	2		T3	4		T4	10
valid_sources[0x22]	9732	1			T3	1		T4	7		T5	6
valid_sources[0x23]	10141	1			T1	2		T2	18		T4	7
valid_sources[0x24]	9089	1			T3	2		T4	17		T5	9
valid_sources[0x25]	11466	1			T3	1		T4	10		T5	2
valid_sources[0x26]	9617	1			T3	2		T4	9		T5	4
valid_sources[0x27]	10476	1			T4	9		T5	3		T16	10
valid_sources[0x28]	10384	1			T2	2		T3	3		T4	14
valid_sources[0x29]	13963	1			T1	10		T3	1		T4	5
valid_sources[0x2a]	11470	1			T1	1		T4	7		T5	9
valid_sources[0x2b]	10668	1			T3	3		T4	3		T5	2
valid_sources[0x2c]	10434	1			T1	3		T3	2		T4	6
valid_sources[0x2d]	16810	1			T1	4		T3	2		T4	17
valid_sources[0x2e]	10711	1			T3	8		T4	9		T5	4
valid_sources[0x2f]	13360	1			T1	1		T3	5		T4	20
valid_sources[0x30]	9829	1			T2	6		T3	6		T4	12
valid_sources[0x31]	9922	1			T1	7		T2	2		T3	2
valid_sources[0x32]	10331	1			T2	8		T4	10		T5	3
valid_sources[0x33]	19014	1			T1	2		T3	6		T4	15
valid_sources[0x34]	10794	1			T1	1		T3	2		T4	6
valid_sources[0x35]	32446	1			T1	3		T2	4		T3	4
valid_sources[0x36]	9490	1			T1	11		T3	4		T4	8
valid_sources[0x37]	11584	1			T4	10		T5	6		T16	5
valid_sources[0x38]	10528	1			T1	4		T4	7		T5	2
valid_sources[0x39]	9986	1			T2	10		T3	1		T4	10
valid_sources[0x3a]	12986	1			T1	1		T2	20		T3	1
valid_sources[0x3b]	10028	1			T1	1		T2	8		T3	1
valid_sources[0x3c]	10155	1			T3	1		T4	2		T5	7
valid_sources[0x3d]	11137	1			T1	1		T2	1		T3	5
valid_sources[0x3e]	9901	1			T1	1		T2	34		T3	1
valid_sources[0x3f]	10370	1			T1	1		T4	6		T5	9
valid_sources[0x40]	9976	1			T2	1		T4	17		T5	1
valid_sources[0x41]	10024	1			T1	1		T3	2		T4	7
valid_sources[0x42]	10564	1			T3	2		T4	10		T5	6
valid_sources[0x43]	12824	1			T2	4		T4	12		T5	4
valid_sources[0x44]	13598	1			T1	1		T2	1		T3	3
valid_sources[0x45]	10062	1			T3	4		T4	9		T5	15
valid_sources[0x46]	10559	1			T1	1		T3	3		T4	12
valid_sources[0x47]	16021	1			T1	4		T3	2		T4	11
valid_sources[0x48]	15322	1			T1	2		T2	3		T3	2
valid_sources[0x49]	17041	1			T1	4		T3	3		T4	16
valid_sources[0x4a]	14830	1			T3	8		T4	15		T5	7
valid_sources[0x4b]	14032	1			T3	1		T4	6		T16	4
valid_sources[0x4c]	11149	1			T3	2		T4	9		T5	7
valid_sources[0x4d]	9827	1			T1	1		T4	13		T5	6
valid_sources[0x4e]	10431	1			T2	3		T3	2		T4	9
valid_sources[0x4f]	11855	1			T1	3		T4	9		T5	5
valid_sources[0x50]	71270	1			T1	10		T2	13		T3	1
valid_sources[0x51]	12132	1			T1	1		T2	17		T3	1
valid_sources[0x52]	9929	1			T3	2		T4	11		T5	2
valid_sources[0x53]	33989	1			T1	2		T3	2		T4	7
valid_sources[0x54]	10626	1			T1	2		T2	17		T4	12
valid_sources[0x55]	9514	1			T4	7		T5	8		T16	4
valid_sources[0x56]	10251	1			T4	8		T5	9		T16	8
valid_sources[0x57]	21028	1			T3	2		T4	16		T5	4
valid_sources[0x58]	11543	1			T1	8		T3	1		T4	8
valid_sources[0x59]	9740	1			T2	11		T3	2		T4	7
valid_sources[0x5a]	13631	1			T1	5		T2	26		T3	5
valid_sources[0x5b]	28586	1			T2	9		T3	2		T4	6
valid_sources[0x5c]	16071	1			T4	10		T5	9		T16	12
valid_sources[0x5d]	10237	1			T1	1		T3	5		T4	16
valid_sources[0x5e]	9778	1			T1	1		T3	5		T4	9
valid_sources[0x5f]	9814	1			T3	2		T4	10		T16	2
valid_sources[0x60]	14671	1			T1	14		T3	1		T4	5
valid_sources[0x61]	13465	1			T1	9		T4	7		T5	7
valid_sources[0x62]	12137	1			T2	10		T4	12		T5	2
valid_sources[0x63]	8757	1			T3	1		T4	14		T5	8
valid_sources[0x64]	11175	1			T2	1		T3	1		T4	7
valid_sources[0x65]	9726	1			T1	1		T2	2		T4	7
valid_sources[0x66]	9921	1			T1	3		T3	1		T4	7
valid_sources[0x67]	17573	1			T3	1		T4	8		T5	4
valid_sources[0x68]	11058	1			T1	17		T3	1		T4	11
valid_sources[0x69]	9603	1			T2	1		T3	2		T4	18
valid_sources[0x6a]	10607	1			T3	1		T4	13		T5	13
valid_sources[0x6b]	10992	1			T3	3		T4	11		T5	7
valid_sources[0x6c]	13187	1			T1	2		T3	1		T4	10
valid_sources[0x6d]	10266	1			T1	3		T4	13		T5	4
valid_sources[0x6e]	11051	1			T3	3		T4	18		T5	5
valid_sources[0x6f]	10549	1			T1	3		T4	15		T5	3
valid_sources[0x70]	36101	1			T3	2		T4	7		T5	14
valid_sources[0x71]	12836	1			T3	8		T4	9		T5	5
valid_sources[0x72]	14094	1			T3	1		T4	9		T5	2
valid_sources[0x73]	10971	1			T2	2		T3	2		T4	6
valid_sources[0x74]	10704	1			T4	9		T5	2		T16	3
valid_sources[0x75]	9914	1			T2	22		T3	1		T4	7
valid_sources[0x76]	9800	1			T1	1		T4	10		T5	4
valid_sources[0x77]	10012	1			T3	1		T4	7		T5	7
valid_sources[0x78]	9776	1			T2	1		T3	4		T4	18
valid_sources[0x79]	9855	1			T3	3		T4	13		T5	1
valid_sources[0x7a]	11690	1			T1	1		T3	2		T4	15
valid_sources[0x7b]	10697	1			T3	1		T4	19		T5	5
valid_sources[0x7c]	10041	1			T1	5		T2	19		T3	2
valid_sources[0x7d]	11169	1			T3	2		T4	10		T5	4
valid_sources[0x7e]	9091	1			T2	3		T3	1		T4	1
valid_sources[0x7f]	11030	1			T3	4		T4	15		T5	9
valid_sources[0x80]	11161	1			T1	8		T4	7		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

335372

1

T1

107

T2

116

T3

118

values[0x0]

all_enables

biggest_size

152441

1

T1

16

T2

19

T3

14

values[0x1]

all_enables

biggest_size

138070

1

T1

11

T2

9

T3

13