Unified Coverage Report :: Module :: keymgr_op_state_ctrl

Module : keymgr_op_state_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_op_state	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_ctrl.u_op_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_op_state_ctrl

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
ALWAYS	44	3	3	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	23	23	100.00

43                        state_e state_q, state_d;
44         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
44.1                    `ifdef SIMULATION                                   
44.2                        prim_sparse_fsm_flop #(                           
44.3                          .StateEnumT(state_e),                            
44.4                          .Width($bits(state_e)),                          
44.5                          .ResetValue($bits(state_e)'(StIdle)),          
44.6                          .EnableAlertTriggerSVA(1), 
44.7                          .CustomForceName("state_q")          
44.8                        ) u_state_regs (                                        
44.9                          .clk_i   ( clk_i   ),                           
44.10                         .rst_ni  ( rst_ni ),                           
44.11                         .state_i ( state_d     ),                           
44.12                         .state_o (         )                            
44.13                       );                                                
44.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
44.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
44.16      1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
44.17                       end else begin                                    
44.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
44.19                       end                                               
44.20                     end  
44.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
44.22                       else begin                                                                           
44.23                         `ifdef UVM                                                                               
44.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
44.25                                               "../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv", 44, "", 1);                                
44.26                   `else                                                                                    
44.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
44.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
44.29                   `endif                                                              
44.30                       end 
44.31                     `else                                               
44.32                       prim_sparse_fsm_flop #(                           
44.33                         .StateEnumT(state_e),                            
44.34                         .Width($bits(state_e)),                          
44.35                         .ResetValue($bits(state_e)'(StIdle)),          
44.36                         .EnableAlertTriggerSVA(1)  
44.37                       ) u_state_regs (                                        
44.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
44.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
44.40                         .state_i ( state_d     ),                           
44.41                         .state_o ( state_q     )                            
44.42                       );                                                
44.43                     `endif45                      
46                        logic gen_en;
47         1/1            assign id_en_o = gen_en & id_req_i;
           Tests:       T1 T2 T3 
48         1/1            assign gen_en_o = gen_en & gen_req_i;
           Tests:       T1 T2 T3 
49                      
50                        always_comb begin
51         1/1              state_d = state_q;
           Tests:       T1 T2 T3 
52         1/1              op_update_o = 1'b0;
           Tests:       T1 T2 T3 
53         1/1              op_ack_o = 1'b0;
           Tests:       T1 T2 T3 
54         1/1              op_busy_o = 1'b1;
           Tests:       T1 T2 T3 
55                      
56                          // output to kmac interface
57         1/1              adv_en_o = 1'b0;
           Tests:       T1 T2 T3 
58                      
59         1/1              gen_en = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              op_fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
61                      
62         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
63                            StIdle: begin
64         1/1                  op_busy_o = '0;
           Tests:       T1 T2 T3 
65         1/1                  if (adv_req_i || dis_req_i) begin
           Tests:       T1 T2 T3 
66         1/1                    state_d = StAdv;
           Tests:       T1 T2 T3 
67         1/1                  end else if (id_req_i || gen_req_i) begin
           Tests:       T1 T2 T3 
68         1/1                    state_d = StWait;
           Tests:       T1 T2 T3 
69                              end
                        MISSING_ELSE
70                            end
71                      
72                            StAdv: begin
73         1/1                  adv_en_o = 1'b1;
           Tests:       T1 T2 T3 
74                      
75         1/1                  if (kmac_done_i && (int'(cnt_i) == CDIs-1)) begin
           Tests:       T1 T2 T3 
76         unreachable            op_ack_o = 1'b1;
77         unreachable            state_d = StIdle;
78         1/1                  end else if (kmac_done_i && (int'(cnt_i) < CDIs-1)) begin
           Tests:       T1 T2 T3 
79         1/1                    op_update_o = 1'b1;
           Tests:       T1 T2 T3 
80         1/1                    state_d = StAdvAck;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                      
84                            // drop adv_en_o to allow kmac interface handshake
85                            StAdvAck: begin
86         1/1                  state_d = StAdv;
           Tests:       T1 T2 T3 
87                            end
88                      
89                            // Not an advanced operation
90                            StWait: begin
91         1/1                  gen_en = 1'b1;
           Tests:       T1 T2 T3 
92                      
93         1/1                  if (kmac_done_i) begin
           Tests:       T1 T2 T3 
94         1/1                    op_ack_o = 1'b1;
           Tests:       T1 T2 T3 
95         1/1                    state_d = StIdle;
           Tests:       T1 T2 T3 
96                              end
                        MISSING_ELSE
97                            end
98                      
99                            // error state
100                           default: begin
101                             // allow completion of transaction
102                             op_ack_o = 1'b1;
103                             op_fsm_err_o = 1'b1;

---

Cond Coverage for Module : keymgr_op_state_ctrl

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (gen_en & id_req_i)
             ---1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       48
 EXPRESSION (gen_en & gen_req_i)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       65
 EXPRESSION (adv_req_i || dis_req_i)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T138,T72
1	0	Covered	T1,T2,T3

 LINE       67
 EXPRESSION (id_req_i || gen_req_i)
             ----1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5

 LINE       75
 EXPRESSION (kmac_done_i && (int'(cnt_i) == (keymgr_pkg::CDIs - 1)))
             -----1-----    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       75
 SUB-EXPRESSION (int'(cnt_i) == (keymgr_pkg::CDIs - 1))
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       78
 EXPRESSION (kmac_done_i && (int'(cnt_i) < (keymgr_pkg::CDIs - 1)))
             -----1-----    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : keymgr_op_state_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StAdv	66	Covered	T1,T2,T3
StAdvAck	80	Covered	T1,T2,T3
StIdle	77	Covered	T1,T2,T3
StWait	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StAdv->StAdvAck	80	Covered	T1,T2,T3
StAdv->StIdle	77	Covered	T1,T2,T3
StAdvAck->StAdv	86	Covered	T1,T2,T3
StIdle->StAdv	66	Covered	T1,T2,T3
StIdle->StWait	68	Covered	T1,T2,T3
StWait->StIdle	95	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_op_state_ctrl

	Line No.	Total	Covered	Percent
Branches		11	11	100.00
IF	44	2	2	100.00
CASE	62	9	9	100.00

44           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

62             unique case (state_q)
                      -1-  
63               StIdle: begin
64                 op_busy_o = '0;
65                 if (adv_req_i || dis_req_i) begin
                   -2-  
66                   state_d = StAdv;
                     ==>
67                 end else if (id_req_i || gen_req_i) begin
                            -3-  
68                   state_d = StWait;
                     ==>
69                 end
                   MISSING_ELSE
                   ==>
70               end
71         
72               StAdv: begin
73                 adv_en_o = 1'b1;
74         
75                 if (kmac_done_i && (int'(cnt_i) == CDIs-1)) begin
                   -4-  
76                   op_ack_o = 1'b1;
                     ==> (Unreachable)
77                   state_d = StIdle;
78                 end else if (kmac_done_i && (int'(cnt_i) < CDIs-1)) begin
                            -5-  
79                   op_update_o = 1'b1;
                     ==>
80                   state_d = StAdvAck;
81                 end
                   MISSING_ELSE
                   ==>
82               end
83         
84               // drop adv_en_o to allow kmac interface handshake
85               StAdvAck: begin
86                 state_d = StAdv;
                   ==>
87               end
88         
89               // Not an advanced operation
90               StWait: begin
91                 gen_en = 1'b1;
92         
93                 if (kmac_done_i) begin
                   -6-  
94                   op_ack_o = 1'b1;
                     ==>
95                   state_d = StIdle;
96                 end
                   MISSING_ELSE
                   ==>
97               end
98         
99               // error state
100              default: begin
101                // allow completion of transaction
102                op_ack_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	Covered	T1,T2,T3
StIdle	0	0	-	-	-	Covered	T1,T2,T3
StAdv	-	-	1	-	-	Unreachable	T1,T2,T3
StAdv	-	-	0	1	-	Covered	T1,T2,T3
StAdv	-	-	0	0	-	Covered	T1,T2,T3
StAdvAck	-	-	-	-	-	Covered	T1,T2,T3
StWait	-	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T11,T12,T13

---

Assert Coverage for Module : keymgr_op_state_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	17939074	17765794	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939074	17765794	0	0
T1	5488	5396	0	0
T2	8870	8784	0	0
T3	4862	4799	0	0
T4	9340	9245	0	0
T5	4830	4708	0	0
T14	7224	7145	0	0
T15	9829	9742	0	0
T16	11443	11304	0	0
T17	2203	2140	0	0
T18	19957	19876	0	0