Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19832108	19461	0	0
attest_sw_binding_0_rd_A	19832108	3946	0	0
attest_sw_binding_1_rd_A	19832108	4171	0	0
attest_sw_binding_2_rd_A	19832108	4127	0	0
attest_sw_binding_3_rd_A	19832108	4212	0	0
attest_sw_binding_4_rd_A	19832108	4064	0	0
attest_sw_binding_5_rd_A	19832108	3983	0	0
attest_sw_binding_6_rd_A	19832108	4055	0	0
attest_sw_binding_7_rd_A	19832108	3868	0	0
intr_enable_rd_A	19832108	4482	0	0
key_version_rd_A	19832108	3951	0	0
max_creator_key_ver_regwen_rd_A	19832108	4019	0	0
max_owner_int_key_ver_regwen_rd_A	19832108	3907	0	0
max_owner_key_ver_regwen_rd_A	19832108	4200	0	0
reseed_interval_regwen_rd_A	19832108	3950	0	0
salt_0_rd_A	19832108	3935	0	0
salt_1_rd_A	19832108	3975	0	0
salt_2_rd_A	19832108	4026	0	0
salt_3_rd_A	19832108	4032	0	0
salt_4_rd_A	19832108	4004	0	0
salt_5_rd_A	19832108	4068	0	0
salt_6_rd_A	19832108	4048	0	0
salt_7_rd_A	19832108	3998	0	0
sealing_sw_binding_0_rd_A	19832108	4123	0	0
sealing_sw_binding_1_rd_A	19832108	4225	0	0
sealing_sw_binding_2_rd_A	19832108	4129	0	0
sealing_sw_binding_3_rd_A	19832108	4096	0	0
sealing_sw_binding_4_rd_A	19832108	3972	0	0
sealing_sw_binding_5_rd_A	19832108	4102	0	0
sealing_sw_binding_6_rd_A	19832108	4033	0	0
sealing_sw_binding_7_rd_A	19832108	4149	0	0
sideload_clear_rd_A	19832108	4014	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	19461	0	0
T11	48704	0	0	0
T12	39866	0	0	0
T65	30983	323	0	0
T66	26032	54	0	0
T72	2169	0	0	0
T73	20812	0	0	0
T74	2803	0	0	0
T78	0	855	0	0
T90	0	335	0	0
T91	0	1173	0	0
T92	0	318	0	0
T93	0	1213	0	0
T94	0	251	0	0
T95	0	954	0	0
T96	14076	0	0	0
T97	4189	0	0	0
T98	12765	0	0	0
T99	0	1349	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3946	0	0
T50	28253	0	0	0
T86	0	140	0	0
T115	0	9	0	0
T148	64247	12	0	0
T161	0	6	0	0
T185	0	60	0	0
T186	0	24	0	0
T187	0	24	0	0
T188	0	50	0	0
T189	0	6	0	0
T190	0	8	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4171	0	0
T50	28253	0	0	0
T86	0	124	0	0
T115	0	26	0	0
T148	64247	44	0	0
T161	0	8	0	0
T185	0	37	0	0
T186	0	18	0	0
T187	0	30	0	0
T188	0	55	0	0
T189	0	2	0	0
T190	0	21	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4127	0	0
T50	28253	0	0	0
T86	0	93	0	0
T115	0	30	0	0
T148	64247	34	0	0
T161	0	2	0	0
T185	0	34	0	0
T186	0	35	0	0
T187	0	30	0	0
T188	0	64	0	0
T189	0	3	0	0
T190	0	10	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4212	0	0
T50	28253	0	0	0
T86	0	108	0	0
T115	0	62	0	0
T148	64247	58	0	0
T161	0	5	0	0
T185	0	26	0	0
T186	0	44	0	0
T187	0	37	0	0
T188	0	71	0	0
T189	0	6	0	0
T190	0	10	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4064	0	0
T50	28253	0	0	0
T86	0	121	0	0
T115	0	17	0	0
T148	64247	42	0	0
T161	0	7	0	0
T185	0	18	0	0
T186	0	27	0	0
T187	0	50	0	0
T188	0	38	0	0
T189	0	4	0	0
T190	0	19	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3983	0	0
T50	28253	0	0	0
T86	0	100	0	0
T115	0	26	0	0
T118	0	46	0	0
T148	64247	41	0	0
T161	0	7	0	0
T185	0	30	0	0
T186	0	22	0	0
T187	0	28	0	0
T188	0	58	0	0
T190	0	1	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4055	0	0
T50	28253	0	0	0
T86	0	124	0	0
T115	0	9	0	0
T118	0	57	0	0
T148	64247	37	0	0
T161	0	7	0	0
T185	0	32	0	0
T186	0	24	0	0
T187	0	25	0	0
T188	0	50	0	0
T189	0	8	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3868	0	0
T50	28253	0	0	0
T115	0	12	0	0
T148	64247	29	0	0
T161	0	11	0	0
T185	0	26	0	0
T186	0	23	0	0
T187	0	24	0	0
T188	0	48	0	0
T189	0	7	0	0
T190	0	8	0	0
T191	44246	0	0	0
T192	32839	9	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4482	0	0
T51	11488	0	0	0
T64	1421	0	0	0
T70	60524	32	0	0
T105	2890	0	0	0
T131	5882	0	0	0
T139	0	30	0	0
T148	0	36	0	0
T154	15587	0	0	0
T155	15992	0	0	0
T185	0	23	0	0
T186	0	32	0	0
T187	0	33	0	0
T199	0	41	0	0
T200	0	11	0	0
T201	0	37	0	0
T202	0	13	0	0
T203	69456	0	0	0
T204	4452	0	0	0
T205	6081	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3951	0	0
T50	28253	0	0	0
T86	0	103	0	0
T115	0	25	0	0
T118	0	59	0	0
T120	0	61	0	0
T148	64247	37	0	0
T161	0	11	0	0
T185	0	43	0	0
T186	0	31	0	0
T187	0	43	0	0
T188	0	46	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4019	0	0
T50	28253	0	0	0
T86	0	96	0	0
T115	0	26	0	0
T148	64247	37	0	0
T161	0	7	0	0
T185	0	48	0	0
T186	0	26	0	0
T187	0	37	0	0
T188	0	80	0	0
T189	0	5	0	0
T190	0	7	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3907	0	0
T50	28253	0	0	0
T86	0	99	0	0
T115	0	5	0	0
T118	0	39	0	0
T148	64247	17	0	0
T161	0	14	0	0
T185	0	28	0	0
T186	0	30	0	0
T187	0	27	0	0
T188	0	43	0	0
T190	0	11	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4200	0	0
T50	28253	0	0	0
T86	0	126	0	0
T115	0	24	0	0
T148	64247	28	0	0
T161	0	8	0	0
T185	0	34	0	0
T186	0	28	0	0
T187	0	40	0	0
T188	0	69	0	0
T189	0	9	0	0
T190	0	15	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3950	0	0
T50	28253	0	0	0
T86	0	113	0	0
T115	0	15	0	0
T148	64247	44	0	0
T161	0	5	0	0
T185	0	26	0	0
T186	0	20	0	0
T187	0	28	0	0
T188	0	63	0	0
T189	0	3	0	0
T190	0	20	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3935	0	0
T50	28253	0	0	0
T86	0	119	0	0
T115	0	39	0	0
T148	64247	19	0	0
T161	0	5	0	0
T185	0	44	0	0
T186	0	18	0	0
T187	0	26	0	0
T188	0	40	0	0
T189	0	8	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0
T206	0	2	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3975	0	0
T50	28253	0	0	0
T86	0	123	0	0
T115	0	23	0	0
T148	64247	25	0	0
T161	0	1	0	0
T185	0	31	0	0
T186	0	33	0	0
T187	0	9	0	0
T188	0	26	0	0
T189	0	1	0	0
T190	0	16	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4026	0	0
T86	0	82	0	0
T110	5109	0	0	0
T111	7121	0	0	0
T115	0	26	0	0
T142	9855	0	0	0
T148	0	32	0	0
T161	0	14	0	0
T185	0	31	0	0
T186	0	30	0	0
T187	0	26	0	0
T188	0	56	0	0
T189	0	9	0	0
T207	42691	2	0	0
T208	5603	0	0	0
T209	17959	0	0	0
T210	3848	0	0	0
T211	10181	0	0	0
T212	8303	0	0	0
T213	1248	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4032	0	0
T50	28253	0	0	0
T86	0	91	0	0
T115	0	48	0	0
T148	64247	43	0	0
T161	0	10	0	0
T185	0	34	0	0
T186	0	18	0	0
T187	0	30	0	0
T188	0	62	0	0
T189	0	7	0	0
T190	0	13	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4004	0	0
T50	28253	0	0	0
T86	0	77	0	0
T115	0	26	0	0
T118	0	67	0	0
T148	64247	33	0	0
T161	0	13	0	0
T185	0	47	0	0
T186	0	27	0	0
T187	0	25	0	0
T188	0	64	0	0
T190	0	4	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4068	0	0
T50	28253	0	0	0
T86	0	110	0	0
T115	0	16	0	0
T148	64247	29	0	0
T161	0	12	0	0
T185	0	30	0	0
T186	0	28	0	0
T187	0	27	0	0
T188	0	41	0	0
T189	0	9	0	0
T190	0	6	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4048	0	0
T50	28253	0	0	0
T86	0	118	0	0
T115	0	35	0	0
T148	64247	18	0	0
T161	0	9	0	0
T185	0	50	0	0
T186	0	40	0	0
T187	0	13	0	0
T188	0	55	0	0
T189	0	3	0	0
T190	0	14	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3998	0	0
T50	28253	0	0	0
T86	0	101	0	0
T115	0	14	0	0
T148	64247	39	0	0
T161	0	8	0	0
T185	0	43	0	0
T186	0	35	0	0
T187	0	21	0	0
T188	0	46	0	0
T189	0	2	0	0
T190	0	21	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4123	0	0
T50	28253	0	0	0
T86	0	115	0	0
T115	0	32	0	0
T148	64247	34	0	0
T161	0	4	0	0
T185	0	18	0	0
T186	0	33	0	0
T187	0	22	0	0
T188	0	76	0	0
T189	0	8	0	0
T190	0	26	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4225	0	0
T50	28253	0	0	0
T86	0	128	0	0
T115	0	36	0	0
T148	64247	29	0	0
T161	0	11	0	0
T185	0	37	0	0
T186	0	21	0	0
T187	0	11	0	0
T188	0	39	0	0
T189	0	5	0	0
T190	0	2	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4129	0	0
T50	28253	0	0	0
T86	0	91	0	0
T118	0	56	0	0
T120	0	41	0	0
T148	64247	47	0	0
T161	0	10	0	0
T185	0	44	0	0
T186	0	33	0	0
T187	0	25	0	0
T188	0	70	0	0
T190	0	11	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4096	0	0
T50	28253	0	0	0
T86	0	90	0	0
T115	0	3	0	0
T148	64247	49	0	0
T161	0	9	0	0
T185	0	26	0	0
T186	0	32	0	0
T187	0	46	0	0
T188	0	51	0	0
T189	0	3	0	0
T190	0	10	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	3972	0	0
T50	28253	0	0	0
T86	0	115	0	0
T118	0	42	0	0
T120	0	30	0	0
T148	64247	32	0	0
T161	0	8	0	0
T185	0	28	0	0
T186	0	21	0	0
T187	0	27	0	0
T188	0	48	0	0
T190	0	26	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4102	0	0
T50	28253	0	0	0
T86	0	99	0	0
T115	0	34	0	0
T148	64247	24	0	0
T161	0	6	0	0
T185	0	39	0	0
T186	0	36	0	0
T187	0	36	0	0
T188	0	79	0	0
T189	0	9	0	0
T190	0	4	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4033	0	0
T50	28253	0	0	0
T86	0	127	0	0
T115	0	11	0	0
T148	64247	20	0	0
T161	0	5	0	0
T185	0	25	0	0
T186	0	19	0	0
T187	0	20	0	0
T188	0	55	0	0
T189	0	3	0	0
T190	0	9	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4149	0	0
T50	28253	0	0	0
T86	0	96	0	0
T115	0	26	0	0
T148	64247	41	0	0
T161	0	11	0	0
T185	0	64	0	0
T186	0	27	0	0
T187	0	30	0	0
T188	0	63	0	0
T189	0	2	0	0
T190	0	27	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19832108	4014	0	0
T50	28253	0	0	0
T86	0	107	0	0
T115	0	24	0	0
T118	0	38	0	0
T148	64247	34	0	0
T161	0	13	0	0
T185	0	29	0	0
T186	0	23	0	0
T187	0	31	0	0
T188	0	56	0	0
T190	0	19	0	0
T191	44246	0	0	0
T192	32839	0	0	0
T193	1268	0	0	0
T194	4782	0	0	0
T195	10424	0	0	0
T196	13494	0	0	0
T197	20637	0	0	0
T198	3901	0	0	0