Unified Coverage Report :: Module

Module : keymgr_reseed_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	100.00	93.33			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reseed_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reseed_ctrl	97.78	100.00	93.33			100.00

Module Instance : tb.dut.u_reseed_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	100.00	93.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	92.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_edn_req	97.96	100.00	91.84			100.00	100.00
u_reseed_cnt	100.00			100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_reseed_ctrl

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	49	6	6	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	86	4	4	100.00



42                      
43         1/1            assign edn_done = edn_req & edn_ack;
           Tests:       T1 T2 T3 
44                      
45                        // An edn request can either come from counter or from external
46         1/1            assign local_req = reseed_cnt >= reseed_interval_i;
           Tests:       T1 T2 T3 
47                      
48                        always_ff @(posedge clk_i or negedge rst_ni) begin
49         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
50         1/1                edn_req <= '0;
           Tests:       T1 T2 T3 
51         1/1              end else if (edn_done) begin
           Tests:       T1 T2 T3 
52         1/1                edn_req <= '0;
           Tests:       T1 T2 T3 
53         1/1              end else if (!edn_req && (reseed_req_i || local_req)) begin
           Tests:       T1 T2 T3 
54                            // if edn request is not going, make a new request
55         1/1                edn_req <= 1'b1;
           Tests:       T1 T2 T3 
56                          end
                        MISSING_ELSE
57                        end
58                      
59         1/1            assign seed_en_o = edn_ack;
           Tests:       T1 T2 T3 
60         1/1            assign reseed_ack_o = reseed_req_i & edn_ack;
           Tests:       T1 T2 T3 
61         1/1            assign reseed_done_o = edn_done;
           Tests:       T1 T2 T3 
62                      
63                        prim_edn_req #(
64                          .OutWidth(LfsrWidth)
65                        ) u_edn_req (
66                          .clk_i,
67                          .rst_ni,
68                          .req_chk_i(1'b1),
69                          .req_i(edn_req),
70                          .ack_o(edn_ack),
71                          .data_o(seed_o),
72                          .fips_o(),
73                          .err_o(),
74                          .clk_edn_i,
75                          .rst_edn_ni,
76                          .edn_o,
77                          .edn_i
78                        );
79                      
80                      
81                        // suppress first reseed count until the first transaction has gone through.
82                        // This ensures the first entropy fetch is controlled by software timing and
83                        // there is no chance to accidentally pick-up boot time entropy unless intended by software.
84                        logic cnt_en;
85                        always_ff @(posedge clk_i or negedge rst_ni) begin
86         1/1               if (!rst_ni) begin
           Tests:       T1 T2 T3 
87         1/1                 cnt_en <= '0;
           Tests:       T1 T2 T3 
88         1/1               end else if (edn_done) begin
           Tests:       T1 T2 T3 
89         1/1                 cnt_en <= 1'b1;
           Tests:       T1 T2 T3 
90                           end
                        MISSING_ELSE

Cond Coverage for Module : keymgr_reseed_ctrl

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (edn_req & edn_ack)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       53
 EXPRESSION (((!edn_req)) && (reseed_req_i || local_req))
             ------1-----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       53
 SUB-EXPRESSION (reseed_req_i || local_req)
                 ------1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3

 LINE       60
 EXPRESSION (reseed_req_i & edn_ack)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (cnt_en & lfsr_en_i)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Module : keymgr_reseed_ctrl

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	49	4	4	100.00
IF	86	3	3	100.00



49             if (!rst_ni) begin
               -1-  
50               edn_req <= '0;
                 ==>
51             end else if (edn_done) begin
                        -2-  
52               edn_req <= '0;
                 ==>
53             end else if (!edn_req && (reseed_req_i || local_req)) begin
                        -3-  
54               // if edn request is not going, make a new request
55               edn_req <= 1'b1;
                 ==>
56             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



86              if (!rst_ni) begin
                -1-  
87                cnt_en <= '0;
                  ==>
88              end else if (edn_done) begin
                         -2-  
89                cnt_en <= 1'b1;
                  ==>
90              end
                MISSING_ELSE
                ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3