Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2847304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

604113

1

T1

121

T2

132

T3

167

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3034309	1			T1	403		T2	705		T3	356
values[0x0]	207060	1			T1	45		T2	40		T3	55
values[0x1]	210048	1			T1	33		T2	39		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1954167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1497250

1

T1

205

T2

322

T3

235

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10891	1			T1	4		T2	2		T4	2
valid_sources[0x01]	11144	1			T1	3		T2	2		T4	2
valid_sources[0x02]	11499	1			T2	6		T3	1		T4	4
valid_sources[0x03]	10451	1			T1	3		T2	4		T4	9
valid_sources[0x04]	10027	1			T1	1		T2	3		T4	9
valid_sources[0x05]	11277	1			T1	3		T2	1		T3	5
valid_sources[0x06]	11206	1			T2	1		T4	1		T6	9
valid_sources[0x07]	16397	1			T1	1		T2	2		T4	4
valid_sources[0x08]	11020	1			T1	1		T2	1		T4	7
valid_sources[0x09]	11729	1			T1	9		T2	3		T4	4
valid_sources[0x0a]	11464	1			T1	1		T2	1		T4	3
valid_sources[0x0b]	10391	1			T1	3		T2	2		T4	4
valid_sources[0x0c]	15429	1			T1	3		T2	4		T4	14
valid_sources[0x0d]	10193	1			T1	1		T2	2		T3	14
valid_sources[0x0e]	11392	1			T1	2		T2	4		T4	3
valid_sources[0x0f]	12017	1			T1	3		T2	4		T4	7
valid_sources[0x10]	10595	1			T3	6		T4	5		T6	6
valid_sources[0x11]	12834	1			T1	4		T2	4		T3	21
valid_sources[0x12]	10461	1			T1	1		T2	3		T4	14
valid_sources[0x13]	12786	1			T1	1		T2	2		T4	3
valid_sources[0x14]	15988	1			T2	5		T4	5		T6	4
valid_sources[0x15]	36688	1			T1	3		T2	5		T4	5
valid_sources[0x16]	10805	1			T2	4		T4	5		T6	5
valid_sources[0x17]	9973	1			T1	1		T2	3		T3	6
valid_sources[0x18]	10167	1			T1	2		T2	3		T4	2
valid_sources[0x19]	9622	1			T1	1		T2	1		T4	3
valid_sources[0x1a]	10133	1			T2	1		T4	3		T6	4
valid_sources[0x1b]	10395	1			T1	2		T2	2		T4	3
valid_sources[0x1c]	10620	1			T1	1		T2	4		T4	5
valid_sources[0x1d]	10014	1			T2	2		T6	5		T5	3
valid_sources[0x1e]	11224	1			T2	3		T4	5		T6	2
valid_sources[0x1f]	10753	1			T2	2		T4	9		T6	7
valid_sources[0x20]	11185	1			T2	2		T4	4		T6	6
valid_sources[0x21]	10320	1			T1	2		T2	3		T4	9
valid_sources[0x22]	10875	1			T1	2		T2	3		T3	51
valid_sources[0x23]	12656	1			T1	4		T2	2		T4	9
valid_sources[0x24]	10208	1			T2	3		T3	5		T4	4
valid_sources[0x25]	9691	1			T1	1		T2	6		T4	7
valid_sources[0x26]	10735	1			T2	1		T4	1		T6	5
valid_sources[0x27]	10848	1			T1	4		T2	5		T4	7
valid_sources[0x28]	12609	1			T1	5		T2	4		T3	2
valid_sources[0x29]	11463	1			T1	2		T2	2		T4	7
valid_sources[0x2a]	13237	1			T1	2		T2	1		T4	2
valid_sources[0x2b]	10836	1			T1	2		T2	5		T4	5
valid_sources[0x2c]	13819	1			T1	2		T2	6		T4	3
valid_sources[0x2d]	11441	1			T1	2		T2	4		T4	8
valid_sources[0x2e]	10294	1			T1	1		T2	7		T4	3
valid_sources[0x2f]	10047	1			T1	2		T2	2		T3	10
valid_sources[0x30]	9472	1			T2	4		T3	4		T4	11
valid_sources[0x31]	34209	1			T1	2		T2	4		T4	9
valid_sources[0x32]	11010	1			T1	1		T2	3		T4	6
valid_sources[0x33]	9998	1			T1	4		T2	3		T3	9
valid_sources[0x34]	15296	1			T1	6		T2	4		T4	5
valid_sources[0x35]	10440	1			T1	4		T2	1		T4	7
valid_sources[0x36]	11736	1			T1	3		T2	3		T4	7
valid_sources[0x37]	10355	1			T1	5		T2	5		T4	8
valid_sources[0x38]	31959	1			T2	3		T4	6		T6	1
valid_sources[0x39]	10088	1			T1	1		T2	2		T4	8
valid_sources[0x3a]	10825	1			T1	3		T2	1		T3	4
valid_sources[0x3b]	10076	1			T1	7		T2	2		T4	5
valid_sources[0x3c]	10122	1			T1	1		T2	1		T4	5
valid_sources[0x3d]	10397	1			T1	2		T2	2		T4	4
valid_sources[0x3e]	9439	1			T1	2		T2	1		T4	2
valid_sources[0x3f]	10739	1			T1	2		T2	4		T4	5
valid_sources[0x40]	10274	1			T1	2		T2	3		T3	12
valid_sources[0x41]	11334	1			T2	5		T4	7		T6	3
valid_sources[0x42]	11170	1			T1	1		T2	4		T4	4
valid_sources[0x43]	25775	1			T1	1		T2	2		T4	6
valid_sources[0x44]	15148	1			T2	3		T4	8		T6	9
valid_sources[0x45]	11572	1			T1	5		T2	1		T3	29
valid_sources[0x46]	11266	1			T1	3		T2	4		T4	2
valid_sources[0x47]	11474	1			T1	1		T2	5		T3	2
valid_sources[0x48]	10535	1			T2	2		T4	14		T6	2
valid_sources[0x49]	14015	1			T1	1		T2	1		T4	7
valid_sources[0x4a]	13584	1			T1	2		T2	2		T3	25
valid_sources[0x4b]	11164	1			T1	2		T2	6		T4	4
valid_sources[0x4c]	280552	1			T1	1		T2	4		T4	4
valid_sources[0x4d]	11813	1			T1	3		T2	3		T4	8
valid_sources[0x4e]	15329	1			T2	4		T4	1		T6	2
valid_sources[0x4f]	10442	1			T2	6		T4	9		T6	4
valid_sources[0x50]	10332	1			T1	2		T2	6		T4	12
valid_sources[0x51]	11124	1			T2	7		T3	3		T4	1
valid_sources[0x52]	10781	1			T1	3		T2	7		T4	7
valid_sources[0x53]	11607	1			T1	1		T2	6		T4	5
valid_sources[0x54]	11156	1			T2	4		T3	18		T4	5
valid_sources[0x55]	9897	1			T1	3		T2	1		T4	5
valid_sources[0x56]	33984	1			T1	3		T2	4		T3	3
valid_sources[0x57]	11381	1			T1	3		T2	1		T4	11
valid_sources[0x58]	11438	1			T1	2		T2	2		T4	8
valid_sources[0x59]	10165	1			T1	1		T2	7		T4	4
valid_sources[0x5a]	10784	1			T1	1		T4	3		T6	5
valid_sources[0x5b]	11171	1			T1	3		T2	2		T4	3
valid_sources[0x5c]	10252	1			T2	4		T4	5		T6	8
valid_sources[0x5d]	16677	1			T1	1		T2	7		T4	3
valid_sources[0x5e]	9583	1			T1	2		T2	2		T4	2
valid_sources[0x5f]	10279	1			T1	2		T2	5		T4	1
valid_sources[0x60]	10643	1			T1	3		T2	3		T4	6
valid_sources[0x61]	12241	1			T1	1		T2	6		T4	10
valid_sources[0x62]	10023	1			T1	1		T2	4		T4	6
valid_sources[0x63]	10225	1			T1	3		T2	1		T4	1
valid_sources[0x64]	12822	1			T1	1		T2	5		T4	5
valid_sources[0x65]	9974	1			T1	2		T2	4		T3	22
valid_sources[0x66]	9912	1			T1	1		T2	4		T4	7
valid_sources[0x67]	10339	1			T1	5		T4	1		T6	5
valid_sources[0x68]	10902	1			T1	1		T2	4		T4	6
valid_sources[0x69]	10845	1			T1	1		T2	7		T4	12
valid_sources[0x6a]	11281	1			T1	2		T2	1		T4	9
valid_sources[0x6b]	10867	1			T1	1		T2	4		T6	3
valid_sources[0x6c]	10899	1			T1	2		T2	1		T3	2
valid_sources[0x6d]	10521	1			T1	1		T2	5		T4	11
valid_sources[0x6e]	10792	1			T1	2		T2	3		T4	1
valid_sources[0x6f]	13927	1			T1	2		T2	3		T3	10
valid_sources[0x70]	12099	1			T1	1		T2	2		T4	5
valid_sources[0x71]	10753	1			T1	2		T2	3		T3	47
valid_sources[0x72]	16666	1			T1	2		T2	3		T4	3
valid_sources[0x73]	13355	1			T1	2		T2	4		T4	7
valid_sources[0x74]	9755	1			T1	2		T2	5		T4	9
valid_sources[0x75]	11474	1			T1	3		T2	1		T4	2
valid_sources[0x76]	10457	1			T1	3		T2	7		T4	4
valid_sources[0x77]	10964	1			T1	3		T2	4		T4	1
valid_sources[0x78]	11076	1			T2	3		T4	1		T6	2
valid_sources[0x79]	42443	1			T2	5		T4	4		T6	3
valid_sources[0x7a]	10602	1			T1	2		T2	2		T4	11
valid_sources[0x7b]	16484	1			T1	2		T2	3		T4	6
valid_sources[0x7c]	11416	1			T1	6		T2	4		T4	3
valid_sources[0x7d]	10301	1			T1	1		T2	5		T4	8
valid_sources[0x7e]	11243	1			T1	4		T2	2		T4	7
valid_sources[0x7f]	11401	1			T1	2		T2	2		T4	9
valid_sources[0x80]	10872	1			T1	3		T2	1		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319969

1

T1

99

T2

114

T3

144

values[0x0]

all_enables

biggest_size

149535

1

T1

15

T2

13

T3

18

values[0x1]

all_enables

biggest_size

134609

1

T1

7

T2

5

T3

5