Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22658735	19453	0	0
attest_sw_binding_0_rd_A	22658735	1917	0	0
attest_sw_binding_1_rd_A	22658735	1911	0	0
attest_sw_binding_2_rd_A	22658735	1888	0	0
attest_sw_binding_3_rd_A	22658735	1632	0	0
attest_sw_binding_4_rd_A	22658735	1706	0	0
attest_sw_binding_5_rd_A	22658735	1717	0	0
attest_sw_binding_6_rd_A	22658735	2010	0	0
attest_sw_binding_7_rd_A	22658735	1792	0	0
intr_enable_rd_A	22658735	2656	0	0
key_version_rd_A	22658735	1934	0	0
max_creator_key_ver_regwen_rd_A	22658735	1983	0	0
max_owner_int_key_ver_regwen_rd_A	22658735	1736	0	0
max_owner_key_ver_regwen_rd_A	22658735	1859	0	0
reseed_interval_regwen_rd_A	22658735	1853	0	0
salt_0_rd_A	22658735	1911	0	0
salt_1_rd_A	22658735	1833	0	0
salt_2_rd_A	22658735	1734	0	0
salt_3_rd_A	22658735	1731	0	0
salt_4_rd_A	22658735	1841	0	0
salt_5_rd_A	22658735	1930	0	0
salt_6_rd_A	22658735	1758	0	0
salt_7_rd_A	22658735	1815	0	0
sealing_sw_binding_0_rd_A	22658735	1744	0	0
sealing_sw_binding_1_rd_A	22658735	1981	0	0
sealing_sw_binding_2_rd_A	22658735	1734	0	0
sealing_sw_binding_3_rd_A	22658735	1877	0	0
sealing_sw_binding_4_rd_A	22658735	1926	0	0
sealing_sw_binding_5_rd_A	22658735	1866	0	0
sealing_sw_binding_6_rd_A	22658735	1746	0	0
sealing_sw_binding_7_rd_A	22658735	1925	0	0
sideload_clear_rd_A	22658735	1785	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	19453	0	0
T19	19685	0	0	0
T36	8356	0	0	0
T66	13426	683	0	0
T69	0	76	0	0
T70	0	667	0	0
T93	0	149	0	0
T94	0	280	0	0
T95	0	252	0	0
T96	0	82	0	0
T97	0	1023	0	0
T98	0	165	0	0
T99	0	334	0	0
T100	5761	0	0	0
T101	2224	0	0	0
T102	3669	0	0	0
T103	2590	0	0	0
T104	9485	0	0	0
T105	7064	0	0	0
T106	4664	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1917	0	0
T89	0	35	0	0
T93	64998	65	0	0
T98	0	22	0	0
T120	0	22	0	0
T137	10062	0	0	0
T138	0	22	0	0
T153	0	7	0	0
T160	0	3	0	0
T171	14532	0	0	0
T184	0	45	0	0
T185	0	51	0	0
T186	0	159	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1911	0	0
T89	0	41	0	0
T93	64998	69	0	0
T98	0	52	0	0
T120	0	42	0	0
T137	10062	0	0	0
T138	0	18	0	0
T159	0	13	0	0
T171	14532	0	0	0
T184	0	19	0	0
T185	0	62	0	0
T186	0	131	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0
T194	0	2	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1888	0	0
T89	0	31	0	0
T93	64998	68	0	0
T98	0	25	0	0
T120	0	6	0	0
T137	10062	0	0	0
T138	0	37	0	0
T153	0	5	0	0
T159	0	6	0	0
T160	0	6	0	0
T171	14532	0	0	0
T184	0	29	0	0
T185	0	35	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1632	0	0
T89	0	26	0	0
T93	64998	42	0	0
T98	0	30	0	0
T120	0	30	0	0
T137	10062	0	0	0
T138	0	25	0	0
T153	0	5	0	0
T168	0	17	0	0
T171	14532	0	0	0
T184	0	30	0	0
T185	0	39	0	0
T186	0	89	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1706	0	0
T89	0	38	0	0
T93	64998	55	0	0
T98	0	25	0	0
T137	10062	0	0	0
T138	0	20	0	0
T153	0	8	0	0
T159	0	4	0	0
T160	0	6	0	0
T171	14532	0	0	0
T184	0	22	0	0
T185	0	69	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0
T195	0	9	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1717	0	0
T89	0	34	0	0
T93	64998	37	0	0
T98	0	24	0	0
T120	0	7	0	0
T137	10062	0	0	0
T138	0	11	0	0
T153	0	1	0	0
T159	0	10	0	0
T160	0	4	0	0
T171	14532	0	0	0
T184	0	32	0	0
T185	0	38	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	2010	0	0
T89	0	34	0	0
T93	64998	79	0	0
T98	0	33	0	0
T120	0	11	0	0
T137	10062	0	0	0
T138	0	25	0	0
T153	0	3	0	0
T159	0	11	0	0
T171	14532	0	0	0
T184	0	49	0	0
T185	0	18	0	0
T186	0	182	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1792	0	0
T89	0	43	0	0
T93	64998	40	0	0
T98	0	23	0	0
T120	0	18	0	0
T137	10062	0	0	0
T138	0	21	0	0
T153	0	1	0	0
T160	0	2	0	0
T171	14532	0	0	0
T184	0	25	0	0
T185	0	30	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0
T196	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	2656	0	0
T8	7619	0	0	0
T44	7046	0	0	0
T93	0	98	0	0
T98	0	36	0	0
T109	5939	0	0	0
T134	6311	0	0	0
T140	0	42	0	0
T149	0	10	0	0
T151	0	22	0	0
T152	0	113	0	0
T197	97441	17	0	0
T198	0	5	0	0
T199	0	52	0	0
T200	0	30	0	0
T201	1583	0	0	0
T202	14416	0	0	0
T203	3368	0	0	0
T204	68426	0	0	0
T205	8937	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1934	0	0
T89	0	31	0	0
T91	0	278	0	0
T93	64998	64	0	0
T98	0	19	0	0
T137	10062	0	0	0
T138	0	43	0	0
T153	0	1	0	0
T168	0	19	0	0
T171	14532	0	0	0
T184	0	34	0	0
T185	0	52	0	0
T186	0	132	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1983	0	0
T89	0	41	0	0
T93	64998	60	0	0
T98	0	32	0	0
T120	0	39	0	0
T137	10062	0	0	0
T138	0	26	0	0
T153	0	9	0	0
T159	0	7	0	0
T160	0	4	0	0
T171	14532	0	0	0
T184	0	32	0	0
T185	0	41	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1736	0	0
T89	0	21	0	0
T93	64998	56	0	0
T98	0	48	0	0
T120	0	4	0	0
T137	10062	0	0	0
T138	0	23	0	0
T153	0	6	0	0
T159	0	5	0	0
T171	14532	0	0	0
T184	0	23	0	0
T185	0	22	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0
T206	0	3	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1859	0	0
T89	0	36	0	0
T93	64998	64	0	0
T98	0	31	0	0
T120	0	5	0	0
T137	10062	0	0	0
T138	0	32	0	0
T153	0	8	0	0
T159	0	14	0	0
T160	0	1	0	0
T171	14532	0	0	0
T184	0	21	0	0
T185	0	58	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1853	0	0
T89	0	36	0	0
T93	64998	53	0	0
T98	0	17	0	0
T120	0	29	0	0
T137	10062	0	0	0
T138	0	21	0	0
T153	0	6	0	0
T160	0	5	0	0
T171	14532	0	0	0
T184	0	25	0	0
T185	0	64	0	0
T186	0	129	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1911	0	0
T89	0	21	0	0
T93	64998	66	0	0
T98	0	12	0	0
T120	0	2	0	0
T137	10062	0	0	0
T138	0	25	0	0
T159	0	6	0	0
T160	0	2	0	0
T171	14532	0	0	0
T184	0	24	0	0
T185	0	24	0	0
T186	0	147	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1833	0	0
T89	0	25	0	0
T93	64998	45	0	0
T98	0	30	0	0
T120	0	42	0	0
T137	10062	0	0	0
T138	0	38	0	0
T159	0	5	0	0
T168	0	27	0	0
T171	14532	0	0	0
T184	0	7	0	0
T185	0	45	0	0
T186	0	123	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1734	0	0
T89	0	46	0	0
T93	64998	29	0	0
T98	0	35	0	0
T120	0	7	0	0
T137	10062	0	0	0
T138	0	11	0	0
T153	0	1	0	0
T159	0	10	0	0
T160	0	2	0	0
T171	14532	0	0	0
T184	0	40	0	0
T185	0	32	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1731	0	0
T89	0	23	0	0
T93	64998	30	0	0
T98	0	43	0	0
T120	0	39	0	0
T137	10062	0	0	0
T138	0	19	0	0
T153	0	3	0	0
T159	0	6	0	0
T171	14532	0	0	0
T184	0	38	0	0
T185	0	13	0	0
T186	0	144	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1841	0	0
T89	0	26	0	0
T93	64998	35	0	0
T98	0	11	0	0
T137	10062	0	0	0
T138	0	18	0	0
T153	0	9	0	0
T159	0	6	0	0
T160	0	3	0	0
T171	14532	0	0	0
T184	0	27	0	0
T185	0	38	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0
T207	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1930	0	0
T89	0	21	0	0
T93	64998	100	0	0
T98	0	27	0	0
T120	0	9	0	0
T137	10062	0	0	0
T138	0	35	0	0
T153	0	6	0	0
T159	0	9	0	0
T160	0	3	0	0
T171	14532	0	0	0
T184	0	26	0	0
T185	0	32	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1758	0	0
T89	0	42	0	0
T93	64998	53	0	0
T98	0	31	0	0
T120	0	33	0	0
T137	10062	0	0	0
T138	0	17	0	0
T153	0	6	0	0
T159	0	11	0	0
T160	0	6	0	0
T171	14532	0	0	0
T184	0	34	0	0
T185	0	29	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1815	0	0
T89	0	22	0	0
T93	64998	60	0	0
T98	0	30	0	0
T120	0	7	0	0
T137	10062	0	0	0
T138	0	25	0	0
T153	0	7	0	0
T160	0	8	0	0
T171	14532	0	0	0
T184	0	22	0	0
T185	0	14	0	0
T186	0	150	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1744	0	0
T89	0	25	0	0
T93	64998	44	0	0
T98	0	38	0	0
T120	0	7	0	0
T137	10062	0	0	0
T138	0	17	0	0
T153	0	5	0	0
T160	0	3	0	0
T171	14532	0	0	0
T184	0	30	0	0
T185	0	66	0	0
T186	0	135	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1981	0	0
T89	0	37	0	0
T93	64998	45	0	0
T98	0	40	0	0
T120	0	6	0	0
T137	10062	0	0	0
T138	0	38	0	0
T160	0	10	0	0
T168	0	28	0	0
T171	14532	0	0	0
T184	0	40	0	0
T185	0	52	0	0
T186	0	123	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1734	0	0
T89	0	20	0	0
T93	64998	53	0	0
T98	0	27	0	0
T120	0	32	0	0
T137	10062	0	0	0
T138	0	14	0	0
T153	0	10	0	0
T159	0	1	0	0
T160	0	8	0	0
T171	14532	0	0	0
T184	0	21	0	0
T185	0	47	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1877	0	0
T89	0	39	0	0
T91	0	262	0	0
T93	64998	56	0	0
T98	0	31	0	0
T120	0	15	0	0
T137	10062	0	0	0
T138	0	10	0	0
T168	0	26	0	0
T171	14532	0	0	0
T184	0	43	0	0
T185	0	54	0	0
T186	0	169	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1926	0	0
T89	0	35	0	0
T93	64998	63	0	0
T98	0	22	0	0
T120	0	44	0	0
T137	10062	0	0	0
T138	0	42	0	0
T153	0	4	0	0
T159	0	14	0	0
T171	14532	0	0	0
T184	0	29	0	0
T185	0	30	0	0
T186	0	107	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1866	0	0
T89	0	40	0	0
T93	64998	54	0	0
T98	0	18	0	0
T120	0	15	0	0
T137	10062	0	0	0
T138	0	14	0	0
T153	0	8	0	0
T168	0	21	0	0
T171	14532	0	0	0
T184	0	46	0	0
T185	0	47	0	0
T186	0	148	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1746	0	0
T89	0	34	0	0
T93	64998	55	0	0
T98	0	29	0	0
T120	0	8	0	0
T137	10062	0	0	0
T138	0	13	0	0
T159	0	1	0	0
T160	0	2	0	0
T171	14532	0	0	0
T184	0	33	0	0
T185	0	39	0	0
T186	0	154	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1925	0	0
T89	0	23	0	0
T93	64998	60	0	0
T98	0	30	0	0
T120	0	28	0	0
T137	10062	0	0	0
T138	0	24	0	0
T153	0	8	0	0
T159	0	9	0	0
T160	0	7	0	0
T171	14532	0	0	0
T184	0	15	0	0
T185	0	37	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22658735	1785	0	0
T89	0	21	0	0
T93	64998	80	0	0
T98	0	22	0	0
T137	10062	0	0	0
T138	0	30	0	0
T153	0	9	0	0
T160	0	5	0	0
T168	0	32	0	0
T171	14532	0	0	0
T184	0	32	0	0
T185	0	40	0	0
T186	0	110	0	0
T187	1752	0	0	0
T188	50131	0	0	0
T189	2985	0	0	0
T190	5409	0	0	0
T191	12066	0	0	0
T192	12889	0	0	0
T193	4513	0	0	0