Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2938892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

609418

1

T1

277

T2

14

T3

338

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3130572	1			T1	444		T2	2325		T3	615
values[0x0]	207766	1			T1	125		T2	10		T3	74
values[0x1]	209972	1			T1	125		T2	10		T3	78

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2016684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1531626

1

T1

375

T2

737

T3

445

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10907	1			T2	34		T3	17		T14	7
valid_sources[0x01]	12245	1			T2	11		T3	6		T5	2
valid_sources[0x02]	24923	1			T14	5		T17	1		T18	2
valid_sources[0x03]	15397	1			T1	8		T2	3		T3	8
valid_sources[0x04]	14211	1			T2	7		T14	10		T17	6
valid_sources[0x05]	12801	1			T1	5		T2	10		T14	2
valid_sources[0x06]	11502	1			T2	11		T3	2		T14	4
valid_sources[0x07]	21120	1			T1	1		T2	7		T4	1
valid_sources[0x08]	13032	1			T1	9		T2	6		T4	2
valid_sources[0x09]	11143	1			T2	3		T3	11		T14	8
valid_sources[0x0a]	23999	1			T1	6		T2	6		T14	13
valid_sources[0x0b]	12231	1			T2	16		T14	8		T17	8
valid_sources[0x0c]	11874	1			T1	2		T2	4		T3	5
valid_sources[0x0d]	10864	1			T1	4		T2	4		T3	19
valid_sources[0x0e]	10968	1			T1	2		T2	20		T14	11
valid_sources[0x0f]	11163	1			T1	1		T2	18		T4	3
valid_sources[0x10]	11934	1			T2	10		T3	1		T14	10
valid_sources[0x11]	11498	1			T1	6		T2	5		T3	6
valid_sources[0x12]	15648	1			T2	8		T14	2		T17	7
valid_sources[0x13]	12108	1			T2	11		T14	5		T17	2
valid_sources[0x14]	11315	1			T2	5		T3	12		T14	7
valid_sources[0x15]	11291	1			T1	2		T2	4		T3	5
valid_sources[0x16]	15951	1			T1	12		T2	16		T5	3
valid_sources[0x17]	12141	1			T2	3		T3	3		T4	6
valid_sources[0x18]	11115	1			T1	7		T2	11		T4	3
valid_sources[0x19]	13356	1			T1	5		T2	1		T14	7
valid_sources[0x1a]	11781	1			T1	1		T2	18		T3	5
valid_sources[0x1b]	13139	1			T1	5		T2	2		T3	4
valid_sources[0x1c]	23383	1			T2	6		T3	6		T4	4
valid_sources[0x1d]	14722	1			T2	6		T3	13		T14	1
valid_sources[0x1e]	12871	1			T1	4		T2	2		T14	7
valid_sources[0x1f]	13537	1			T1	10		T2	7		T3	9
valid_sources[0x20]	11762	1			T2	8		T14	8		T16	3
valid_sources[0x21]	11677	1			T2	7		T4	2		T14	10
valid_sources[0x22]	14345	1			T2	20		T14	8		T17	5
valid_sources[0x23]	16582	1			T2	9		T4	17		T14	3
valid_sources[0x24]	11147	1			T1	5		T2	2		T14	8
valid_sources[0x25]	11143	1			T1	2		T2	5		T4	8
valid_sources[0x26]	13294	1			T1	2		T2	1		T14	9
valid_sources[0x27]	11896	1			T2	25		T4	2		T5	39
valid_sources[0x28]	10788	1			T1	9		T2	5		T3	6
valid_sources[0x29]	11249	1			T1	2		T2	10		T3	11
valid_sources[0x2a]	11743	1			T1	8		T2	10		T14	7
valid_sources[0x2b]	16673	1			T2	4		T14	4		T17	3
valid_sources[0x2c]	11706	1			T2	12		T3	3		T4	5
valid_sources[0x2d]	10949	1			T2	4		T4	3		T14	5
valid_sources[0x2e]	12363	1			T1	14		T2	2		T14	5
valid_sources[0x2f]	11629	1			T1	6		T2	18		T3	9
valid_sources[0x30]	12398	1			T1	2		T2	6		T14	6
valid_sources[0x31]	11257	1			T1	1		T2	11		T4	2
valid_sources[0x32]	11620	1			T1	1		T2	15		T4	35
valid_sources[0x33]	14038	1			T2	7		T3	1		T5	2
valid_sources[0x34]	12738	1			T1	1		T2	1		T3	3
valid_sources[0x35]	12117	1			T1	1		T2	9		T4	6
valid_sources[0x36]	12544	1			T1	7		T2	22		T14	8
valid_sources[0x37]	12640	1			T2	7		T14	2		T17	3
valid_sources[0x38]	11884	1			T1	10		T2	4		T4	1
valid_sources[0x39]	11283	1			T1	3		T2	20		T4	5
valid_sources[0x3a]	12053	1			T1	3		T2	2		T14	4
valid_sources[0x3b]	31401	1			T2	2		T14	8		T17	1
valid_sources[0x3c]	12739	1			T1	18		T2	4		T5	13
valid_sources[0x3d]	11963	1			T1	3		T2	9		T14	4
valid_sources[0x3e]	53984	1			T1	5		T2	3		T3	10
valid_sources[0x3f]	11380	1			T1	4		T2	14		T14	8
valid_sources[0x40]	10957	1			T1	18		T2	20		T3	3
valid_sources[0x41]	11074	1			T1	2		T2	21		T4	1
valid_sources[0x42]	27082	1			T1	5		T2	11		T3	4
valid_sources[0x43]	12429	1			T2	3		T5	2		T14	6
valid_sources[0x44]	11689	1			T1	1		T2	13		T14	3
valid_sources[0x45]	11286	1			T1	10		T2	10		T4	6
valid_sources[0x46]	13110	1			T1	3		T14	12		T16	2
valid_sources[0x47]	11577	1			T1	9		T2	11		T4	4
valid_sources[0x48]	11047	1			T1	2		T2	5		T3	3
valid_sources[0x49]	12320	1			T1	2		T2	6		T14	7
valid_sources[0x4a]	11129	1			T2	9		T3	5		T14	5
valid_sources[0x4b]	12428	1			T2	6		T14	8		T17	2
valid_sources[0x4c]	10880	1			T2	9		T14	4		T17	2
valid_sources[0x4d]	11431	1			T1	1		T2	20		T4	9
valid_sources[0x4e]	13231	1			T2	4		T4	4		T14	5
valid_sources[0x4f]	12821	1			T1	3		T4	5		T14	7
valid_sources[0x50]	11144	1			T2	12		T3	8		T14	6
valid_sources[0x51]	11639	1			T2	3		T4	15		T14	2
valid_sources[0x52]	15289	1			T2	6		T4	2		T14	3
valid_sources[0x53]	11714	1			T1	5		T2	13		T4	5
valid_sources[0x54]	10800	1			T2	7		T4	5		T14	8
valid_sources[0x55]	53451	1			T1	1		T2	3		T3	8
valid_sources[0x56]	10805	1			T2	27		T3	1		T5	15
valid_sources[0x57]	11488	1			T2	3		T3	13		T14	3
valid_sources[0x58]	11868	1			T3	1		T14	7		T18	2
valid_sources[0x59]	12856	1			T1	5		T2	1		T4	3
valid_sources[0x5a]	11018	1			T1	2		T2	13		T3	3
valid_sources[0x5b]	11271	1			T1	5		T2	3		T4	9
valid_sources[0x5c]	15908	1			T1	3		T2	7		T14	5
valid_sources[0x5d]	11638	1			T1	7		T2	2		T3	7
valid_sources[0x5e]	11305	1			T1	2		T2	26		T3	8
valid_sources[0x5f]	11760	1			T2	8		T3	18		T14	17
valid_sources[0x60]	16363	1			T1	2		T2	29		T14	6
valid_sources[0x61]	12706	1			T1	4		T2	10		T4	8
valid_sources[0x62]	11298	1			T1	6		T2	6		T14	6
valid_sources[0x63]	14593	1			T1	3		T2	13		T14	12
valid_sources[0x64]	12449	1			T1	10		T2	4		T4	18
valid_sources[0x65]	13051	1			T1	3		T2	2		T3	10
valid_sources[0x66]	12854	1			T1	4		T2	16		T3	4
valid_sources[0x67]	15590	1			T1	1		T3	1		T4	2
valid_sources[0x68]	12382	1			T1	1		T2	7		T3	10
valid_sources[0x69]	11869	1			T1	4		T2	9		T14	7
valid_sources[0x6a]	11249	1			T2	6		T3	3		T4	3
valid_sources[0x6b]	20967	1			T1	1		T2	7		T3	5
valid_sources[0x6c]	11571	1			T1	2		T2	6		T3	1
valid_sources[0x6d]	11570	1			T2	4		T4	8		T14	4
valid_sources[0x6e]	10951	1			T1	2		T2	16		T4	8
valid_sources[0x6f]	12757	1			T2	9		T4	7		T14	9
valid_sources[0x70]	10630	1			T1	7		T2	23		T3	18
valid_sources[0x71]	13584	1			T2	4		T3	2		T4	13
valid_sources[0x72]	15483	1			T1	5		T2	2		T4	7
valid_sources[0x73]	15672	1			T1	3		T2	7		T14	2
valid_sources[0x74]	12837	1			T2	10		T4	31		T14	4
valid_sources[0x75]	18224	1			T2	19		T3	1		T4	2
valid_sources[0x76]	11338	1			T2	8		T4	4		T14	10
valid_sources[0x77]	13142	1			T2	13		T3	2		T5	4
valid_sources[0x78]	11030	1			T2	9		T4	1		T14	3
valid_sources[0x79]	11584	1			T1	2		T2	5		T3	10
valid_sources[0x7a]	10888	1			T1	4		T2	5		T4	6
valid_sources[0x7b]	12400	1			T2	25		T4	10		T14	5
valid_sources[0x7c]	15476	1			T1	5		T2	4		T3	1
valid_sources[0x7d]	11024	1			T1	6		T2	22		T3	14
valid_sources[0x7e]	12466	1			T2	5		T5	15		T14	3
valid_sources[0x7f]	11698	1			T2	11		T3	23		T4	3
valid_sources[0x80]	11732	1			T1	3		T2	11		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325085

1

T1

122

T2

8

T3

289

values[0x0]

all_enables

biggest_size

149546

1

T1

93

T2

3

T3

34

values[0x1]

all_enables

biggest_size

134787

1

T1

62

T2

3

T3

15