Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24118787	17297	0	0
attest_sw_binding_0_rd_A	24118787	2620	0	0
attest_sw_binding_1_rd_A	24118787	2698	0	0
attest_sw_binding_2_rd_A	24118787	2740	0	0
attest_sw_binding_3_rd_A	24118787	2752	0	0
attest_sw_binding_4_rd_A	24118787	2745	0	0
attest_sw_binding_5_rd_A	24118787	2735	0	0
attest_sw_binding_6_rd_A	24118787	2597	0	0
attest_sw_binding_7_rd_A	24118787	2718	0	0
intr_enable_rd_A	24118787	3407	0	0
key_version_rd_A	24118787	2749	0	0
max_creator_key_ver_regwen_rd_A	24118787	2590	0	0
max_owner_int_key_ver_regwen_rd_A	24118787	2672	0	0
max_owner_key_ver_regwen_rd_A	24118787	2565	0	0
reseed_interval_regwen_rd_A	24118787	2674	0	0
salt_0_rd_A	24118787	2620	0	0
salt_1_rd_A	24118787	2685	0	0
salt_2_rd_A	24118787	2553	0	0
salt_3_rd_A	24118787	2708	0	0
salt_4_rd_A	24118787	2636	0	0
salt_5_rd_A	24118787	2591	0	0
salt_6_rd_A	24118787	2675	0	0
salt_7_rd_A	24118787	2727	0	0
sealing_sw_binding_0_rd_A	24118787	2745	0	0
sealing_sw_binding_1_rd_A	24118787	2675	0	0
sealing_sw_binding_2_rd_A	24118787	2725	0	0
sealing_sw_binding_3_rd_A	24118787	2673	0	0
sealing_sw_binding_4_rd_A	24118787	2616	0	0
sealing_sw_binding_5_rd_A	24118787	2663	0	0
sealing_sw_binding_6_rd_A	24118787	2683	0	0
sealing_sw_binding_7_rd_A	24118787	2680	0	0
sideload_clear_rd_A	24118787	2799	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	17297	0	0
T6	30928	473	0	0
T59	1198	0	0	0
T63	0	56	0	0
T64	0	232	0	0
T74	0	400	0	0
T86	0	26	0	0
T87	0	1091	0	0
T89	0	80	0	0
T90	0	437	0	0
T91	7476	0	0	0
T92	28439	0	0	0
T93	9097	0	0	0
T94	15842	0	0	0
T95	3055	0	0	0
T96	2480	0	0	0
T97	18037	0	0	0
T98	4961	0	0	0
T101	0	240	0	0
T181	0	483	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2620	0	0
T89	43263	33	0	0
T158	0	6	0	0
T164	0	5	0	0
T168	0	32	0	0
T182	0	15	0	0
T183	0	39	0	0
T184	0	24	0	0
T185	0	37	0	0
T186	0	16	0	0
T187	0	288	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2698	0	0
T89	43263	41	0	0
T158	0	9	0	0
T164	0	9	0	0
T168	0	54	0	0
T182	0	25	0	0
T183	0	17	0	0
T184	0	33	0	0
T185	0	34	0	0
T186	0	26	0	0
T187	0	283	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2740	0	0
T89	43263	52	0	0
T158	0	5	0	0
T164	0	4	0	0
T168	0	30	0	0
T182	0	41	0	0
T183	0	32	0	0
T184	0	33	0	0
T185	0	9	0	0
T186	0	37	0	0
T187	0	265	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2752	0	0
T89	43263	63	0	0
T158	0	8	0	0
T164	0	7	0	0
T168	0	28	0	0
T182	0	35	0	0
T183	0	20	0	0
T184	0	32	0	0
T185	0	17	0	0
T186	0	31	0	0
T187	0	293	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2745	0	0
T89	43263	42	0	0
T158	0	9	0	0
T164	0	3	0	0
T182	0	39	0	0
T183	0	27	0	0
T184	0	38	0	0
T185	0	47	0	0
T186	0	19	0	0
T187	0	228	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T197	0	7	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2735	0	0
T89	43263	52	0	0
T158	0	11	0	0
T164	0	15	0	0
T168	0	46	0	0
T182	0	58	0	0
T183	0	25	0	0
T184	0	17	0	0
T185	0	34	0	0
T186	0	36	0	0
T187	0	247	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2597	0	0
T89	43263	56	0	0
T158	0	2	0	0
T164	0	14	0	0
T168	0	41	0	0
T182	0	48	0	0
T183	0	32	0	0
T184	0	36	0	0
T185	0	21	0	0
T186	0	39	0	0
T187	0	210	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2718	0	0
T89	43263	28	0	0
T158	0	8	0	0
T164	0	7	0	0
T168	0	36	0	0
T182	0	26	0	0
T183	0	23	0	0
T184	0	31	0	0
T185	0	27	0	0
T186	0	21	0	0
T187	0	272	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	3407	0	0
T89	43263	102	0	0
T134	0	4	0	0
T146	0	18	0	0
T182	0	31	0	0
T183	0	27	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T198	0	54	0	0
T199	0	21	0	0
T200	0	40	0	0
T201	0	24	0	0
T202	0	26	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2749	0	0
T89	43263	56	0	0
T158	0	5	0	0
T164	0	9	0	0
T168	0	41	0	0
T182	0	43	0	0
T183	0	28	0	0
T184	0	42	0	0
T185	0	32	0	0
T186	0	30	0	0
T187	0	266	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2590	0	0
T89	43263	67	0	0
T158	0	4	0	0
T164	0	19	0	0
T182	0	32	0	0
T183	0	33	0	0
T184	0	36	0	0
T185	0	41	0	0
T186	0	23	0	0
T187	0	241	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T203	0	3	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2672	0	0
T89	43263	47	0	0
T158	0	16	0	0
T164	0	5	0	0
T168	0	44	0	0
T182	0	33	0	0
T183	0	25	0	0
T184	0	29	0	0
T185	0	31	0	0
T186	0	35	0	0
T187	0	211	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2565	0	0
T89	43263	69	0	0
T158	0	4	0	0
T168	0	38	0	0
T182	0	40	0	0
T183	0	23	0	0
T184	0	22	0	0
T185	0	19	0	0
T186	0	38	0	0
T187	0	244	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T204	0	10	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2674	0	0
T89	43263	47	0	0
T158	0	6	0	0
T164	0	8	0	0
T168	0	35	0	0
T182	0	20	0	0
T183	0	36	0	0
T184	0	33	0	0
T185	0	36	0	0
T186	0	31	0	0
T187	0	252	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2620	0	0
T89	43263	43	0	0
T158	0	7	0	0
T164	0	4	0	0
T168	0	56	0	0
T182	0	8	0	0
T183	0	25	0	0
T184	0	30	0	0
T185	0	13	0	0
T186	0	16	0	0
T187	0	270	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2685	0	0
T89	43263	67	0	0
T158	0	9	0	0
T164	0	8	0	0
T168	0	31	0	0
T182	0	17	0	0
T183	0	41	0	0
T184	0	25	0	0
T185	0	50	0	0
T186	0	33	0	0
T187	0	297	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2553	0	0
T89	43263	47	0	0
T158	0	11	0	0
T164	0	9	0	0
T168	0	45	0	0
T182	0	19	0	0
T183	0	15	0	0
T184	0	46	0	0
T185	0	19	0	0
T186	0	23	0	0
T187	0	250	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2708	0	0
T89	43263	52	0	0
T158	0	10	0	0
T164	0	8	0	0
T168	0	43	0	0
T182	0	41	0	0
T183	0	30	0	0
T184	0	19	0	0
T185	0	30	0	0
T186	0	32	0	0
T187	0	233	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2636	0	0
T27	24474	0	0	0
T42	55204	3	0	0
T89	0	46	0	0
T99	4230	0	0	0
T130	5277	0	0	0
T158	0	2	0	0
T164	0	9	0	0
T182	0	17	0	0
T183	0	49	0	0
T184	0	11	0	0
T185	0	26	0	0
T186	0	24	0	0
T187	0	260	0	0
T205	6255	0	0	0
T206	10929	0	0	0
T207	1167	0	0	0
T208	18323	0	0	0
T209	20925	0	0	0
T210	35986	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2591	0	0
T89	43263	59	0	0
T158	0	15	0	0
T164	0	10	0	0
T182	0	31	0	0
T183	0	33	0	0
T184	0	33	0	0
T185	0	40	0	0
T186	0	15	0	0
T187	0	233	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T211	0	8	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2675	0	0
T89	43263	63	0	0
T158	0	2	0	0
T164	0	2	0	0
T168	0	40	0	0
T182	0	36	0	0
T183	0	12	0	0
T184	0	25	0	0
T185	0	24	0	0
T186	0	29	0	0
T187	0	246	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2727	0	0
T89	43263	54	0	0
T158	0	10	0	0
T164	0	15	0	0
T168	0	46	0	0
T182	0	29	0	0
T183	0	20	0	0
T184	0	37	0	0
T185	0	40	0	0
T186	0	27	0	0
T187	0	258	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2745	0	0
T89	43263	75	0	0
T158	0	4	0	0
T164	0	9	0	0
T168	0	36	0	0
T182	0	24	0	0
T183	0	20	0	0
T184	0	15	0	0
T185	0	34	0	0
T186	0	30	0	0
T187	0	230	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2675	0	0
T89	43263	55	0	0
T158	0	8	0	0
T164	0	9	0	0
T168	0	44	0	0
T182	0	28	0	0
T183	0	41	0	0
T184	0	24	0	0
T185	0	35	0	0
T186	0	31	0	0
T187	0	268	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2725	0	0
T89	43263	58	0	0
T158	0	14	0	0
T164	0	13	0	0
T168	0	63	0	0
T182	0	25	0	0
T183	0	22	0	0
T184	0	17	0	0
T185	0	22	0	0
T186	0	11	0	0
T187	0	252	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2673	0	0
T89	43263	59	0	0
T158	0	13	0	0
T164	0	5	0	0
T182	0	15	0	0
T183	0	23	0	0
T184	0	15	0	0
T185	0	39	0	0
T186	0	26	0	0
T187	0	219	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T212	0	2	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2616	0	0
T89	43263	73	0	0
T158	0	6	0	0
T164	0	5	0	0
T168	0	39	0	0
T182	0	12	0	0
T183	0	24	0	0
T184	0	34	0	0
T185	0	21	0	0
T186	0	25	0	0
T187	0	220	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2663	0	0
T89	43263	47	0	0
T158	0	6	0	0
T164	0	11	0	0
T168	0	62	0	0
T182	0	31	0	0
T183	0	42	0	0
T184	0	24	0	0
T185	0	40	0	0
T186	0	31	0	0
T187	0	267	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2683	0	0
T89	43263	57	0	0
T158	0	8	0	0
T168	0	52	0	0
T182	0	44	0	0
T183	0	34	0	0
T184	0	23	0	0
T185	0	44	0	0
T186	0	30	0	0
T187	0	297	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0
T213	0	8	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2680	0	0
T89	43263	66	0	0
T158	0	13	0	0
T164	0	13	0	0
T168	0	45	0	0
T182	0	23	0	0
T183	0	42	0	0
T184	0	38	0	0
T185	0	28	0	0
T186	0	14	0	0
T187	0	261	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24118787	2799	0	0
T89	43263	49	0	0
T158	0	13	0	0
T164	0	13	0	0
T168	0	32	0	0
T182	0	32	0	0
T183	0	11	0	0
T184	0	30	0	0
T185	0	41	0	0
T186	0	34	0	0
T187	0	279	0	0
T188	7560	0	0	0
T189	3405	0	0	0
T190	34668	0	0	0
T191	4618	0	0	0
T192	2558	0	0	0
T193	14857	0	0	0
T194	7093	0	0	0
T195	17012	0	0	0
T196	1120	0	0	0