Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3364924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

609259

1

T1

145

T2

233

T3

141

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3558231	1			T1	351		T2	463		T3	612
values[0x0]	206287	1			T1	38		T2	69		T3	45
values[0x1]	209665	1			T1	49		T2	68		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2300321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1673862

1

T1

207

T2

324

T3

303

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12592	1			T1	1		T3	3		T14	6
valid_sources[0x01]	13114	1			T1	1		T3	6		T14	5
valid_sources[0x02]	11502	1			T1	7		T3	1		T4	4
valid_sources[0x03]	12751	1			T3	4		T4	11		T6	5
valid_sources[0x04]	11733	1			T1	4		T4	3		T14	2
valid_sources[0x05]	14423	1			T3	5		T4	9		T14	3
valid_sources[0x06]	77624	1			T3	4		T4	11		T16	6
valid_sources[0x07]	11142	1			T3	2		T4	5		T14	1
valid_sources[0x08]	12151	1			T3	4		T4	1		T14	2
valid_sources[0x09]	11891	1			T1	2		T3	7		T4	2
valid_sources[0x0a]	10900	1			T3	3		T4	8		T14	5
valid_sources[0x0b]	11847	1			T1	3		T14	4		T15	2
valid_sources[0x0c]	12583	1			T3	3		T4	2		T14	1
valid_sources[0x0d]	12321	1			T1	1		T3	2		T14	2
valid_sources[0x0e]	16762	1			T3	5		T4	7		T14	2
valid_sources[0x0f]	11181	1			T1	5		T3	4		T4	2
valid_sources[0x10]	11386	1			T1	1		T3	3		T14	3
valid_sources[0x11]	11478	1			T3	4		T4	1		T14	2
valid_sources[0x12]	11217	1			T1	1		T3	2		T14	7
valid_sources[0x13]	35271	1			T1	1		T3	3		T4	7
valid_sources[0x14]	14275	1			T1	3		T3	3		T14	5
valid_sources[0x15]	16260	1			T3	1		T4	2		T14	2
valid_sources[0x16]	23763	1			T1	1		T3	2		T4	4
valid_sources[0x17]	13844	1			T3	5		T14	2		T15	3
valid_sources[0x18]	11843	1			T3	3		T14	4		T15	3
valid_sources[0x19]	11370	1			T1	1		T14	1		T16	5
valid_sources[0x1a]	10778	1			T3	2		T4	5		T14	1
valid_sources[0x1b]	11175	1			T1	4		T3	2		T15	3
valid_sources[0x1c]	11453	1			T4	8		T14	2		T15	2
valid_sources[0x1d]	12107	1			T1	2		T3	5		T4	3
valid_sources[0x1e]	13126	1			T1	4		T3	1		T14	1
valid_sources[0x1f]	10545	1			T1	9		T3	5		T4	3
valid_sources[0x20]	11564	1			T3	3		T4	24		T14	3
valid_sources[0x21]	11433	1			T3	2		T4	6		T14	3
valid_sources[0x22]	12584	1			T1	5		T3	1		T16	5
valid_sources[0x23]	15600	1			T1	3		T14	3		T15	4
valid_sources[0x24]	11923	1			T1	3		T3	1		T4	3
valid_sources[0x25]	11489	1			T3	1		T4	9		T14	8
valid_sources[0x26]	14506	1			T1	1		T3	3		T14	2
valid_sources[0x27]	11197	1			T1	1		T4	5		T14	5
valid_sources[0x28]	14684	1			T3	1		T14	3		T16	3
valid_sources[0x29]	17256	1			T3	1		T14	2		T15	1
valid_sources[0x2a]	11872	1			T1	2		T3	6		T14	2
valid_sources[0x2b]	11328	1			T3	8		T14	5		T15	3
valid_sources[0x2c]	10934	1			T3	4		T15	3		T16	5
valid_sources[0x2d]	19543	1			T1	4		T3	7		T14	3
valid_sources[0x2e]	11358	1			T1	2		T3	5		T4	4
valid_sources[0x2f]	12798	1			T3	1		T4	1		T14	4
valid_sources[0x30]	11763	1			T1	1		T3	4		T4	1
valid_sources[0x31]	26713	1			T1	1		T3	1		T14	1
valid_sources[0x32]	11420	1			T1	2		T3	2		T4	18
valid_sources[0x33]	17615	1			T3	3		T4	4		T14	6
valid_sources[0x34]	11374	1			T3	1		T14	6		T15	1
valid_sources[0x35]	12248	1			T3	2		T4	5		T15	1
valid_sources[0x36]	17106	1			T14	5		T16	2		T6	4
valid_sources[0x37]	11698	1			T14	5		T15	1		T16	3
valid_sources[0x38]	12723	1			T3	7		T14	2		T15	4
valid_sources[0x39]	11559	1			T1	4		T3	6		T14	2
valid_sources[0x3a]	11475	1			T3	3		T4	16		T14	2
valid_sources[0x3b]	11598	1			T3	5		T14	4		T15	1
valid_sources[0x3c]	11411	1			T3	6		T4	11		T14	3
valid_sources[0x3d]	12722	1			T3	3		T14	4		T16	8
valid_sources[0x3e]	10852	1			T3	5		T4	6		T14	5
valid_sources[0x3f]	12792	1			T1	1		T3	2		T4	12
valid_sources[0x40]	11539	1			T3	4		T4	2		T14	2
valid_sources[0x41]	12864	1			T3	3		T4	10		T14	4
valid_sources[0x42]	14370	1			T1	14		T3	4		T4	1
valid_sources[0x43]	11608	1			T1	1		T3	1		T4	6
valid_sources[0x44]	12185	1			T1	1		T3	5		T4	7
valid_sources[0x45]	13285	1			T3	3		T14	3		T15	7
valid_sources[0x46]	10800	1			T3	2		T4	6		T15	3
valid_sources[0x47]	16566	1			T1	1		T3	3		T14	1
valid_sources[0x48]	18694	1			T3	3		T4	8		T14	1
valid_sources[0x49]	66170	1			T1	3		T3	2		T4	7
valid_sources[0x4a]	11794	1			T3	2		T15	2		T16	5
valid_sources[0x4b]	18464	1			T3	4		T14	7		T15	1
valid_sources[0x4c]	14604	1			T3	3		T14	8		T15	1
valid_sources[0x4d]	12862	1			T4	5		T14	1		T15	2
valid_sources[0x4e]	16002	1			T15	1		T16	6		T6	4
valid_sources[0x4f]	14195	1			T1	2		T3	2		T14	7
valid_sources[0x50]	11611	1			T3	3		T4	12		T14	6
valid_sources[0x51]	11361	1			T3	5		T4	7		T14	7
valid_sources[0x52]	12760	1			T1	2		T3	7		T14	7
valid_sources[0x53]	10999	1			T1	6		T3	1		T4	2
valid_sources[0x54]	11150	1			T1	3		T3	2		T4	4
valid_sources[0x55]	11246	1			T1	1		T3	2		T14	1
valid_sources[0x56]	11929	1			T3	3		T4	6		T14	2
valid_sources[0x57]	11224	1			T1	3		T3	2		T14	5
valid_sources[0x58]	12305	1			T1	3		T3	3		T4	3
valid_sources[0x59]	11302	1			T1	12		T3	2		T14	1
valid_sources[0x5a]	10922	1			T3	1		T4	3		T16	5
valid_sources[0x5b]	11239	1			T3	4		T14	6		T15	3
valid_sources[0x5c]	18099	1			T3	4		T14	2		T16	3
valid_sources[0x5d]	22064	1			T1	2		T3	4		T14	7
valid_sources[0x5e]	10933	1			T1	2		T3	2		T4	15
valid_sources[0x5f]	28713	1			T1	9		T3	1		T14	11
valid_sources[0x60]	11091	1			T3	4		T14	4		T15	1
valid_sources[0x61]	18708	1			T14	4		T15	6		T16	2
valid_sources[0x62]	12010	1			T2	600		T3	3		T14	5
valid_sources[0x63]	11805	1			T1	6		T3	1		T14	3
valid_sources[0x64]	20911	1			T1	23		T3	2		T14	6
valid_sources[0x65]	10932	1			T3	3		T14	3		T15	1
valid_sources[0x66]	61930	1			T3	4		T14	6		T15	1
valid_sources[0x67]	12908	1			T1	4		T3	3		T4	1
valid_sources[0x68]	59452	1			T1	1		T3	2		T15	2
valid_sources[0x69]	17588	1			T3	1		T14	3		T16	7
valid_sources[0x6a]	11766	1			T1	1		T14	3		T15	2
valid_sources[0x6b]	47287	1			T1	7		T3	4		T14	6
valid_sources[0x6c]	11598	1			T1	2		T3	2		T4	2
valid_sources[0x6d]	13992	1			T1	2		T3	2		T4	4
valid_sources[0x6e]	12428	1			T3	5		T14	4		T15	3
valid_sources[0x6f]	11653	1			T1	2		T3	3		T15	2
valid_sources[0x70]	11035	1			T3	4		T14	3		T16	6
valid_sources[0x71]	10943	1			T3	2		T14	3		T16	7
valid_sources[0x72]	11471	1			T3	2		T4	5		T14	4
valid_sources[0x73]	13277	1			T1	3		T3	3		T4	2
valid_sources[0x74]	11879	1			T1	2		T3	4		T14	6
valid_sources[0x75]	13676	1			T3	4		T14	4		T16	6
valid_sources[0x76]	12797	1			T1	3		T4	2		T14	1
valid_sources[0x77]	10964	1			T1	12		T3	2		T4	12
valid_sources[0x78]	27567	1			T3	4		T14	4		T16	4
valid_sources[0x79]	11278	1			T3	2		T4	5		T14	1
valid_sources[0x7a]	27007	1			T3	1		T14	1		T15	1
valid_sources[0x7b]	13603	1			T3	3		T14	6		T16	5
valid_sources[0x7c]	11583	1			T3	2		T4	2		T14	1
valid_sources[0x7d]	11917	1			T1	6		T3	3		T15	1
valid_sources[0x7e]	12633	1			T1	5		T3	3		T14	3
valid_sources[0x7f]	12197	1			T1	1		T3	3		T4	9
valid_sources[0x80]	10598	1			T3	1		T14	6		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325503

1

T1

122

T2

190

T3

115

values[0x0]

all_enables

biggest_size

148897

1

T1

15

T2

29

T3

17

values[0x1]

all_enables

biggest_size

134859

1

T1

8

T2

14

T3

9