Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sideload_ctrl.u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00

---

Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_sideload_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sideload_ctrl.u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        3/3              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[0].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[1].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[2].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[3].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[4].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[5].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[6].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[7].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	7758	7758	0	0
OutputsKnown_A	205562214	204054003	0	0
gen_no_flops.OutputDelay_A	205562214	204054003	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758	7758	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T14	9	9	0	0
T15	9	9	0	0
T16	9	9	0	0
T17	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205562214	204054003	0	0
T1	16578	15741	0	0
T2	22302	21528	0	0
T3	27513	27018	0	0
T4	22878	22239	0	0
T5	34353	33687	0	0
T6	45783	44442	0	0
T14	25452	24993	0	0
T15	47295	46773	0	0
T16	27594	27018	0	0
T17	68319	67635	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205562214	204054003	0	0
T1	16578	15741	0	0
T2	22302	21528	0	0
T3	27513	27018	0	0
T4	22878	22239	0	0
T5	34353	33687	0	0
T6	45783	44442	0	0
T14	25452	24993	0	0
T15	47295	46773	0	0
T16	27594	27018	0	0
T17	68319	67635	0	0

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        3/3              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T1 T2 T3 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        2/2              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	862	862	0	0
OutputsKnown_A	22840246	22672667	0	0
gen_no_flops.OutputDelay_A	22840246	22672667	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	862	862	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22840246	22672667	0	0
T1	1842	1749	0	0
T2	2478	2392	0	0
T3	3057	3002	0	0
T4	2542	2471	0	0
T5	3817	3743	0	0
T6	5087	4938	0	0
T14	2828	2777	0	0
T15	5255	5197	0	0
T16	3066	3002	0	0
T17	7591	7515	0	0