Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24455288	18253	0	0
attest_sw_binding_0_rd_A	24455288	2362	0	0
attest_sw_binding_1_rd_A	24455288	2455	0	0
attest_sw_binding_2_rd_A	24455288	2449	0	0
attest_sw_binding_3_rd_A	24455288	2460	0	0
attest_sw_binding_4_rd_A	24455288	2466	0	0
attest_sw_binding_5_rd_A	24455288	2516	0	0
attest_sw_binding_6_rd_A	24455288	2464	0	0
attest_sw_binding_7_rd_A	24455288	2327	0	0
intr_enable_rd_A	24455288	2859	0	0
key_version_rd_A	24455288	2368	0	0
max_creator_key_ver_regwen_rd_A	24455288	2234	0	0
max_owner_int_key_ver_regwen_rd_A	24455288	2409	0	0
max_owner_key_ver_regwen_rd_A	24455288	2523	0	0
reseed_interval_regwen_rd_A	24455288	2591	0	0
salt_0_rd_A	24455288	2536	0	0
salt_1_rd_A	24455288	2482	0	0
salt_2_rd_A	24455288	2447	0	0
salt_3_rd_A	24455288	2335	0	0
salt_4_rd_A	24455288	2377	0	0
salt_5_rd_A	24455288	2478	0	0
salt_6_rd_A	24455288	2397	0	0
salt_7_rd_A	24455288	2397	0	0
sealing_sw_binding_0_rd_A	24455288	2442	0	0
sealing_sw_binding_1_rd_A	24455288	2423	0	0
sealing_sw_binding_2_rd_A	24455288	2444	0	0
sealing_sw_binding_3_rd_A	24455288	2305	0	0
sealing_sw_binding_4_rd_A	24455288	2353	0	0
sealing_sw_binding_5_rd_A	24455288	2479	0	0
sealing_sw_binding_6_rd_A	24455288	2315	0	0
sealing_sw_binding_7_rd_A	24455288	2430	0	0
sideload_clear_rd_A	24455288	2323	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	18253	0	0
T44	30353	1	0	0
T52	10624	0	0	0
T54	3543	0	0	0
T74	0	1050	0	0
T75	0	20	0	0
T76	0	63	0	0
T77	0	368	0	0
T78	0	153	0	0
T79	0	60	0	0
T101	0	483	0	0
T102	0	888	0	0
T150	5836	0	0	0
T186	0	1	0	0
T187	6402	0	0	0
T188	11330	0	0	0
T189	15470	0	0	0
T190	15288	0	0	0
T191	9529	0	0	0
T192	12482	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2362	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	20	0	0
T77	31106	34	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	94	0	0
T93	0	35	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	28	0	0
T193	0	60	0	0
T194	0	3	0	0
T195	0	12	0	0
T196	0	28	0	0
T197	0	10	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2455	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	21	0	0
T77	31106	10	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	95	0	0
T93	0	21	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	46	0	0
T193	0	76	0	0
T194	0	3	0	0
T195	0	5	0	0
T196	0	27	0	0
T197	0	12	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2449	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	23	0	0
T77	31106	22	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	84	0	0
T93	0	35	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	35	0	0
T193	0	68	0	0
T194	0	6	0	0
T195	0	4	0	0
T196	0	33	0	0
T197	0	8	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2460	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	26	0	0
T77	31106	22	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	120	0	0
T93	0	30	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	56	0	0
T193	0	58	0	0
T194	0	6	0	0
T195	0	16	0	0
T196	0	45	0	0
T197	0	16	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2466	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	27	0	0
T77	31106	38	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	109	0	0
T93	0	14	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	51	0	0
T193	0	35	0	0
T194	0	33	0	0
T195	0	19	0	0
T196	0	38	0	0
T197	0	10	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2516	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	37	0	0
T77	31106	34	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	141	0	0
T93	0	26	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	41	0	0
T193	0	58	0	0
T194	0	25	0	0
T195	0	20	0	0
T196	0	48	0	0
T197	0	4	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2464	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	40	0	0
T77	31106	52	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	164	0	0
T93	0	25	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	37	0	0
T193	0	53	0	0
T194	0	28	0	0
T195	0	11	0	0
T196	0	26	0	0
T197	0	1	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2327	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	12	0	0
T77	31106	44	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	129	0	0
T93	0	23	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	34	0	0
T193	0	69	0	0
T194	0	13	0	0
T195	0	19	0	0
T196	0	35	0	0
T197	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2859	0	0
T21	4240	0	0	0
T69	1156	0	0	0
T70	3002	0	0	0
T76	0	69	0	0
T77	0	118	0	0
T148	0	25	0	0
T159	4061	0	0	0
T160	1826	0	0	0
T161	3289	9	0	0
T193	0	89	0	0
T194	0	31	0	0
T198	0	24	0	0
T199	0	27	0	0
T200	0	1	0	0
T201	0	7	0	0
T202	4785	0	0	0
T203	3523	0	0	0
T204	1329	0	0	0
T205	2144	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2368	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	15	0	0
T77	31106	20	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	98	0	0
T93	0	16	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	50	0	0
T193	0	39	0	0
T194	0	23	0	0
T195	0	18	0	0
T196	0	32	0	0
T197	0	7	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2234	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	25	0	0
T77	31106	26	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	106	0	0
T93	0	20	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	31	0	0
T193	0	28	0	0
T194	0	17	0	0
T195	0	18	0	0
T196	0	11	0	0
T197	0	17	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2409	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	40	0	0
T77	31106	34	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	87	0	0
T93	0	31	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	26	0	0
T193	0	71	0	0
T194	0	12	0	0
T195	0	10	0	0
T196	0	48	0	0
T197	0	16	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2523	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	36	0	0
T77	31106	43	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	110	0	0
T93	0	26	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	32	0	0
T193	0	57	0	0
T194	0	11	0	0
T195	0	31	0	0
T196	0	31	0	0
T197	0	13	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2591	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	20	0	0
T77	31106	29	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	159	0	0
T93	0	33	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	31	0	0
T193	0	46	0	0
T194	0	14	0	0
T195	0	30	0	0
T196	0	61	0	0
T197	0	20	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2536	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	43	0	0
T77	31106	39	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	83	0	0
T93	0	20	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	39	0	0
T193	0	40	0	0
T194	0	1	0	0
T195	0	14	0	0
T196	0	29	0	0
T197	0	16	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2482	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	36	0	0
T77	31106	40	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	140	0	0
T93	0	15	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	45	0	0
T168	0	74	0	0
T193	0	28	0	0
T195	0	13	0	0
T196	0	27	0	0
T197	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2447	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	26	0	0
T77	31106	19	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	137	0	0
T93	0	25	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	47	0	0
T168	0	97	0	0
T193	0	57	0	0
T194	0	20	0	0
T195	0	10	0	0
T196	0	23	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2335	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	46	0	0
T77	31106	29	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	117	0	0
T93	0	28	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	48	0	0
T193	0	48	0	0
T194	0	10	0	0
T195	0	32	0	0
T196	0	23	0	0
T197	0	8	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2377	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	31	0	0
T77	31106	27	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	92	0	0
T93	0	17	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	46	0	0
T193	0	55	0	0
T194	0	4	0	0
T195	0	17	0	0
T196	0	26	0	0
T197	0	6	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2478	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	24	0	0
T77	31106	24	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	87	0	0
T93	0	13	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	33	0	0
T193	0	79	0	0
T194	0	22	0	0
T195	0	3	0	0
T196	0	42	0	0
T197	0	20	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2397	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	28	0	0
T77	31106	18	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	110	0	0
T93	0	25	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	18	0	0
T193	0	60	0	0
T194	0	13	0	0
T195	0	21	0	0
T196	0	13	0	0
T197	0	3	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2397	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	31	0	0
T77	31106	27	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	73	0	0
T93	0	27	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	39	0	0
T168	0	87	0	0
T193	0	67	0	0
T194	0	5	0	0
T195	0	7	0	0
T196	0	9	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2442	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	29	0	0
T77	31106	31	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	80	0	0
T93	0	28	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	47	0	0
T193	0	50	0	0
T194	0	22	0	0
T195	0	33	0	0
T196	0	38	0	0
T197	0	11	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2423	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	24	0	0
T77	31106	24	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	102	0	0
T93	0	12	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	43	0	0
T193	0	50	0	0
T194	0	9	0	0
T195	0	17	0	0
T196	0	26	0	0
T197	0	15	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2444	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	33	0	0
T77	31106	33	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	111	0	0
T93	0	35	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	51	0	0
T193	0	32	0	0
T194	0	6	0	0
T195	0	35	0	0
T196	0	38	0	0
T197	0	9	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2305	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	46	0	0
T77	31106	25	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	74	0	0
T93	0	27	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	28	0	0
T193	0	52	0	0
T194	0	16	0	0
T195	0	22	0	0
T196	0	24	0	0
T197	0	13	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2353	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	25	0	0
T77	31106	7	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	142	0	0
T93	0	20	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	43	0	0
T193	0	63	0	0
T194	0	11	0	0
T195	0	14	0	0
T196	0	13	0	0
T197	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2479	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	38	0	0
T77	31106	41	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	126	0	0
T93	0	25	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	49	0	0
T193	0	56	0	0
T194	0	11	0	0
T195	0	43	0	0
T196	0	34	0	0
T197	0	15	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2315	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	27	0	0
T77	31106	43	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	100	0	0
T93	0	21	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	40	0	0
T193	0	60	0	0
T194	0	13	0	0
T195	0	18	0	0
T196	0	7	0	0
T197	0	15	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2430	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	22	0	0
T77	31106	40	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	128	0	0
T93	0	22	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	48	0	0
T193	0	54	0	0
T194	0	8	0	0
T195	0	21	0	0
T196	0	30	0	0
T197	0	3	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24455288	2323	0	0
T45	5052	0	0	0
T53	8277	0	0	0
T76	0	21	0	0
T77	31106	19	0	0
T84	4309	0	0	0
T85	936	0	0	0
T86	3180	0	0	0
T87	26871	0	0	0
T88	12608	0	0	0
T89	0	98	0	0
T93	0	25	0	0
T110	8778	0	0	0
T111	20636	0	0	0
T163	0	32	0	0
T193	0	42	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	35	0	0
T197	0	7	0	0