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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.11 98.39 100.00 99.02 98.63 91.22


Total test records in report: 1067
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1006 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.4178337172 Sep 01 12:28:25 PM UTC 24 Sep 01 12:28:28 PM UTC 24 60612581 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3934751019 Sep 01 12:28:24 PM UTC 24 Sep 01 12:28:29 PM UTC 24 100840808 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1184686377 Sep 01 12:28:25 PM UTC 24 Sep 01 12:28:29 PM UTC 24 381332474 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3121187630 Sep 01 12:28:26 PM UTC 24 Sep 01 12:28:29 PM UTC 24 377658021 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.1543350741 Sep 01 12:28:27 PM UTC 24 Sep 01 12:28:30 PM UTC 24 12919405 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.4024374232 Sep 01 12:28:27 PM UTC 24 Sep 01 12:28:30 PM UTC 24 44356082 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4203834491 Sep 01 12:28:28 PM UTC 24 Sep 01 12:28:31 PM UTC 24 65252879 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2682348381 Sep 01 12:28:29 PM UTC 24 Sep 01 12:28:32 PM UTC 24 28173085 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3633146420 Sep 01 12:28:23 PM UTC 24 Sep 01 12:28:32 PM UTC 24 521855361 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1234712764 Sep 01 12:28:27 PM UTC 24 Sep 01 12:28:32 PM UTC 24 69662047 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2371373951 Sep 01 12:28:29 PM UTC 24 Sep 01 12:28:32 PM UTC 24 184230724 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.1406576731 Sep 01 12:28:30 PM UTC 24 Sep 01 12:28:32 PM UTC 24 25482124 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1172169990 Sep 01 12:28:30 PM UTC 24 Sep 01 12:28:33 PM UTC 24 26792560 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2144155344 Sep 01 12:28:27 PM UTC 24 Sep 01 12:28:33 PM UTC 24 117479324 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3570553431 Sep 01 12:28:29 PM UTC 24 Sep 01 12:28:34 PM UTC 24 1496917023 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1830569765 Sep 01 12:28:24 PM UTC 24 Sep 01 12:28:34 PM UTC 24 1873676783 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.375799442 Sep 01 12:28:30 PM UTC 24 Sep 01 12:28:35 PM UTC 24 251706974 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1934130573 Sep 01 12:28:31 PM UTC 24 Sep 01 12:28:35 PM UTC 24 168185535 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.233200491 Sep 01 12:28:27 PM UTC 24 Sep 01 12:28:36 PM UTC 24 238460420 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.1157184043 Sep 01 12:28:34 PM UTC 24 Sep 01 12:28:37 PM UTC 24 34456596 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.983021123 Sep 01 12:28:21 PM UTC 24 Sep 01 12:28:37 PM UTC 24 909587964 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3308537517 Sep 01 12:28:29 PM UTC 24 Sep 01 12:28:37 PM UTC 24 157801943 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.435477171 Sep 01 12:28:31 PM UTC 24 Sep 01 12:28:37 PM UTC 24 524178247 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.534204887 Sep 01 12:28:32 PM UTC 24 Sep 01 12:28:38 PM UTC 24 52437333 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3219891567 Sep 01 12:28:32 PM UTC 24 Sep 01 12:28:38 PM UTC 24 71486062 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3902377502 Sep 01 12:28:34 PM UTC 24 Sep 01 12:28:38 PM UTC 24 230127830 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.754984702 Sep 01 12:28:36 PM UTC 24 Sep 01 12:28:39 PM UTC 24 39432068 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3175488190 Sep 01 12:28:36 PM UTC 24 Sep 01 12:28:39 PM UTC 24 11628472 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1652573461 Sep 01 12:28:34 PM UTC 24 Sep 01 12:28:39 PM UTC 24 237174986 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1131855376 Sep 01 12:28:34 PM UTC 24 Sep 01 12:28:39 PM UTC 24 95954964 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3038298139 Sep 01 12:28:35 PM UTC 24 Sep 01 12:28:40 PM UTC 24 37903414 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3750703602 Sep 01 12:28:38 PM UTC 24 Sep 01 12:28:40 PM UTC 24 26938332 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.104929669 Sep 01 12:28:38 PM UTC 24 Sep 01 12:28:40 PM UTC 24 26960417 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2599932018 Sep 01 12:28:38 PM UTC 24 Sep 01 12:28:40 PM UTC 24 12450152 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.731006685 Sep 01 12:28:29 PM UTC 24 Sep 01 12:28:41 PM UTC 24 3224623854 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2276417102 Sep 01 12:28:39 PM UTC 24 Sep 01 12:28:41 PM UTC 24 16892045 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1702511585 Sep 01 12:28:39 PM UTC 24 Sep 01 12:28:41 PM UTC 24 18851905 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.220403242 Sep 01 12:28:37 PM UTC 24 Sep 01 12:28:41 PM UTC 24 74605384 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3051302525 Sep 01 12:28:39 PM UTC 24 Sep 01 12:28:41 PM UTC 24 144914300 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2374269801 Sep 01 12:28:32 PM UTC 24 Sep 01 12:28:41 PM UTC 24 374098735 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.621065460 Sep 01 12:28:39 PM UTC 24 Sep 01 12:28:41 PM UTC 24 32573668 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.158573748 Sep 01 12:28:40 PM UTC 24 Sep 01 12:28:42 PM UTC 24 17115562 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.3547807988 Sep 01 12:28:40 PM UTC 24 Sep 01 12:28:42 PM UTC 24 24085063 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3049547479 Sep 01 12:28:40 PM UTC 24 Sep 01 12:28:42 PM UTC 24 31264830 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1758516907 Sep 01 12:28:37 PM UTC 24 Sep 01 12:28:42 PM UTC 24 44648720 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1342200910 Sep 01 12:28:40 PM UTC 24 Sep 01 12:28:42 PM UTC 24 16724909 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3166711717 Sep 01 12:28:35 PM UTC 24 Sep 01 12:28:43 PM UTC 24 178612506 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.788737495 Sep 01 12:28:41 PM UTC 24 Sep 01 12:28:44 PM UTC 24 30069101 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.2131489387 Sep 01 12:28:41 PM UTC 24 Sep 01 12:28:44 PM UTC 24 64283236 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.3762323813 Sep 01 12:28:42 PM UTC 24 Sep 01 12:28:44 PM UTC 24 9365738 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2598986488 Sep 01 12:28:41 PM UTC 24 Sep 01 12:28:44 PM UTC 24 214070568 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.30321877 Sep 01 12:28:42 PM UTC 24 Sep 01 12:28:44 PM UTC 24 14587520 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.325074442 Sep 01 12:28:42 PM UTC 24 Sep 01 12:28:44 PM UTC 24 36306460 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3867053139 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 14568154 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3402558038 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 12258278 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3097232861 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 13901296 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2527133618 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 11062155 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.525772419 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 26071727 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2005030837 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 12788438 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1138613602 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:45 PM UTC 24 13041626 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3690187927 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:46 PM UTC 24 20250896 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.294742000 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:46 PM UTC 24 90275180 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.2728885590 Sep 01 12:28:43 PM UTC 24 Sep 01 12:28:46 PM UTC 24 16152640 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.3480276899 Sep 01 12:28:44 PM UTC 24 Sep 01 12:28:46 PM UTC 24 41848436 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.1391151673 Sep 01 12:28:45 PM UTC 24 Sep 01 12:28:47 PM UTC 24 18710022 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.4209700137 Sep 01 12:28:45 PM UTC 24 Sep 01 12:28:47 PM UTC 24 81816697 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.4198856355 Sep 01 12:28:35 PM UTC 24 Sep 01 12:28:48 PM UTC 24 543894249 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.1372864957
Short name T6
Test name
Test status
Simulation time 51932543 ps
CPU time 2.59 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372864957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1372864957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.724709957
Short name T74
Test name
Test status
Simulation time 284999075 ps
CPU time 15.73 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 232360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=724709957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_
stress_all_with_rand_reset.724709957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.1475526470
Short name T16
Test name
Test status
Simulation time 127869876 ps
CPU time 2.3 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 228224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475526470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1475526470
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.1490013137
Short name T148
Test name
Test status
Simulation time 821358643 ps
CPU time 26.25 seconds
Started Sep 01 01:31:51 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 228524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490013137 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1490013137
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.3347388742
Short name T77
Test name
Test status
Simulation time 3110807553 ps
CPU time 7.21 seconds
Started Sep 01 01:31:44 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 230448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3347388742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr
_stress_all_with_rand_reset.3347388742
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.2037780251
Short name T12
Test name
Test status
Simulation time 2315031138 ps
CPU time 8.64 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 254620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037780251 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2037780251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.2084078780
Short name T84
Test name
Test status
Simulation time 93694189 ps
CPU time 2.98 seconds
Started Sep 01 01:31:48 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084078780 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2084078780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.3512504238
Short name T290
Test name
Test status
Simulation time 130136007 ps
CPU time 4.78 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:56 PM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512504238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3512504238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.1802549185
Short name T141
Test name
Test status
Simulation time 611261646 ps
CPU time 13.82 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802549185 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1802549185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.3499712193
Short name T126
Test name
Test status
Simulation time 150694676 ps
CPU time 4.51 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499712193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3499712193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.3963363338
Short name T38
Test name
Test status
Simulation time 88790571 ps
CPU time 2.4 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:40 PM UTC 24
Peak memory 226024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963363338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3963363338
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.1974035930
Short name T92
Test name
Test status
Simulation time 453247261 ps
CPU time 5.77 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:54 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974035930 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1974035930
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2958513420
Short name T89
Test name
Test status
Simulation time 380378369 ps
CPU time 12.98 seconds
Started Sep 01 12:27:02 PM UTC 24
Finished Sep 01 12:27:16 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958513420 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.2958513420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.3686150500
Short name T113
Test name
Test status
Simulation time 168684718 ps
CPU time 8.04 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686150500 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3686150500
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.480546658
Short name T9
Test name
Test status
Simulation time 652760476 ps
CPU time 6.23 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:19 PM UTC 24
Peak memory 230912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480546658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.480546658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.1532136362
Short name T88
Test name
Test status
Simulation time 394075360 ps
CPU time 6.08 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:54 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532136362 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1532136362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.1410793615
Short name T112
Test name
Test status
Simulation time 57617578 ps
CPU time 3.83 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410793615 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1410793615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.1332556571
Short name T53
Test name
Test status
Simulation time 331123617 ps
CPU time 4.16 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:56 PM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332556571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1332556571
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.3864457056
Short name T19
Test name
Test status
Simulation time 346624788 ps
CPU time 4.02 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 224264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864457056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3864457056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.3761071775
Short name T149
Test name
Test status
Simulation time 2289270101 ps
CPU time 40.04 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 232580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761071775 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3761071775
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.1755731620
Short name T214
Test name
Test status
Simulation time 299405724 ps
CPU time 4.45 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 226024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755731620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1755731620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.359803656
Short name T254
Test name
Test status
Simulation time 322093740 ps
CPU time 7.74 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359803656 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.359803656
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1400480999
Short name T95
Test name
Test status
Simulation time 279637443 ps
CPU time 5.41 seconds
Started Sep 01 12:27:21 PM UTC 24
Finished Sep 01 12:27:27 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400480999 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1400480999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.1731276945
Short name T71
Test name
Test status
Simulation time 486682955 ps
CPU time 3.02 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:40 PM UTC 24
Peak memory 225716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731276945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1731276945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.2979255535
Short name T41
Test name
Test status
Simulation time 716170446 ps
CPU time 4.59 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:14 PM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979255535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2979255535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.4069961635
Short name T22
Test name
Test status
Simulation time 178765694 ps
CPU time 3.77 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:11 PM UTC 24
Peak memory 224520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069961635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4069961635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.50002419
Short name T32
Test name
Test status
Simulation time 92473492 ps
CPU time 3.26 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50002419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.50002419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.3070887863
Short name T382
Test name
Test status
Simulation time 1810039137 ps
CPU time 79.81 seconds
Started Sep 01 01:34:24 PM UTC 24
Finished Sep 01 01:35:45 PM UTC 24
Peak memory 226168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070887863 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3070887863
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.764365398
Short name T104
Test name
Test status
Simulation time 76748681 ps
CPU time 3.05 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764365398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.764365398
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.110533946
Short name T64
Test name
Test status
Simulation time 5107480184 ps
CPU time 71.48 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:33:36 PM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110533946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.110533946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.1488093561
Short name T49
Test name
Test status
Simulation time 214701598 ps
CPU time 3.03 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 218124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488093561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1488093561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.2769225897
Short name T8
Test name
Test status
Simulation time 408075608 ps
CPU time 12.99 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769225897 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2769225897
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.2256103996
Short name T202
Test name
Test status
Simulation time 111343686 ps
CPU time 2.81 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256103996 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2256103996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.579524373
Short name T280
Test name
Test status
Simulation time 505499634 ps
CPU time 6.94 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:28 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579524373 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.579524373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.3683963465
Short name T252
Test name
Test status
Simulation time 1420373554 ps
CPU time 67.9 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:33:06 PM UTC 24
Peak memory 232512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683963465 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3683963465
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.3548285117
Short name T78
Test name
Test status
Simulation time 3738113019 ps
CPU time 8.45 seconds
Started Sep 01 01:31:51 PM UTC 24
Finished Sep 01 01:32:00 PM UTC 24
Peak memory 232352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3548285117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr
_stress_all_with_rand_reset.3548285117
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.3859404238
Short name T223
Test name
Test status
Simulation time 1639526823 ps
CPU time 18.52 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859404238 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3859404238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.1573486019
Short name T348
Test name
Test status
Simulation time 1494269053 ps
CPU time 19.29 seconds
Started Sep 01 01:32:35 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573486019 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1573486019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_random.1044217957
Short name T426
Test name
Test status
Simulation time 1268280256 ps
CPU time 11.44 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044217957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1044217957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.853946032
Short name T44
Test name
Test status
Simulation time 1011775505 ps
CPU time 9.06 seconds
Started Sep 01 01:31:44 PM UTC 24
Finished Sep 01 01:31:54 PM UTC 24
Peak memory 219668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853946032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.853946032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_random.356629535
Short name T5
Test name
Test status
Simulation time 159096417 ps
CPU time 1.91 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 217672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356629535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.356629535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.2130792251
Short name T23
Test name
Test status
Simulation time 61286334 ps
CPU time 3.68 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130792251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2130792251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.1548428997
Short name T199
Test name
Test status
Simulation time 10489590850 ps
CPU time 34.02 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:33:02 PM UTC 24
Peak memory 231444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548428997 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1548428997
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.1479139892
Short name T147
Test name
Test status
Simulation time 1595868369 ps
CPU time 40.91 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:42 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479139892 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1479139892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.796372919
Short name T67
Test name
Test status
Simulation time 11669640 ps
CPU time 0.77 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:47 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796372919 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.796372919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.4032357636
Short name T292
Test name
Test status
Simulation time 90932501 ps
CPU time 2.86 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:24 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032357636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4032357636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.1522327161
Short name T166
Test name
Test status
Simulation time 183012174 ps
CPU time 6.88 seconds
Started Sep 01 12:27:52 PM UTC 24
Finished Sep 01 12:28:00 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522327161 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.1522327161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2374269801
Short name T164
Test name
Test status
Simulation time 374098735 ps
CPU time 7.33 seconds
Started Sep 01 12:28:32 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374269801 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.2374269801
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.3248006560
Short name T102
Test name
Test status
Simulation time 1102765439 ps
CPU time 23.29 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:30 PM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3248006560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg
r_stress_all_with_rand_reset.3248006560
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.4051762760
Short name T391
Test name
Test status
Simulation time 125549518 ps
CPU time 6.28 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:17 PM UTC 24
Peak memory 232312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051762760 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4051762760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.3106826291
Short name T244
Test name
Test status
Simulation time 66979379 ps
CPU time 3.94 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:38 PM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106826291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3106826291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.1468187838
Short name T145
Test name
Test status
Simulation time 454909395 ps
CPU time 9.08 seconds
Started Sep 01 01:32:44 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468187838 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1468187838
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.3751838276
Short name T128
Test name
Test status
Simulation time 58324038 ps
CPU time 2.37 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 232468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751838276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3751838276
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.1800212996
Short name T72
Test name
Test status
Simulation time 314039820 ps
CPU time 3.47 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 215492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800212996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1800212996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1291559343
Short name T340
Test name
Test status
Simulation time 8064807860 ps
CPU time 99.05 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:34:18 PM UTC 24
Peak memory 231252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291559343 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1291559343
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.1606851638
Short name T52
Test name
Test status
Simulation time 965934560 ps
CPU time 3.25 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 226520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606851638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1606851638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.175905289
Short name T406
Test name
Test status
Simulation time 268519369 ps
CPU time 13.96 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 232404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=175905289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr
_stress_all_with_rand_reset.175905289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.3214889690
Short name T276
Test name
Test status
Simulation time 93716620 ps
CPU time 3.81 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:58 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214889690 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3214889690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.56011468
Short name T629
Test name
Test status
Simulation time 420936484 ps
CPU time 7.36 seconds
Started Sep 01 01:33:01 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 232408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=56011468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_
stress_all_with_rand_reset.56011468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3704537713
Short name T93
Test name
Test status
Simulation time 171063536 ps
CPU time 3.06 seconds
Started Sep 01 12:27:02 PM UTC 24
Finished Sep 01 12:27:06 PM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704537713 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.3704537713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1952505264
Short name T176
Test name
Test status
Simulation time 160915267 ps
CPU time 3.55 seconds
Started Sep 01 12:28:21 PM UTC 24
Finished Sep 01 12:28:26 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952505264 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.1952505264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.520100306
Short name T114
Test name
Test status
Simulation time 192372716 ps
CPU time 3.91 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:05 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520100306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.520100306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.3237276334
Short name T109
Test name
Test status
Simulation time 598969031 ps
CPU time 18.24 seconds
Started Sep 01 01:32:14 PM UTC 24
Finished Sep 01 01:32:34 PM UTC 24
Peak memory 232336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3237276334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymg
r_stress_all_with_rand_reset.3237276334
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.1363406301
Short name T322
Test name
Test status
Simulation time 116459627 ps
CPU time 4.23 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:29 PM UTC 24
Peak memory 232452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363406301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1363406301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.3676622183
Short name T440
Test name
Test status
Simulation time 11931304450 ps
CPU time 36.08 seconds
Started Sep 01 01:33:02 PM UTC 24
Finished Sep 01 01:34:30 PM UTC 24
Peak memory 224424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676622183 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3676622183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.900614918
Short name T183
Test name
Test status
Simulation time 2028390926 ps
CPU time 15.5 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900614918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.900614918
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.476076
Short name T185
Test name
Test status
Simulation time 511194238 ps
CPU time 4.39 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=ke
ymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.476076
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.1387682547
Short name T3
Test name
Test status
Simulation time 31213022 ps
CPU time 2.04 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387682547 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1387682547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.3994779914
Short name T227
Test name
Test status
Simulation time 2556705568 ps
CPU time 26.67 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:32:14 PM UTC 24
Peak memory 233012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994779914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3994779914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.4062321038
Short name T217
Test name
Test status
Simulation time 843617945 ps
CPU time 10.95 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062321038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4062321038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.3051323659
Short name T357
Test name
Test status
Simulation time 169639187 ps
CPU time 3.64 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:22 PM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051323659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3051323659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2758387165
Short name T386
Test name
Test status
Simulation time 29676801348 ps
CPU time 195.22 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:35:42 PM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758387165 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2758387165
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.956011003
Short name T25
Test name
Test status
Simulation time 1379655786 ps
CPU time 4.42 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956011003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.956011003
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.1275630501
Short name T387
Test name
Test status
Simulation time 197209714 ps
CPU time 9.83 seconds
Started Sep 01 01:32:59 PM UTC 24
Finished Sep 01 01:34:01 PM UTC 24
Peak memory 225904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275630501 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1275630501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.1872725452
Short name T241
Test name
Test status
Simulation time 3964020589 ps
CPU time 101.68 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:33:31 PM UTC 24
Peak memory 232296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872725452 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1872725452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.346233805
Short name T136
Test name
Test status
Simulation time 259795683 ps
CPU time 2.61 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 220028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346233805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.346233805
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.2126342000
Short name T129
Test name
Test status
Simulation time 68518282 ps
CPU time 2.95 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126342000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2126342000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.1394605411
Short name T130
Test name
Test status
Simulation time 145532157 ps
CPU time 3.05 seconds
Started Sep 01 01:33:09 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 226392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394605411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1394605411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_random.2389735760
Short name T111
Test name
Test status
Simulation time 412764442 ps
CPU time 8.13 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:55 PM UTC 24
Peak memory 227768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389735760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2389735760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.2871781474
Short name T267
Test name
Test status
Simulation time 249792768 ps
CPU time 3.01 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 226524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871781474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2871781474
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.277089225
Short name T115
Test name
Test status
Simulation time 283279625 ps
CPU time 4.26 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:14 PM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277089225 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.277089225
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.1697368958
Short name T265
Test name
Test status
Simulation time 146125621 ps
CPU time 3.32 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:13 PM UTC 24
Peak memory 228416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697368958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1697368958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.3583485105
Short name T270
Test name
Test status
Simulation time 50815892 ps
CPU time 3.49 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583485105 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3583485105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.2106672206
Short name T242
Test name
Test status
Simulation time 983662873 ps
CPU time 12.86 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 225900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106672206 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2106672206
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.991514465
Short name T316
Test name
Test status
Simulation time 89093815 ps
CPU time 2.19 seconds
Started Sep 01 01:32:52 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991514465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.991514465
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.2763019625
Short name T248
Test name
Test status
Simulation time 5134212890 ps
CPU time 33.07 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:35:11 PM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763019625 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2763019625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.138230125
Short name T900
Test name
Test status
Simulation time 8200770189 ps
CPU time 90.83 seconds
Started Sep 01 01:34:43 PM UTC 24
Finished Sep 01 01:36:16 PM UTC 24
Peak memory 230240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138230125 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.138230125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.1869054526
Short name T260
Test name
Test status
Simulation time 119140342 ps
CPU time 3.75 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 215540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869054526 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1869054526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1830569765
Short name T175
Test name
Test status
Simulation time 1873676783 ps
CPU time 9.58 seconds
Started Sep 01 12:28:24 PM UTC 24
Finished Sep 01 12:28:34 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830569765 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.1830569765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.4198856355
Short name T182
Test name
Test status
Simulation time 543894249 ps
CPU time 11.56 seconds
Started Sep 01 12:28:35 PM UTC 24
Finished Sep 01 12:28:48 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198856355 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.4198856355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.3296638110
Short name T174
Test name
Test status
Simulation time 265832276 ps
CPU time 9.33 seconds
Started Sep 01 12:27:25 PM UTC 24
Finished Sep 01 12:27:36 PM UTC 24
Peak memory 228196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296638110 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.3296638110
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.3433443014
Short name T171
Test name
Test status
Simulation time 3026015841 ps
CPU time 9.08 seconds
Started Sep 01 12:28:05 PM UTC 24
Finished Sep 01 12:28:15 PM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433443014 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.3433443014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.3140050833
Short name T13
Test name
Test status
Simulation time 421346968 ps
CPU time 10.11 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 260396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140050833 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3140050833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.2833410140
Short name T177
Test name
Test status
Simulation time 109703361 ps
CPU time 2.41 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833410140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2833410140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3318339624
Short name T137
Test name
Test status
Simulation time 47142998 ps
CPU time 2.1 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318339624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3318339624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.2353295747
Short name T359
Test name
Test status
Simulation time 1214872128 ps
CPU time 20.92 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353295747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2353295747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.1419359048
Short name T399
Test name
Test status
Simulation time 1382237863 ps
CPU time 3.87 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:11 PM UTC 24
Peak memory 224428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419359048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1419359048
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.1179738859
Short name T116
Test name
Test status
Simulation time 132681576 ps
CPU time 2.85 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:15 PM UTC 24
Peak memory 230224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179738859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1179738859
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1997180337
Short name T33
Test name
Test status
Simulation time 381219012 ps
CPU time 5.8 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:27 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997180337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1997180337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.4102988260
Short name T225
Test name
Test status
Simulation time 77222721 ps
CPU time 3.53 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:31 PM UTC 24
Peak memory 218644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102988260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4102988260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.1611624075
Short name T403
Test name
Test status
Simulation time 1965869690 ps
CPU time 26.63 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:33:02 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611624075 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1611624075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.1771252801
Short name T249
Test name
Test status
Simulation time 1500505736 ps
CPU time 24.19 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:33:04 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771252801 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1771252801
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.1276125410
Short name T354
Test name
Test status
Simulation time 1361646658 ps
CPU time 11.53 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276125410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1276125410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.2958878684
Short name T376
Test name
Test status
Simulation time 73154279 ps
CPU time 3.22 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:46 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958878684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2958878684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.3376758704
Short name T303
Test name
Test status
Simulation time 929052480 ps
CPU time 31.06 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:33:19 PM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376758704 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3376758704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.1241948791
Short name T61
Test name
Test status
Simulation time 109907854 ps
CPU time 4.37 seconds
Started Sep 01 01:32:48 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241948791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1241948791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2886822625
Short name T443
Test name
Test status
Simulation time 227629239 ps
CPU time 11.01 seconds
Started Sep 01 01:32:51 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 222872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886822625 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2886822625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.1498878972
Short name T338
Test name
Test status
Simulation time 639354832 ps
CPU time 9.66 seconds
Started Sep 01 01:33:54 PM UTC 24
Finished Sep 01 01:34:06 PM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498878972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1498878972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.1565637091
Short name T375
Test name
Test status
Simulation time 28251751 ps
CPU time 1.84 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:08 PM UTC 24
Peak memory 224416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565637091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1565637091
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.4054749683
Short name T196
Test name
Test status
Simulation time 2049232986 ps
CPU time 15.49 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 230304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4054749683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg
r_stress_all_with_rand_reset.4054749683
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.697636338
Short name T271
Test name
Test status
Simulation time 1147955742 ps
CPU time 7.32 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:39 PM UTC 24
Peak memory 232228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697636338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.697636338
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.3095948166
Short name T347
Test name
Test status
Simulation time 256545212 ps
CPU time 3.49 seconds
Started Sep 01 01:34:43 PM UTC 24
Finished Sep 01 01:34:48 PM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095948166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3095948166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.327339609
Short name T119
Test name
Test status
Simulation time 189338293 ps
CPU time 5.69 seconds
Started Sep 01 12:27:09 PM UTC 24
Finished Sep 01 12:27:16 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327339609 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.327339609
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4189730112
Short name T909
Test name
Test status
Simulation time 253617858 ps
CPU time 19.74 seconds
Started Sep 01 12:27:08 PM UTC 24
Finished Sep 01 12:27:29 PM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189730112 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4189730112
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.598015965
Short name T162
Test name
Test status
Simulation time 30355876 ps
CPU time 1.55 seconds
Started Sep 01 12:27:07 PM UTC 24
Finished Sep 01 12:27:10 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598015965 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.598015965
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1555055758
Short name T422
Test name
Test status
Simulation time 38994443 ps
CPU time 3.14 seconds
Started Sep 01 12:27:12 PM UTC 24
Finished Sep 01 12:27:16 PM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1555055758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w
ith_rand_reset.1555055758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.660257428
Short name T118
Test name
Test status
Simulation time 25293534 ps
CPU time 1.75 seconds
Started Sep 01 12:27:08 PM UTC 24
Finished Sep 01 12:27:11 PM UTC 24
Peak memory 213184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660257428 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.660257428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.2157649552
Short name T902
Test name
Test status
Simulation time 11478968 ps
CPU time 1.13 seconds
Started Sep 01 12:27:05 PM UTC 24
Finished Sep 01 12:27:07 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157649552 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2157649552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1383177776
Short name T120
Test name
Test status
Simulation time 1523402218 ps
CPU time 5.99 seconds
Started Sep 01 12:27:11 PM UTC 24
Finished Sep 01 12:27:18 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383177776 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1383177776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.721529283
Short name T903
Test name
Test status
Simulation time 89650594 ps
CPU time 4.78 seconds
Started Sep 01 12:27:03 PM UTC 24
Finished Sep 01 12:27:09 PM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721529283 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.721529283
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.3431664950
Short name T163
Test name
Test status
Simulation time 514053222 ps
CPU time 8.35 seconds
Started Sep 01 12:27:03 PM UTC 24
Finished Sep 01 12:27:13 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431664950 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.3431664950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.3488706895
Short name T911
Test name
Test status
Simulation time 530145370 ps
CPU time 11.59 seconds
Started Sep 01 12:27:20 PM UTC 24
Finished Sep 01 12:27:32 PM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488706895 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3488706895
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4161552429
Short name T918
Test name
Test status
Simulation time 1038391344 ps
CPU time 19.85 seconds
Started Sep 01 12:27:19 PM UTC 24
Finished Sep 01 12:27:40 PM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161552429 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4161552429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1617651228
Short name T906
Test name
Test status
Simulation time 55796413 ps
CPU time 1.76 seconds
Started Sep 01 12:27:17 PM UTC 24
Finished Sep 01 12:27:20 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617651228 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1617651228
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2846587612
Short name T197
Test name
Test status
Simulation time 203713827 ps
CPU time 3 seconds
Started Sep 01 12:27:20 PM UTC 24
Finished Sep 01 12:27:24 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2846587612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w
ith_rand_reset.2846587612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.2253912322
Short name T121
Test name
Test status
Simulation time 19881706 ps
CPU time 1.63 seconds
Started Sep 01 12:27:19 PM UTC 24
Finished Sep 01 12:27:21 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253912322 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2253912322
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.3847706038
Short name T905
Test name
Test status
Simulation time 22291708 ps
CPU time 1.11 seconds
Started Sep 01 12:27:16 PM UTC 24
Finished Sep 01 12:27:18 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847706038 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3847706038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2477450558
Short name T122
Test name
Test status
Simulation time 168072303 ps
CPU time 3.65 seconds
Started Sep 01 12:27:20 PM UTC 24
Finished Sep 01 12:27:24 PM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477450558 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.2477450558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4155341273
Short name T94
Test name
Test status
Simulation time 293270966 ps
CPU time 4.59 seconds
Started Sep 01 12:27:13 PM UTC 24
Finished Sep 01 12:27:19 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155341273 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.4155341273
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.631857772
Short name T90
Test name
Test status
Simulation time 293690763 ps
CPU time 4.65 seconds
Started Sep 01 12:27:13 PM UTC 24
Finished Sep 01 12:27:19 PM UTC 24
Peak memory 226792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631857772 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.631857772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.2587310851
Short name T904
Test name
Test status
Simulation time 86931733 ps
CPU time 3.54 seconds
Started Sep 01 12:27:13 PM UTC 24
Finished Sep 01 12:27:18 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587310851 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2587310851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.496119455
Short name T168
Test name
Test status
Simulation time 263734958 ps
CPU time 9.56 seconds
Started Sep 01 12:27:16 PM UTC 24
Finished Sep 01 12:27:27 PM UTC 24
Peak memory 226348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496119455 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.496119455
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2641301549
Short name T969
Test name
Test status
Simulation time 19619671 ps
CPU time 1.96 seconds
Started Sep 01 12:28:10 PM UTC 24
Finished Sep 01 12:28:13 PM UTC 24
Peak memory 223748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2641301549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_
with_rand_reset.2641301549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.2378357810
Short name T966
Test name
Test status
Simulation time 40804426 ps
CPU time 1.29 seconds
Started Sep 01 12:28:09 PM UTC 24
Finished Sep 01 12:28:11 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378357810 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2378357810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.2896372457
Short name T965
Test name
Test status
Simulation time 161312715 ps
CPU time 1.3 seconds
Started Sep 01 12:28:09 PM UTC 24
Finished Sep 01 12:28:11 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896372457 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2896372457
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3992581936
Short name T970
Test name
Test status
Simulation time 843223773 ps
CPU time 2.56 seconds
Started Sep 01 12:28:10 PM UTC 24
Finished Sep 01 12:28:14 PM UTC 24
Peak memory 215948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992581936 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.3992581936
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1935373884
Short name T967
Test name
Test status
Simulation time 94581742 ps
CPU time 4.02 seconds
Started Sep 01 12:28:07 PM UTC 24
Finished Sep 01 12:28:12 PM UTC 24
Peak memory 226680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935373884 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.1935373884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2501030220
Short name T983
Test name
Test status
Simulation time 621474019 ps
CPU time 11.5 seconds
Started Sep 01 12:28:07 PM UTC 24
Finished Sep 01 12:28:19 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501030220 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.2501030220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.3760218857
Short name T964
Test name
Test status
Simulation time 295887614 ps
CPU time 2.34 seconds
Started Sep 01 12:28:08 PM UTC 24
Finished Sep 01 12:28:11 PM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760218857 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3760218857
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1302501334
Short name T972
Test name
Test status
Simulation time 235308689 ps
CPU time 5.34 seconds
Started Sep 01 12:28:08 PM UTC 24
Finished Sep 01 12:28:14 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302501334 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1302501334
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4290503909
Short name T978
Test name
Test status
Simulation time 28497024 ps
CPU time 2.14 seconds
Started Sep 01 12:28:14 PM UTC 24
Finished Sep 01 12:28:17 PM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4290503909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_
with_rand_reset.4290503909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.1865111187
Short name T975
Test name
Test status
Simulation time 48792561 ps
CPU time 1.78 seconds
Started Sep 01 12:28:12 PM UTC 24
Finished Sep 01 12:28:16 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865111187 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1865111187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.2372022832
Short name T973
Test name
Test status
Simulation time 13541442 ps
CPU time 1.07 seconds
Started Sep 01 12:28:12 PM UTC 24
Finished Sep 01 12:28:15 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372022832 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2372022832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1539220088
Short name T977
Test name
Test status
Simulation time 1084347532 ps
CPU time 2.75 seconds
Started Sep 01 12:28:12 PM UTC 24
Finished Sep 01 12:28:17 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539220088 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.1539220088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.945111025
Short name T974
Test name
Test status
Simulation time 897919019 ps
CPU time 4.61 seconds
Started Sep 01 12:28:10 PM UTC 24
Finished Sep 01 12:28:16 PM UTC 24
Peak memory 226612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945111025 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.945111025
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1909438253
Short name T985
Test name
Test status
Simulation time 583393571 ps
CPU time 8.33 seconds
Started Sep 01 12:28:10 PM UTC 24
Finished Sep 01 12:28:20 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909438253 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.1909438253
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.1207584496
Short name T971
Test name
Test status
Simulation time 142041142 ps
CPU time 1.54 seconds
Started Sep 01 12:28:11 PM UTC 24
Finished Sep 01 12:28:14 PM UTC 24
Peak memory 226340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207584496 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1207584496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.2633184806
Short name T982
Test name
Test status
Simulation time 500017114 ps
CPU time 5.08 seconds
Started Sep 01 12:28:12 PM UTC 24
Finished Sep 01 12:28:19 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633184806 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.2633184806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4076725418
Short name T988
Test name
Test status
Simulation time 116979604 ps
CPU time 3.04 seconds
Started Sep 01 12:28:16 PM UTC 24
Finished Sep 01 12:28:21 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4076725418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_
with_rand_reset.4076725418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.2663922267
Short name T980
Test name
Test status
Simulation time 13074898 ps
CPU time 1.34 seconds
Started Sep 01 12:28:15 PM UTC 24
Finished Sep 01 12:28:17 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663922267 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2663922267
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.1598630117
Short name T979
Test name
Test status
Simulation time 8894941 ps
CPU time 1.24 seconds
Started Sep 01 12:28:15 PM UTC 24
Finished Sep 01 12:28:17 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598630117 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1598630117
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2111317484
Short name T986
Test name
Test status
Simulation time 25190591 ps
CPU time 2.24 seconds
Started Sep 01 12:28:16 PM UTC 24
Finished Sep 01 12:28:20 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111317484 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.2111317484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.879939723
Short name T981
Test name
Test status
Simulation time 289031479 ps
CPU time 2.7 seconds
Started Sep 01 12:28:14 PM UTC 24
Finished Sep 01 12:28:18 PM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879939723 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.879939723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1483756896
Short name T996
Test name
Test status
Simulation time 419683747 ps
CPU time 8.54 seconds
Started Sep 01 12:28:14 PM UTC 24
Finished Sep 01 12:28:23 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483756896 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.1483756896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.1310806369
Short name T984
Test name
Test status
Simulation time 37772233 ps
CPU time 3.29 seconds
Started Sep 01 12:28:15 PM UTC 24
Finished Sep 01 12:28:19 PM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310806369 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1310806369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.3730536908
Short name T172
Test name
Test status
Simulation time 117963544 ps
CPU time 6.54 seconds
Started Sep 01 12:28:15 PM UTC 24
Finished Sep 01 12:28:23 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730536908 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.3730536908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1739930267
Short name T991
Test name
Test status
Simulation time 304179720 ps
CPU time 2.06 seconds
Started Sep 01 12:28:19 PM UTC 24
Finished Sep 01 12:28:22 PM UTC 24
Peak memory 226208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1739930267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_
with_rand_reset.1739930267
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2360935420
Short name T989
Test name
Test status
Simulation time 11559311 ps
CPU time 1.49 seconds
Started Sep 01 12:28:19 PM UTC 24
Finished Sep 01 12:28:22 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360935420 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2360935420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.3222965260
Short name T987
Test name
Test status
Simulation time 34952102 ps
CPU time 1.15 seconds
Started Sep 01 12:28:18 PM UTC 24
Finished Sep 01 12:28:21 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222965260 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3222965260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3063445939
Short name T992
Test name
Test status
Simulation time 31747412 ps
CPU time 2.48 seconds
Started Sep 01 12:28:19 PM UTC 24
Finished Sep 01 12:28:23 PM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063445939 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.3063445939
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3334198988
Short name T994
Test name
Test status
Simulation time 315109256 ps
CPU time 5.18 seconds
Started Sep 01 12:28:16 PM UTC 24
Finished Sep 01 12:28:23 PM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334198988 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.3334198988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1715253185
Short name T1005
Test name
Test status
Simulation time 1060094944 ps
CPU time 9.65 seconds
Started Sep 01 12:28:16 PM UTC 24
Finished Sep 01 12:28:28 PM UTC 24
Peak memory 232812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715253185 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.1715253185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.4245027280
Short name T990
Test name
Test status
Simulation time 41871468 ps
CPU time 2.68 seconds
Started Sep 01 12:28:17 PM UTC 24
Finished Sep 01 12:28:22 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245027280 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4245027280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.906336510
Short name T180
Test name
Test status
Simulation time 510055215 ps
CPU time 7.56 seconds
Started Sep 01 12:28:18 PM UTC 24
Finished Sep 01 12:28:27 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906336510 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.906336510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2448508559
Short name T1002
Test name
Test status
Simulation time 165930644 ps
CPU time 3.11 seconds
Started Sep 01 12:28:22 PM UTC 24
Finished Sep 01 12:28:27 PM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2448508559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_
with_rand_reset.2448508559
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1481726998
Short name T997
Test name
Test status
Simulation time 14355824 ps
CPU time 1.64 seconds
Started Sep 01 12:28:21 PM UTC 24
Finished Sep 01 12:28:24 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481726998 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1481726998
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.941042952
Short name T995
Test name
Test status
Simulation time 33418272 ps
CPU time 1.07 seconds
Started Sep 01 12:28:21 PM UTC 24
Finished Sep 01 12:28:23 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941042952 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.941042952
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1939355324
Short name T1003
Test name
Test status
Simulation time 121347067 ps
CPU time 3.42 seconds
Started Sep 01 12:28:22 PM UTC 24
Finished Sep 01 12:28:27 PM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939355324 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.1939355324
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2130169958
Short name T999
Test name
Test status
Simulation time 174223728 ps
CPU time 4.67 seconds
Started Sep 01 12:28:20 PM UTC 24
Finished Sep 01 12:28:26 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130169958 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.2130169958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.983021123
Short name T1024
Test name
Test status
Simulation time 909587964 ps
CPU time 14.32 seconds
Started Sep 01 12:28:21 PM UTC 24
Finished Sep 01 12:28:37 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983021123 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.983021123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.876025771
Short name T998
Test name
Test status
Simulation time 196480085 ps
CPU time 3.05 seconds
Started Sep 01 12:28:21 PM UTC 24
Finished Sep 01 12:28:25 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876025771 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.876025771
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3404431177
Short name T1004
Test name
Test status
Simulation time 25526739 ps
CPU time 1.32 seconds
Started Sep 01 12:28:25 PM UTC 24
Finished Sep 01 12:28:27 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3404431177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_
with_rand_reset.3404431177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.4178337172
Short name T1006
Test name
Test status
Simulation time 60612581 ps
CPU time 1.77 seconds
Started Sep 01 12:28:25 PM UTC 24
Finished Sep 01 12:28:28 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178337172 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4178337172
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.2508139249
Short name T1000
Test name
Test status
Simulation time 12870669 ps
CPU time 1.19 seconds
Started Sep 01 12:28:24 PM UTC 24
Finished Sep 01 12:28:26 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508139249 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2508139249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1184686377
Short name T1008
Test name
Test status
Simulation time 381332474 ps
CPU time 2.79 seconds
Started Sep 01 12:28:25 PM UTC 24
Finished Sep 01 12:28:29 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184686377 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.1184686377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1910311786
Short name T1001
Test name
Test status
Simulation time 127762236 ps
CPU time 2.24 seconds
Started Sep 01 12:28:23 PM UTC 24
Finished Sep 01 12:28:27 PM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910311786 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.1910311786
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3633146420
Short name T1014
Test name
Test status
Simulation time 521855361 ps
CPU time 7.26 seconds
Started Sep 01 12:28:23 PM UTC 24
Finished Sep 01 12:28:32 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633146420 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.3633146420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3934751019
Short name T1007
Test name
Test status
Simulation time 100840808 ps
CPU time 4 seconds
Started Sep 01 12:28:24 PM UTC 24
Finished Sep 01 12:28:29 PM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934751019 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3934751019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2682348381
Short name T1013
Test name
Test status
Simulation time 28173085 ps
CPU time 1.79 seconds
Started Sep 01 12:28:29 PM UTC 24
Finished Sep 01 12:28:32 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2682348381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_
with_rand_reset.2682348381
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.4024374232
Short name T1011
Test name
Test status
Simulation time 44356082 ps
CPU time 1.55 seconds
Started Sep 01 12:28:27 PM UTC 24
Finished Sep 01 12:28:30 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024374232 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4024374232
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.1543350741
Short name T1010
Test name
Test status
Simulation time 12919405 ps
CPU time 1.14 seconds
Started Sep 01 12:28:27 PM UTC 24
Finished Sep 01 12:28:30 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543350741 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1543350741
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4203834491
Short name T1012
Test name
Test status
Simulation time 65252879 ps
CPU time 2.61 seconds
Started Sep 01 12:28:28 PM UTC 24
Finished Sep 01 12:28:31 PM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203834491 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.4203834491
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3121187630
Short name T1009
Test name
Test status
Simulation time 377658021 ps
CPU time 2.31 seconds
Started Sep 01 12:28:26 PM UTC 24
Finished Sep 01 12:28:29 PM UTC 24
Peak memory 226544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121187630 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.3121187630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.233200491
Short name T1022
Test name
Test status
Simulation time 238460420 ps
CPU time 7.72 seconds
Started Sep 01 12:28:27 PM UTC 24
Finished Sep 01 12:28:36 PM UTC 24
Peak memory 232760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233200491 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.233200491
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1234712764
Short name T1015
Test name
Test status
Simulation time 69662047 ps
CPU time 3.82 seconds
Started Sep 01 12:28:27 PM UTC 24
Finished Sep 01 12:28:32 PM UTC 24
Peak memory 228516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234712764 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1234712764
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2144155344
Short name T173
Test name
Test status
Simulation time 117479324 ps
CPU time 4.47 seconds
Started Sep 01 12:28:27 PM UTC 24
Finished Sep 01 12:28:33 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144155344 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.2144155344
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1934130573
Short name T1021
Test name
Test status
Simulation time 168185535 ps
CPU time 2.78 seconds
Started Sep 01 12:28:31 PM UTC 24
Finished Sep 01 12:28:35 PM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1934130573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_
with_rand_reset.1934130573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1172169990
Short name T1018
Test name
Test status
Simulation time 26792560 ps
CPU time 1.61 seconds
Started Sep 01 12:28:30 PM UTC 24
Finished Sep 01 12:28:33 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172169990 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1172169990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.1406576731
Short name T1017
Test name
Test status
Simulation time 25482124 ps
CPU time 1.17 seconds
Started Sep 01 12:28:30 PM UTC 24
Finished Sep 01 12:28:32 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406576731 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1406576731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.375799442
Short name T1020
Test name
Test status
Simulation time 251706974 ps
CPU time 3.51 seconds
Started Sep 01 12:28:30 PM UTC 24
Finished Sep 01 12:28:35 PM UTC 24
Peak memory 215948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375799442 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.375799442
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2371373951
Short name T1016
Test name
Test status
Simulation time 184230724 ps
CPU time 2.42 seconds
Started Sep 01 12:28:29 PM UTC 24
Finished Sep 01 12:28:32 PM UTC 24
Peak memory 226576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371373951 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.2371373951
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.731006685
Short name T1037
Test name
Test status
Simulation time 3224623854 ps
CPU time 10.61 seconds
Started Sep 01 12:28:29 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 232780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731006685 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.731006685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3570553431
Short name T1019
Test name
Test status
Simulation time 1496917023 ps
CPU time 3.7 seconds
Started Sep 01 12:28:29 PM UTC 24
Finished Sep 01 12:28:34 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570553431 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3570553431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3308537517
Short name T179
Test name
Test status
Simulation time 157801943 ps
CPU time 6.49 seconds
Started Sep 01 12:28:29 PM UTC 24
Finished Sep 01 12:28:37 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308537517 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.3308537517
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3902377502
Short name T1028
Test name
Test status
Simulation time 230127830 ps
CPU time 3.07 seconds
Started Sep 01 12:28:34 PM UTC 24
Finished Sep 01 12:28:38 PM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3902377502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_
with_rand_reset.3902377502
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.1157184043
Short name T1023
Test name
Test status
Simulation time 34456596 ps
CPU time 1.51 seconds
Started Sep 01 12:28:34 PM UTC 24
Finished Sep 01 12:28:37 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157184043 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1157184043
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1962157735
Short name T993
Test name
Test status
Simulation time 14041090 ps
CPU time 1.16 seconds
Started Sep 01 12:28:33 PM UTC 24
Finished Sep 01 12:28:36 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962157735 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1962157735
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1652573461
Short name T1031
Test name
Test status
Simulation time 237174986 ps
CPU time 4.04 seconds
Started Sep 01 12:28:34 PM UTC 24
Finished Sep 01 12:28:39 PM UTC 24
Peak memory 216068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652573461 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.1652573461
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.435477171
Short name T1025
Test name
Test status
Simulation time 524178247 ps
CPU time 4.66 seconds
Started Sep 01 12:28:31 PM UTC 24
Finished Sep 01 12:28:37 PM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435477171 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.435477171
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3219891567
Short name T1027
Test name
Test status
Simulation time 71486062 ps
CPU time 4.13 seconds
Started Sep 01 12:28:32 PM UTC 24
Finished Sep 01 12:28:38 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219891567 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.3219891567
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.534204887
Short name T1026
Test name
Test status
Simulation time 52437333 ps
CPU time 3.97 seconds
Started Sep 01 12:28:32 PM UTC 24
Finished Sep 01 12:28:38 PM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534204887 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.534204887
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.220403242
Short name T1040
Test name
Test status
Simulation time 74605384 ps
CPU time 2.5 seconds
Started Sep 01 12:28:37 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=220403242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_w
ith_rand_reset.220403242
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3175488190
Short name T1030
Test name
Test status
Simulation time 11628472 ps
CPU time 1.54 seconds
Started Sep 01 12:28:36 PM UTC 24
Finished Sep 01 12:28:39 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175488190 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3175488190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.754984702
Short name T1029
Test name
Test status
Simulation time 39432068 ps
CPU time 1.04 seconds
Started Sep 01 12:28:36 PM UTC 24
Finished Sep 01 12:28:39 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754984702 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.754984702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1758516907
Short name T1046
Test name
Test status
Simulation time 44648720 ps
CPU time 3.65 seconds
Started Sep 01 12:28:37 PM UTC 24
Finished Sep 01 12:28:42 PM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758516907 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.1758516907
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1131855376
Short name T1032
Test name
Test status
Simulation time 95954964 ps
CPU time 4.1 seconds
Started Sep 01 12:28:34 PM UTC 24
Finished Sep 01 12:28:39 PM UTC 24
Peak memory 226544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131855376 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.1131855376
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3166711717
Short name T1048
Test name
Test status
Simulation time 178612506 ps
CPU time 6.35 seconds
Started Sep 01 12:28:35 PM UTC 24
Finished Sep 01 12:28:43 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166711717 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.3166711717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3038298139
Short name T1033
Test name
Test status
Simulation time 37903414 ps
CPU time 3.16 seconds
Started Sep 01 12:28:35 PM UTC 24
Finished Sep 01 12:28:40 PM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038298139 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3038298139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.3309440610
Short name T917
Test name
Test status
Simulation time 900711524 ps
CPU time 8.61 seconds
Started Sep 01 12:27:30 PM UTC 24
Finished Sep 01 12:27:39 PM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309440610 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3309440610
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.451211071
Short name T953
Test name
Test status
Simulation time 898509284 ps
CPU time 35.63 seconds
Started Sep 01 12:27:29 PM UTC 24
Finished Sep 01 12:28:06 PM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451211071 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.451211071
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1655993961
Short name T910
Test name
Test status
Simulation time 48052828 ps
CPU time 1.73 seconds
Started Sep 01 12:27:27 PM UTC 24
Finished Sep 01 12:27:30 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655993961 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1655993961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1850046411
Short name T912
Test name
Test status
Simulation time 77412724 ps
CPU time 2.36 seconds
Started Sep 01 12:27:31 PM UTC 24
Finished Sep 01 12:27:34 PM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1850046411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w
ith_rand_reset.1850046411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.2719277828
Short name T123
Test name
Test status
Simulation time 29221811 ps
CPU time 1.81 seconds
Started Sep 01 12:27:29 PM UTC 24
Finished Sep 01 12:27:31 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719277828 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2719277828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.1335350253
Short name T907
Test name
Test status
Simulation time 45617513 ps
CPU time 1.08 seconds
Started Sep 01 12:27:26 PM UTC 24
Finished Sep 01 12:27:28 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335350253 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1335350253
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3279357533
Short name T124
Test name
Test status
Simulation time 121696176 ps
CPU time 2.98 seconds
Started Sep 01 12:27:30 PM UTC 24
Finished Sep 01 12:27:34 PM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279357533 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.3279357533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1864127977
Short name T91
Test name
Test status
Simulation time 76793000 ps
CPU time 4.91 seconds
Started Sep 01 12:27:22 PM UTC 24
Finished Sep 01 12:27:28 PM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864127977 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.1864127977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3521671416
Short name T908
Test name
Test status
Simulation time 63968859 ps
CPU time 3.99 seconds
Started Sep 01 12:27:24 PM UTC 24
Finished Sep 01 12:27:29 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521671416 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3521671416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.104929669
Short name T1035
Test name
Test status
Simulation time 26960417 ps
CPU time 1.08 seconds
Started Sep 01 12:28:38 PM UTC 24
Finished Sep 01 12:28:40 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104929669 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.104929669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3750703602
Short name T1034
Test name
Test status
Simulation time 26938332 ps
CPU time 0.98 seconds
Started Sep 01 12:28:38 PM UTC 24
Finished Sep 01 12:28:40 PM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750703602 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3750703602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2599932018
Short name T1036
Test name
Test status
Simulation time 12450152 ps
CPU time 1.18 seconds
Started Sep 01 12:28:38 PM UTC 24
Finished Sep 01 12:28:40 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599932018 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2599932018
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3051302525
Short name T1041
Test name
Test status
Simulation time 144914300 ps
CPU time 1.22 seconds
Started Sep 01 12:28:39 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051302525 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3051302525
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2276417102
Short name T1038
Test name
Test status
Simulation time 16892045 ps
CPU time 1.04 seconds
Started Sep 01 12:28:39 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276417102 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2276417102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1702511585
Short name T1039
Test name
Test status
Simulation time 18851905 ps
CPU time 0.99 seconds
Started Sep 01 12:28:39 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702511585 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1702511585
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.621065460
Short name T1042
Test name
Test status
Simulation time 32573668 ps
CPU time 1.31 seconds
Started Sep 01 12:28:39 PM UTC 24
Finished Sep 01 12:28:41 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621065460 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.621065460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1342200910
Short name T1047
Test name
Test status
Simulation time 16724909 ps
CPU time 1.19 seconds
Started Sep 01 12:28:40 PM UTC 24
Finished Sep 01 12:28:42 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342200910 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1342200910
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.158573748
Short name T1043
Test name
Test status
Simulation time 17115562 ps
CPU time 1 seconds
Started Sep 01 12:28:40 PM UTC 24
Finished Sep 01 12:28:42 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158573748 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.158573748
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3049547479
Short name T1045
Test name
Test status
Simulation time 31264830 ps
CPU time 1.1 seconds
Started Sep 01 12:28:40 PM UTC 24
Finished Sep 01 12:28:42 PM UTC 24
Peak memory 213404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049547479 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3049547479
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.3150106790
Short name T926
Test name
Test status
Simulation time 127904874 ps
CPU time 9.91 seconds
Started Sep 01 12:27:38 PM UTC 24
Finished Sep 01 12:27:49 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150106790 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3150106790
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.50152210
Short name T925
Test name
Test status
Simulation time 1723745607 ps
CPU time 11.34 seconds
Started Sep 01 12:27:37 PM UTC 24
Finished Sep 01 12:27:49 PM UTC 24
Peak memory 215936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50152210 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.50152210
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2193052792
Short name T914
Test name
Test status
Simulation time 65456589 ps
CPU time 1.55 seconds
Started Sep 01 12:27:34 PM UTC 24
Finished Sep 01 12:27:37 PM UTC 24
Peak memory 213128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193052792 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2193052792
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4282726514
Short name T920
Test name
Test status
Simulation time 55471711 ps
CPU time 3.47 seconds
Started Sep 01 12:27:38 PM UTC 24
Finished Sep 01 12:27:42 PM UTC 24
Peak memory 226244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4282726514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w
ith_rand_reset.4282726514
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1440559521
Short name T916
Test name
Test status
Simulation time 29451725 ps
CPU time 2.19 seconds
Started Sep 01 12:27:35 PM UTC 24
Finished Sep 01 12:27:39 PM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440559521 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1440559521
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.3343143155
Short name T913
Test name
Test status
Simulation time 46516948 ps
CPU time 1.31 seconds
Started Sep 01 12:27:34 PM UTC 24
Finished Sep 01 12:27:37 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343143155 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3343143155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2833001993
Short name T919
Test name
Test status
Simulation time 47816424 ps
CPU time 3.03 seconds
Started Sep 01 12:27:38 PM UTC 24
Finished Sep 01 12:27:42 PM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833001993 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.2833001993
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.44048492
Short name T99
Test name
Test status
Simulation time 101973512 ps
CPU time 1.91 seconds
Started Sep 01 12:27:31 PM UTC 24
Finished Sep 01 12:27:34 PM UTC 24
Peak memory 223896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44048492 -assert nopostproc +UVM_T
ESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.44048492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.997243696
Short name T96
Test name
Test status
Simulation time 1398942333 ps
CPU time 5.92 seconds
Started Sep 01 12:27:32 PM UTC 24
Finished Sep 01 12:27:39 PM UTC 24
Peak memory 226672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997243696 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.997243696
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.850398539
Short name T915
Test name
Test status
Simulation time 207212976 ps
CPU time 4.2 seconds
Started Sep 01 12:27:33 PM UTC 24
Finished Sep 01 12:27:38 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850398539 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.850398539
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.485854209
Short name T418
Test name
Test status
Simulation time 220234686 ps
CPU time 6.84 seconds
Started Sep 01 12:27:34 PM UTC 24
Finished Sep 01 12:27:42 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485854209 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.485854209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.3547807988
Short name T1044
Test name
Test status
Simulation time 24085063 ps
CPU time 1.09 seconds
Started Sep 01 12:28:40 PM UTC 24
Finished Sep 01 12:28:42 PM UTC 24
Peak memory 213420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547807988 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3547807988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2598986488
Short name T1052
Test name
Test status
Simulation time 214070568 ps
CPU time 1.27 seconds
Started Sep 01 12:28:41 PM UTC 24
Finished Sep 01 12:28:44 PM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598986488 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2598986488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.2131489387
Short name T1050
Test name
Test status
Simulation time 64283236 ps
CPU time 1.11 seconds
Started Sep 01 12:28:41 PM UTC 24
Finished Sep 01 12:28:44 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131489387 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2131489387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.788737495
Short name T1049
Test name
Test status
Simulation time 30069101 ps
CPU time 1.09 seconds
Started Sep 01 12:28:41 PM UTC 24
Finished Sep 01 12:28:44 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788737495 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.788737495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.30321877
Short name T1053
Test name
Test status
Simulation time 14587520 ps
CPU time 1.14 seconds
Started Sep 01 12:28:42 PM UTC 24
Finished Sep 01 12:28:44 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30321877 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.30321877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.3762323813
Short name T1051
Test name
Test status
Simulation time 9365738 ps
CPU time 1 seconds
Started Sep 01 12:28:42 PM UTC 24
Finished Sep 01 12:28:44 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762323813 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3762323813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.325074442
Short name T1054
Test name
Test status
Simulation time 36306460 ps
CPU time 1.24 seconds
Started Sep 01 12:28:42 PM UTC 24
Finished Sep 01 12:28:44 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325074442 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.325074442
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3402558038
Short name T1056
Test name
Test status
Simulation time 12258278 ps
CPU time 1.13 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402558038 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3402558038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3867053139
Short name T1055
Test name
Test status
Simulation time 14568154 ps
CPU time 1.06 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867053139 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3867053139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3097232861
Short name T1057
Test name
Test status
Simulation time 13901296 ps
CPU time 1.1 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097232861 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3097232861
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.2722010108
Short name T938
Test name
Test status
Simulation time 262840827 ps
CPU time 12.14 seconds
Started Sep 01 12:27:44 PM UTC 24
Finished Sep 01 12:27:57 PM UTC 24
Peak memory 216068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722010108 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2722010108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1207892811
Short name T941
Test name
Test status
Simulation time 2482573606 ps
CPU time 15.11 seconds
Started Sep 01 12:27:43 PM UTC 24
Finished Sep 01 12:27:59 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207892811 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1207892811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3702991841
Short name T922
Test name
Test status
Simulation time 118126244 ps
CPU time 2.09 seconds
Started Sep 01 12:27:41 PM UTC 24
Finished Sep 01 12:27:44 PM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702991841 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3702991841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3117637561
Short name T927
Test name
Test status
Simulation time 155750197 ps
CPU time 3.44 seconds
Started Sep 01 12:27:45 PM UTC 24
Finished Sep 01 12:27:49 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3117637561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w
ith_rand_reset.3117637561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.664759986
Short name T924
Test name
Test status
Simulation time 151660707 ps
CPU time 2.12 seconds
Started Sep 01 12:27:43 PM UTC 24
Finished Sep 01 12:27:46 PM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664759986 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.664759986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.1219159755
Short name T921
Test name
Test status
Simulation time 26233719 ps
CPU time 1.2 seconds
Started Sep 01 12:27:41 PM UTC 24
Finished Sep 01 12:27:43 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219159755 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1219159755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2760261303
Short name T930
Test name
Test status
Simulation time 152024088 ps
CPU time 6 seconds
Started Sep 01 12:27:44 PM UTC 24
Finished Sep 01 12:27:51 PM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760261303 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.2760261303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3268797356
Short name T100
Test name
Test status
Simulation time 313576255 ps
CPU time 3.6 seconds
Started Sep 01 12:27:39 PM UTC 24
Finished Sep 01 12:27:44 PM UTC 24
Peak memory 226512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268797356 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.3268797356
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3488695198
Short name T929
Test name
Test status
Simulation time 298873984 ps
CPU time 10.17 seconds
Started Sep 01 12:27:39 PM UTC 24
Finished Sep 01 12:27:51 PM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488695198 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.3488695198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.263826034
Short name T923
Test name
Test status
Simulation time 85858574 ps
CPU time 3.56 seconds
Started Sep 01 12:27:39 PM UTC 24
Finished Sep 01 12:27:44 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263826034 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.263826034
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.4220893418
Short name T419
Test name
Test status
Simulation time 225254414 ps
CPU time 12.66 seconds
Started Sep 01 12:27:40 PM UTC 24
Finished Sep 01 12:27:54 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220893418 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.4220893418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2527133618
Short name T1058
Test name
Test status
Simulation time 11062155 ps
CPU time 1.05 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527133618 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2527133618
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.525772419
Short name T1059
Test name
Test status
Simulation time 26071727 ps
CPU time 1.07 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525772419 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.525772419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2005030837
Short name T1060
Test name
Test status
Simulation time 12788438 ps
CPU time 1.01 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005030837 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2005030837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1138613602
Short name T1061
Test name
Test status
Simulation time 13041626 ps
CPU time 1.13 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:45 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138613602 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1138613602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3690187927
Short name T1062
Test name
Test status
Simulation time 20250896 ps
CPU time 1.18 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:46 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690187927 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3690187927
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.2728885590
Short name T1064
Test name
Test status
Simulation time 16152640 ps
CPU time 1.11 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:46 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728885590 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2728885590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.294742000
Short name T1063
Test name
Test status
Simulation time 90275180 ps
CPU time 1.08 seconds
Started Sep 01 12:28:43 PM UTC 24
Finished Sep 01 12:28:46 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294742000 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.294742000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.3480276899
Short name T1065
Test name
Test status
Simulation time 41848436 ps
CPU time 1.09 seconds
Started Sep 01 12:28:44 PM UTC 24
Finished Sep 01 12:28:46 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480276899 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3480276899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.4209700137
Short name T1067
Test name
Test status
Simulation time 81816697 ps
CPU time 1.36 seconds
Started Sep 01 12:28:45 PM UTC 24
Finished Sep 01 12:28:47 PM UTC 24
Peak memory 213572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209700137 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4209700137
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.1391151673
Short name T1066
Test name
Test status
Simulation time 18710022 ps
CPU time 1.16 seconds
Started Sep 01 12:28:45 PM UTC 24
Finished Sep 01 12:28:47 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391151673 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1391151673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.560270256
Short name T934
Test name
Test status
Simulation time 31609356 ps
CPU time 2.15 seconds
Started Sep 01 12:27:52 PM UTC 24
Finished Sep 01 12:27:55 PM UTC 24
Peak memory 226308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=560270256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_wi
th_rand_reset.560270256
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.4092627423
Short name T932
Test name
Test status
Simulation time 13468185 ps
CPU time 1.24 seconds
Started Sep 01 12:27:50 PM UTC 24
Finished Sep 01 12:27:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092627423 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.4092627423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.2615154067
Short name T931
Test name
Test status
Simulation time 10316805 ps
CPU time 1.13 seconds
Started Sep 01 12:27:49 PM UTC 24
Finished Sep 01 12:27:51 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615154067 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2615154067
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1951834013
Short name T933
Test name
Test status
Simulation time 22456161 ps
CPU time 1.68 seconds
Started Sep 01 12:27:50 PM UTC 24
Finished Sep 01 12:27:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951834013 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1951834013
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.561552036
Short name T98
Test name
Test status
Simulation time 131972846 ps
CPU time 2.61 seconds
Started Sep 01 12:27:45 PM UTC 24
Finished Sep 01 12:27:49 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561552036 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.561552036
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.996821958
Short name T935
Test name
Test status
Simulation time 228382464 ps
CPU time 8.86 seconds
Started Sep 01 12:27:45 PM UTC 24
Finished Sep 01 12:27:55 PM UTC 24
Peak memory 226672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996821958 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.996821958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.771041929
Short name T928
Test name
Test status
Simulation time 126943026 ps
CPU time 2.2 seconds
Started Sep 01 12:27:47 PM UTC 24
Finished Sep 01 12:27:50 PM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771041929 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.771041929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.3563243473
Short name T165
Test name
Test status
Simulation time 264822648 ps
CPU time 5.68 seconds
Started Sep 01 12:27:49 PM UTC 24
Finished Sep 01 12:27:56 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563243473 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.3563243473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1378290298
Short name T943
Test name
Test status
Simulation time 42762369 ps
CPU time 2.61 seconds
Started Sep 01 12:27:56 PM UTC 24
Finished Sep 01 12:28:00 PM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1378290298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w
ith_rand_reset.1378290298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3474182251
Short name T937
Test name
Test status
Simulation time 27547369 ps
CPU time 1.84 seconds
Started Sep 01 12:27:54 PM UTC 24
Finished Sep 01 12:27:57 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474182251 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3474182251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.2313281416
Short name T936
Test name
Test status
Simulation time 38946681 ps
CPU time 1.16 seconds
Started Sep 01 12:27:53 PM UTC 24
Finished Sep 01 12:27:55 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313281416 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2313281416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.322076904
Short name T945
Test name
Test status
Simulation time 360902311 ps
CPU time 5.89 seconds
Started Sep 01 12:27:55 PM UTC 24
Finished Sep 01 12:28:02 PM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322076904 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.322076904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.803239191
Short name T940
Test name
Test status
Simulation time 133151045 ps
CPU time 5.3 seconds
Started Sep 01 12:27:52 PM UTC 24
Finished Sep 01 12:27:58 PM UTC 24
Peak memory 230568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803239191 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.803239191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.488875151
Short name T950
Test name
Test status
Simulation time 160968274 ps
CPU time 10.95 seconds
Started Sep 01 12:27:52 PM UTC 24
Finished Sep 01 12:28:04 PM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488875151 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.488875151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.121932501
Short name T939
Test name
Test status
Simulation time 1798462949 ps
CPU time 4.1 seconds
Started Sep 01 12:27:52 PM UTC 24
Finished Sep 01 12:27:57 PM UTC 24
Peak memory 232664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121932501 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.121932501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3602948926
Short name T947
Test name
Test status
Simulation time 44617217 ps
CPU time 2.42 seconds
Started Sep 01 12:28:00 PM UTC 24
Finished Sep 01 12:28:03 PM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3602948926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w
ith_rand_reset.3602948926
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2414287113
Short name T944
Test name
Test status
Simulation time 28641838 ps
CPU time 1.55 seconds
Started Sep 01 12:27:58 PM UTC 24
Finished Sep 01 12:28:00 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414287113 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2414287113
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.351986061
Short name T942
Test name
Test status
Simulation time 28661991 ps
CPU time 1 seconds
Started Sep 01 12:27:58 PM UTC 24
Finished Sep 01 12:28:00 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351986061 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.351986061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2595720620
Short name T951
Test name
Test status
Simulation time 85344450 ps
CPU time 5.08 seconds
Started Sep 01 12:27:59 PM UTC 24
Finished Sep 01 12:28:05 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595720620 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.2595720620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.24616384
Short name T97
Test name
Test status
Simulation time 75636085 ps
CPU time 2.22 seconds
Started Sep 01 12:27:56 PM UTC 24
Finished Sep 01 12:28:00 PM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24616384 -assert nopostproc +UVM_T
ESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.24616384
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3704746743
Short name T946
Test name
Test status
Simulation time 276457663 ps
CPU time 5.63 seconds
Started Sep 01 12:27:56 PM UTC 24
Finished Sep 01 12:28:03 PM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704746743 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.3704746743
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.3240815357
Short name T954
Test name
Test status
Simulation time 538800183 ps
CPU time 8.01 seconds
Started Sep 01 12:27:57 PM UTC 24
Finished Sep 01 12:28:06 PM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240815357 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3240815357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.1652513505
Short name T169
Test name
Test status
Simulation time 328835452 ps
CPU time 7.22 seconds
Started Sep 01 12:27:58 PM UTC 24
Finished Sep 01 12:28:06 PM UTC 24
Peak memory 215996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652513505 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.1652513505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2724926705
Short name T956
Test name
Test status
Simulation time 26073322 ps
CPU time 1.67 seconds
Started Sep 01 12:28:05 PM UTC 24
Finished Sep 01 12:28:07 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2724926705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w
ith_rand_reset.2724926705
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.3736894148
Short name T955
Test name
Test status
Simulation time 46515785 ps
CPU time 1.89 seconds
Started Sep 01 12:28:03 PM UTC 24
Finished Sep 01 12:28:06 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736894148 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3736894148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.1991940834
Short name T948
Test name
Test status
Simulation time 9919738 ps
CPU time 1.12 seconds
Started Sep 01 12:28:01 PM UTC 24
Finished Sep 01 12:28:03 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991940834 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1991940834
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1890688204
Short name T960
Test name
Test status
Simulation time 34119678 ps
CPU time 3.1 seconds
Started Sep 01 12:28:05 PM UTC 24
Finished Sep 01 12:28:09 PM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890688204 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.1890688204
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3409724758
Short name T949
Test name
Test status
Simulation time 95278578 ps
CPU time 2.65 seconds
Started Sep 01 12:28:00 PM UTC 24
Finished Sep 01 12:28:04 PM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409724758 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.3409724758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3556512863
Short name T959
Test name
Test status
Simulation time 294108443 ps
CPU time 6.28 seconds
Started Sep 01 12:28:01 PM UTC 24
Finished Sep 01 12:28:08 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556512863 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.3556512863
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.1662459533
Short name T952
Test name
Test status
Simulation time 60983572 ps
CPU time 3.22 seconds
Started Sep 01 12:28:01 PM UTC 24
Finished Sep 01 12:28:05 PM UTC 24
Peak memory 226272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662459533 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1662459533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.718841469
Short name T167
Test name
Test status
Simulation time 381769599 ps
CPU time 11.08 seconds
Started Sep 01 12:28:01 PM UTC 24
Finished Sep 01 12:28:13 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718841469 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.718841469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1878108601
Short name T963
Test name
Test status
Simulation time 573312981 ps
CPU time 2.72 seconds
Started Sep 01 12:28:06 PM UTC 24
Finished Sep 01 12:28:10 PM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1878108601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w
ith_rand_reset.1878108601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.85854483
Short name T958
Test name
Test status
Simulation time 17657197 ps
CPU time 1.18 seconds
Started Sep 01 12:28:06 PM UTC 24
Finished Sep 01 12:28:08 PM UTC 24
Peak memory 213184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85854483 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.85854483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.2763142277
Short name T957
Test name
Test status
Simulation time 23995385 ps
CPU time 0.96 seconds
Started Sep 01 12:28:06 PM UTC 24
Finished Sep 01 12:28:08 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763142277 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2763142277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4183687692
Short name T962
Test name
Test status
Simulation time 71281179 ps
CPU time 2.04 seconds
Started Sep 01 12:28:06 PM UTC 24
Finished Sep 01 12:28:09 PM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183687692 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.4183687692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2334484171
Short name T961
Test name
Test status
Simulation time 346482776 ps
CPU time 3.28 seconds
Started Sep 01 12:28:05 PM UTC 24
Finished Sep 01 12:28:09 PM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334484171 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.2334484171
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3889642703
Short name T976
Test name
Test status
Simulation time 159211839 ps
CPU time 10.68 seconds
Started Sep 01 12:28:05 PM UTC 24
Finished Sep 01 12:28:17 PM UTC 24
Peak memory 232656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889642703 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.3889642703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.2996977344
Short name T968
Test name
Test status
Simulation time 234801358 ps
CPU time 6.59 seconds
Started Sep 01 12:28:05 PM UTC 24
Finished Sep 01 12:28:13 PM UTC 24
Peak memory 228396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996977344 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2996977344
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.2314206898
Short name T4
Test name
Test status
Simulation time 30299954 ps
CPU time 2.13 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314206898 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2314206898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1959986205
Short name T39
Test name
Test status
Simulation time 1125866889 ps
CPU time 3.28 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:40 PM UTC 24
Peak memory 226100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959986205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1959986205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.2673393483
Short name T11
Test name
Test status
Simulation time 302406186 ps
CPU time 5.37 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 260328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673393483 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2673393483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.3008125274
Short name T2
Test name
Test status
Simulation time 24809324 ps
CPU time 1.88 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 217704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008125274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3008125274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.1571653452
Short name T1
Test name
Test status
Simulation time 33537722 ps
CPU time 1.5 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:38 PM UTC 24
Peak memory 215316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571653452 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1571653452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.1082152024
Short name T14
Test name
Test status
Simulation time 217647714 ps
CPU time 1.95 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082152024 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1082152024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.3507202549
Short name T15
Test name
Test status
Simulation time 90629837 ps
CPU time 2.14 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 218344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507202549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3507202549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.746804557
Short name T17
Test name
Test status
Simulation time 281160919 ps
CPU time 2.68 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:39 PM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746804557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.746804557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.3233824806
Short name T231
Test name
Test status
Simulation time 11308283158 ps
CPU time 76.74 seconds
Started Sep 01 01:31:44 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 232300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233824806 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3233824806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.3578677298
Short name T18
Test name
Test status
Simulation time 1838101603 ps
CPU time 5.16 seconds
Started Sep 01 01:30:35 PM UTC 24
Finished Sep 01 01:30:42 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578677298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3578677298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.3045107227
Short name T68
Test name
Test status
Simulation time 28780243 ps
CPU time 0.7 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:48 PM UTC 24
Peak memory 213536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045107227 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3045107227
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.1470082496
Short name T379
Test name
Test status
Simulation time 7894912379 ps
CPU time 82.83 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:33:11 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470082496 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1470082496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.466478071
Short name T70
Test name
Test status
Simulation time 30656365 ps
CPU time 1.89 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:49 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466478071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.466478071
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.2561391167
Short name T190
Test name
Test status
Simulation time 637120564 ps
CPU time 4.5 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561391167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2561391167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.3696696589
Short name T87
Test name
Test status
Simulation time 1492989967 ps
CPU time 6.62 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:53 PM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696696589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3696696589
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.202337011
Short name T220
Test name
Test status
Simulation time 39780747 ps
CPU time 2.92 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 217420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202337011 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.202337011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.33041695
Short name T159
Test name
Test status
Simulation time 41039523 ps
CPU time 2.15 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:49 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33041695 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.33041695
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3725646815
Short name T21
Test name
Test status
Simulation time 43279968 ps
CPU time 2.28 seconds
Started Sep 01 01:31:45 PM UTC 24
Finished Sep 01 01:31:49 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725646815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3725646815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3684863484
Short name T161
Test name
Test status
Simulation time 32916722 ps
CPU time 0.88 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:48 PM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684863484 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3684863484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.1151331761
Short name T188
Test name
Test status
Simulation time 453284889 ps
CPU time 4.56 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 217740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151331761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1151331761
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.2300737059
Short name T36
Test name
Test status
Simulation time 46742957 ps
CPU time 2.88 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 220112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300737059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2300737059
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.321544236
Short name T474
Test name
Test status
Simulation time 21179656 ps
CPU time 0.88 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 213496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321544236 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.321544236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.1358609351
Short name T351
Test name
Test status
Simulation time 53435903 ps
CPU time 3.63 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358609351 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1358609351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.387430580
Short name T135
Test name
Test status
Simulation time 334647922 ps
CPU time 9.56 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387430580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.387430580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.2912681950
Short name T291
Test name
Test status
Simulation time 30165955 ps
CPU time 2.76 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912681950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2912681950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.1171009886
Short name T142
Test name
Test status
Simulation time 240484936 ps
CPU time 3.33 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 220376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171009886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1171009886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_random.607932549
Short name T210
Test name
Test status
Simulation time 291032696 ps
CPU time 4.05 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 218324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607932549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.607932549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.3010330997
Short name T284
Test name
Test status
Simulation time 60841800 ps
CPU time 2.9 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010330997 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3010330997
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.3198006551
Short name T365
Test name
Test status
Simulation time 3739333708 ps
CPU time 24.7 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:29 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198006551 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3198006551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.2487428375
Short name T288
Test name
Test status
Simulation time 65306247 ps
CPU time 3.26 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487428375 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2487428375
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.4131662022
Short name T472
Test name
Test status
Simulation time 35662386 ps
CPU time 2.19 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131662022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.4131662022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.1222344879
Short name T154
Test name
Test status
Simulation time 25023093314 ps
CPU time 60.8 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:33:08 PM UTC 24
Peak memory 232644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222344879 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1222344879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.864094488
Short name T209
Test name
Test status
Simulation time 268142624 ps
CPU time 2.96 seconds
Started Sep 01 01:32:05 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864094488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.864094488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.1864562618
Short name T417
Test name
Test status
Simulation time 38645602 ps
CPU time 1.99 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864562618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1864562618
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.114250926
Short name T477
Test name
Test status
Simulation time 15372142 ps
CPU time 0.93 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:11 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114250926 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.114250926
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.239950690
Short name T326
Test name
Test status
Simulation time 157351898 ps
CPU time 3.29 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:13 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239950690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.239950690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.2184075523
Short name T268
Test name
Test status
Simulation time 104259572 ps
CPU time 1.94 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:12 PM UTC 24
Peak memory 225648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184075523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2184075523
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.2482008565
Short name T117
Test name
Test status
Simulation time 596276175 ps
CPU time 6.06 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482008565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2482008565
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_random.866041395
Short name T312
Test name
Test status
Simulation time 47416652 ps
CPU time 2.98 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 228196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866041395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.866041395
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.2487209693
Short name T476
Test name
Test status
Simulation time 1063854403 ps
CPU time 3.47 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:11 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487209693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2487209693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.1830199981
Short name T464
Test name
Test status
Simulation time 19462785 ps
CPU time 1.72 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830199981 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1830199981
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.4248682363
Short name T475
Test name
Test status
Simulation time 181520333 ps
CPU time 2.44 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248682363 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4248682363
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.1669711827
Short name T536
Test name
Test status
Simulation time 3266080449 ps
CPU time 33.18 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669711827 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1669711827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.2792244247
Short name T258
Test name
Test status
Simulation time 126615386 ps
CPU time 2.45 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:12 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792244247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2792244247
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.37141749
Short name T478
Test name
Test status
Simulation time 376484153 ps
CPU time 4.5 seconds
Started Sep 01 01:32:06 PM UTC 24
Finished Sep 01 01:32:12 PM UTC 24
Peak memory 216104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37141749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.37141749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.24395573
Short name T240
Test name
Test status
Simulation time 6764139051 ps
CPU time 49.72 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:33:00 PM UTC 24
Peak memory 232572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24395573 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.24395573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.134196235
Short name T101
Test name
Test status
Simulation time 153243019 ps
CPU time 6.98 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 232392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=134196235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr
_stress_all_with_rand_reset.134196235
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.1741307695
Short name T327
Test name
Test status
Simulation time 1810836931 ps
CPU time 22.22 seconds
Started Sep 01 01:32:08 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741307695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1741307695
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.1683911738
Short name T420
Test name
Test status
Simulation time 256399499 ps
CPU time 1.96 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:12 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683911738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1683911738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.3706428434
Short name T479
Test name
Test status
Simulation time 15667437 ps
CPU time 0.97 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:14 PM UTC 24
Peak memory 213720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706428434 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3706428434
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.1413361424
Short name T383
Test name
Test status
Simulation time 9119771528 ps
CPU time 19.7 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413361424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1413361424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.2667187955
Short name T262
Test name
Test status
Simulation time 58405751 ps
CPU time 2.52 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:15 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667187955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2667187955
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.1426430872
Short name T431
Test name
Test status
Simulation time 79318499 ps
CPU time 3.38 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 232296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426430872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1426430872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_random.1880339101
Short name T279
Test name
Test status
Simulation time 186654439 ps
CPU time 6.92 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 228240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880339101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1880339101
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.2391297009
Short name T278
Test name
Test status
Simulation time 34909310 ps
CPU time 2.18 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:12 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391297009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2391297009
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.3897647879
Short name T480
Test name
Test status
Simulation time 433475282 ps
CPU time 5.64 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897647879 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3897647879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.713100889
Short name T345
Test name
Test status
Simulation time 95523231 ps
CPU time 2.29 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:12 PM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713100889 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.713100889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.1273341715
Short name T505
Test name
Test status
Simulation time 1241841266 ps
CPU time 19.17 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:30 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273341715 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1273341715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.2278690015
Short name T255
Test name
Test status
Simulation time 257074478 ps
CPU time 5.35 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 224176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278690015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2278690015
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.112006854
Short name T493
Test name
Test status
Simulation time 3092285316 ps
CPU time 10.22 seconds
Started Sep 01 01:32:09 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112006854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.112006854
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.3663370755
Short name T625
Test name
Test status
Simulation time 9221194672 ps
CPU time 74.43 seconds
Started Sep 01 01:32:11 PM UTC 24
Finished Sep 01 01:33:28 PM UTC 24
Peak memory 224292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663370755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3663370755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.2134530296
Short name T170
Test name
Test status
Simulation time 94758762 ps
CPU time 2.89 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134530296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2134530296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.1525076428
Short name T482
Test name
Test status
Simulation time 31470282 ps
CPU time 0.97 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525076428 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1525076428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.794408356
Short name T127
Test name
Test status
Simulation time 153469025 ps
CPU time 2.15 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 226580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794408356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.794408356
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.4288422384
Short name T414
Test name
Test status
Simulation time 106259224 ps
CPU time 2.49 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288422384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4288422384
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.2390527177
Short name T56
Test name
Test status
Simulation time 91741764 ps
CPU time 4.38 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390527177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2390527177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.2977553106
Short name T315
Test name
Test status
Simulation time 86678059 ps
CPU time 3.82 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977553106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2977553106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.3297278016
Short name T358
Test name
Test status
Simulation time 311624083 ps
CPU time 3.52 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297278016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3297278016
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_random.3521812177
Short name T366
Test name
Test status
Simulation time 865248256 ps
CPU time 7.09 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521812177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3521812177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.2112883153
Short name T321
Test name
Test status
Simulation time 315570986 ps
CPU time 7.79 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:21 PM UTC 24
Peak memory 217760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112883153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2112883153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.569072665
Short name T364
Test name
Test status
Simulation time 350604755 ps
CPU time 6.2 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:19 PM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569072665 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.569072665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.2680845521
Short name T486
Test name
Test status
Simulation time 1450174111 ps
CPU time 5.86 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:19 PM UTC 24
Peak memory 217764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680845521 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2680845521
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.1823532060
Short name T432
Test name
Test status
Simulation time 272181953 ps
CPU time 3.91 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823532060 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1823532060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.295614166
Short name T318
Test name
Test status
Simulation time 34295366 ps
CPU time 2.99 seconds
Started Sep 01 01:32:14 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295614166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.295614166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.419796889
Short name T481
Test name
Test status
Simulation time 86828900 ps
CPU time 3.03 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:16 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419796889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.419796889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.3144034823
Short name T834
Test name
Test status
Simulation time 22448573334 ps
CPU time 140.14 seconds
Started Sep 01 01:32:14 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 232344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144034823 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3144034823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.3896207075
Short name T560
Test name
Test status
Simulation time 4996597499 ps
CPU time 32.32 seconds
Started Sep 01 01:32:12 PM UTC 24
Finished Sep 01 01:32:46 PM UTC 24
Peak memory 218272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896207075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3896207075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.1543425425
Short name T483
Test name
Test status
Simulation time 41267735 ps
CPU time 2.04 seconds
Started Sep 01 01:32:14 PM UTC 24
Finished Sep 01 01:32:17 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543425425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1543425425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.3229837768
Short name T489
Test name
Test status
Simulation time 16358288 ps
CPU time 0.89 seconds
Started Sep 01 01:32:18 PM UTC 24
Finished Sep 01 01:32:19 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229837768 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3229837768
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.1773832791
Short name T423
Test name
Test status
Simulation time 2513726681 ps
CPU time 86.71 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:33:44 PM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773832791 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1773832791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.3981994370
Short name T457
Test name
Test status
Simulation time 203695373 ps
CPU time 3.84 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:22 PM UTC 24
Peak memory 231168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981994370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3981994370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.4014208412
Short name T272
Test name
Test status
Simulation time 96788169 ps
CPU time 2.64 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:19 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014208412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4014208412
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.2668472847
Short name T392
Test name
Test status
Simulation time 91988487 ps
CPU time 4.44 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:23 PM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668472847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2668472847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.1994832149
Short name T448
Test name
Test status
Simulation time 175091561 ps
CPU time 3 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:21 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994832149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1994832149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_random.3593070055
Short name T353
Test name
Test status
Simulation time 615003013 ps
CPU time 6.28 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:22 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593070055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3593070055
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.3161933025
Short name T307
Test name
Test status
Simulation time 464063887 ps
CPU time 4.49 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161933025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3161933025
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.2072990629
Short name T484
Test name
Test status
Simulation time 20788806 ps
CPU time 2.19 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072990629 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2072990629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.1456205212
Short name T323
Test name
Test status
Simulation time 26879637 ps
CPU time 2.31 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456205212 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1456205212
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.3349949843
Short name T346
Test name
Test status
Simulation time 449770805 ps
CPU time 6.38 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:22 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349949843 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3349949843
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.3273076329
Short name T494
Test name
Test status
Simulation time 68534339 ps
CPU time 2.84 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:21 PM UTC 24
Peak memory 226532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273076329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3273076329
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.2577248046
Short name T490
Test name
Test status
Simulation time 664427911 ps
CPU time 4.08 seconds
Started Sep 01 01:32:15 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577248046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2577248046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.3887043916
Short name T198
Test name
Test status
Simulation time 6362635717 ps
CPU time 39.89 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:59 PM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887043916 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3887043916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.1775430556
Short name T108
Test name
Test status
Simulation time 209654541 ps
CPU time 14.45 seconds
Started Sep 01 01:32:18 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1775430556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymg
r_stress_all_with_rand_reset.1775430556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.3484351481
Short name T273
Test name
Test status
Simulation time 356339466 ps
CPU time 5.2 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:23 PM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484351481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3484351481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.1751636142
Short name T491
Test name
Test status
Simulation time 43474323 ps
CPU time 1.39 seconds
Started Sep 01 01:32:17 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751636142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1751636142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2268564019
Short name T496
Test name
Test status
Simulation time 36465386 ps
CPU time 0.85 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:23 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268564019 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2268564019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.4087687512
Short name T487
Test name
Test status
Simulation time 121349800 ps
CPU time 1.98 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:23 PM UTC 24
Peak memory 215764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087687512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4087687512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.3567432237
Short name T285
Test name
Test status
Simulation time 213761740 ps
CPU time 4.73 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567432237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3567432237
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_random.2396535403
Short name T500
Test name
Test status
Simulation time 115074936 ps
CPU time 4.77 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396535403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2396535403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.1990440078
Short name T308
Test name
Test status
Simulation time 508798978 ps
CPU time 7.51 seconds
Started Sep 01 01:32:18 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990440078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1990440078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.2454583468
Short name T275
Test name
Test status
Simulation time 23761042 ps
CPU time 2.2 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:23 PM UTC 24
Peak memory 217864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454583468 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2454583468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.778508356
Short name T492
Test name
Test status
Simulation time 21603941 ps
CPU time 1.52 seconds
Started Sep 01 01:32:18 PM UTC 24
Finished Sep 01 01:32:20 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778508356 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.778508356
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.2214550186
Short name T367
Test name
Test status
Simulation time 66879968 ps
CPU time 2.88 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:24 PM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214550186 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2214550186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2105838572
Short name T498
Test name
Test status
Simulation time 371331051 ps
CPU time 3.94 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105838572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2105838572
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.1688084774
Short name T495
Test name
Test status
Simulation time 235270745 ps
CPU time 2.82 seconds
Started Sep 01 01:32:18 PM UTC 24
Finished Sep 01 01:32:22 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688084774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1688084774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.481087554
Short name T352
Test name
Test status
Simulation time 694401717 ps
CPU time 20.31 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:42 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481087554 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.481087554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.2500143758
Short name T524
Test name
Test status
Simulation time 351442282 ps
CPU time 14.93 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:37 PM UTC 24
Peak memory 230152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2500143758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg
r_stress_all_with_rand_reset.2500143758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.884168705
Short name T390
Test name
Test status
Simulation time 325121732 ps
CPU time 8.56 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:30 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884168705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.884168705
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.2521880919
Short name T421
Test name
Test status
Simulation time 160054886 ps
CPU time 3.48 seconds
Started Sep 01 01:32:20 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521880919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2521880919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1100399332
Short name T499
Test name
Test status
Simulation time 42238569 ps
CPU time 1.02 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100399332 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1100399332
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.1771177166
Short name T251
Test name
Test status
Simulation time 139838856 ps
CPU time 2.46 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:27 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771177166 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1771177166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.261598406
Short name T331
Test name
Test status
Simulation time 204068321 ps
CPU time 4.1 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:28 PM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261598406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.261598406
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.4233721181
Short name T360
Test name
Test status
Simulation time 98100222 ps
CPU time 1.89 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 223720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233721181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.4233721181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.590255700
Short name T146
Test name
Test status
Simulation time 60853944 ps
CPU time 2.76 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:27 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590255700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.590255700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_random.1104368715
Short name T398
Test name
Test status
Simulation time 395040568 ps
CPU time 9.11 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:31 PM UTC 24
Peak memory 228452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104368715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1104368715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2862660467
Short name T259
Test name
Test status
Simulation time 47594284 ps
CPU time 2.86 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862660467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2862660467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.584535777
Short name T410
Test name
Test status
Simulation time 376043587 ps
CPU time 3.12 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 218112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584535777 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.584535777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.3546065196
Short name T552
Test name
Test status
Simulation time 1393038948 ps
CPU time 29.28 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:51 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546065196 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3546065196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.1099629865
Short name T411
Test name
Test status
Simulation time 61563538 ps
CPU time 3.88 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099629865 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1099629865
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.879902900
Short name T344
Test name
Test status
Simulation time 150803121 ps
CPU time 1.47 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879902900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.879902900
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.4137411341
Short name T497
Test name
Test status
Simulation time 199289296 ps
CPU time 3.38 seconds
Started Sep 01 01:32:21 PM UTC 24
Finished Sep 01 01:32:25 PM UTC 24
Peak memory 215472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137411341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4137411341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.2024328617
Short name T394
Test name
Test status
Simulation time 65451100 ps
CPU time 2.82 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:27 PM UTC 24
Peak memory 220292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024328617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2024328617
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.119754488
Short name T501
Test name
Test status
Simulation time 110588423 ps
CPU time 1.92 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:26 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119754488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.119754488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.3994879253
Short name T502
Test name
Test status
Simulation time 52860506 ps
CPU time 1.02 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:28 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994879253 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3994879253
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.189037923
Short name T311
Test name
Test status
Simulation time 219009214 ps
CPU time 11.03 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:38 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189037923 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.189037923
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.405452460
Short name T534
Test name
Test status
Simulation time 1209926308 ps
CPU time 13.12 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405452460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.405452460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.1160565943
Short name T319
Test name
Test status
Simulation time 147269407 ps
CPU time 3.38 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:31 PM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160565943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1160565943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.895992293
Short name T305
Test name
Test status
Simulation time 407261192 ps
CPU time 3.85 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:31 PM UTC 24
Peak memory 219956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895992293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.895992293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_random.1125311749
Short name T313
Test name
Test status
Simulation time 87861214 ps
CPU time 5.14 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125311749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1125311749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.1613211875
Short name T384
Test name
Test status
Simulation time 3744103254 ps
CPU time 10.46 seconds
Started Sep 01 01:32:24 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613211875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1613211875
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.2958193695
Short name T507
Test name
Test status
Simulation time 810590694 ps
CPU time 6.84 seconds
Started Sep 01 01:32:24 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958193695 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2958193695
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.1220025364
Short name T380
Test name
Test status
Simulation time 687296468 ps
CPU time 5.1 seconds
Started Sep 01 01:32:24 PM UTC 24
Finished Sep 01 01:32:30 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220025364 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1220025364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.2103795319
Short name T508
Test name
Test status
Simulation time 438506737 ps
CPU time 7.13 seconds
Started Sep 01 01:32:24 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103795319 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2103795319
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.3418597783
Short name T504
Test name
Test status
Simulation time 53032716 ps
CPU time 2.02 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:29 PM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418597783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3418597783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.1029988290
Short name T503
Test name
Test status
Simulation time 3823885253 ps
CPU time 4.54 seconds
Started Sep 01 01:32:23 PM UTC 24
Finished Sep 01 01:32:29 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029988290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1029988290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.3374793558
Short name T451
Test name
Test status
Simulation time 437614204 ps
CPU time 4.82 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 224332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374793558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3374793558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.1692623622
Short name T186
Test name
Test status
Simulation time 299316844 ps
CPU time 4.24 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692623622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1692623622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.1927726221
Short name T513
Test name
Test status
Simulation time 57628111 ps
CPU time 1.15 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927726221 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1927726221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.2482295776
Short name T310
Test name
Test status
Simulation time 26186160 ps
CPU time 2.03 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482295776 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2482295776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.1840830108
Short name T34
Test name
Test status
Simulation time 69857609 ps
CPU time 2.75 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840830108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1840830108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.3175679418
Short name T511
Test name
Test status
Simulation time 126537503 ps
CPU time 3.29 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175679418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3175679418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.3426944821
Short name T337
Test name
Test status
Simulation time 156214127 ps
CPU time 3.76 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 232152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426944821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3426944821
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.104065617
Short name T306
Test name
Test status
Simulation time 4734271625 ps
CPU time 7.2 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:37 PM UTC 24
Peak memory 220516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104065617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.104065617
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.180993641
Short name T143
Test name
Test status
Simulation time 140573047 ps
CPU time 3.31 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180993641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.180993641
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_random.2034681851
Short name T517
Test name
Test status
Simulation time 356708842 ps
CPU time 5.53 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 226064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034681851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2034681851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.4236748364
Short name T509
Test name
Test status
Simulation time 170057934 ps
CPU time 4.84 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:32 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236748364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4236748364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.3561309441
Short name T512
Test name
Test status
Simulation time 119958469 ps
CPU time 3.74 seconds
Started Sep 01 01:32:28 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561309441 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3561309441
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.2108683413
Short name T324
Test name
Test status
Simulation time 360807395 ps
CPU time 2.75 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:30 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108683413 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2108683413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.2227460182
Short name T510
Test name
Test status
Simulation time 859968599 ps
CPU time 3.31 seconds
Started Sep 01 01:32:28 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227460182 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2227460182
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.4154139796
Short name T433
Test name
Test status
Simulation time 347762339 ps
CPU time 2.8 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:33 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154139796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4154139796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.2894302999
Short name T506
Test name
Test status
Simulation time 180690889 ps
CPU time 2.73 seconds
Started Sep 01 01:32:26 PM UTC 24
Finished Sep 01 01:32:30 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894302999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2894302999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.1194998473
Short name T514
Test name
Test status
Simulation time 152901609 ps
CPU time 4.41 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:34 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194998473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1194998473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.3726335645
Short name T526
Test name
Test status
Simulation time 492234333 ps
CPU time 7.63 seconds
Started Sep 01 01:32:29 PM UTC 24
Finished Sep 01 01:32:38 PM UTC 24
Peak memory 219500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726335645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3726335645
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.1528482639
Short name T521
Test name
Test status
Simulation time 15671239 ps
CPU time 0.78 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528482639 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1528482639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.2038624658
Short name T287
Test name
Test status
Simulation time 229391151 ps
CPU time 3.94 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:37 PM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038624658 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2038624658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1754232199
Short name T229
Test name
Test status
Simulation time 80416837 ps
CPU time 2.23 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754232199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1754232199
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.2279001052
Short name T369
Test name
Test status
Simulation time 47668018 ps
CPU time 2.65 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279001052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2279001052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.2562096481
Short name T66
Test name
Test status
Simulation time 83683772 ps
CPU time 3.72 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562096481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2562096481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.4280837829
Short name T263
Test name
Test status
Simulation time 506722876 ps
CPU time 3.65 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 226020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280837829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4280837829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.2356631772
Short name T372
Test name
Test status
Simulation time 286584575 ps
CPU time 3.62 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356631772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2356631772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_random.4244537418
Short name T368
Test name
Test status
Simulation time 455170104 ps
CPU time 3.75 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 230328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244537418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4244537418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3731685812
Short name T519
Test name
Test status
Simulation time 269596207 ps
CPU time 2.97 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731685812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3731685812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2677451471
Short name T576
Test name
Test status
Simulation time 4413860704 ps
CPU time 33.36 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:33:06 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677451471 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2677451471
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.846578352
Short name T518
Test name
Test status
Simulation time 38787665 ps
CPU time 2.87 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846578352 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.846578352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.1281477529
Short name T515
Test name
Test status
Simulation time 37033301 ps
CPU time 2.02 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:32:34 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281477529 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1281477529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.3151022787
Short name T523
Test name
Test status
Simulation time 355353331 ps
CPU time 2.61 seconds
Started Sep 01 01:32:33 PM UTC 24
Finished Sep 01 01:32:37 PM UTC 24
Peak memory 218084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151022787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3151022787
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.78224273
Short name T516
Test name
Test status
Simulation time 141497793 ps
CPU time 2.55 seconds
Started Sep 01 01:32:31 PM UTC 24
Finished Sep 01 01:32:35 PM UTC 24
Peak memory 217860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78224273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.78224273
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.4224711813
Short name T520
Test name
Test status
Simulation time 264023228 ps
CPU time 3.17 seconds
Started Sep 01 01:32:32 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224711813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4224711813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.1132722293
Short name T525
Test name
Test status
Simulation time 108432909 ps
CPU time 2.56 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:38 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132722293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1132722293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.3911762003
Short name T69
Test name
Test status
Simulation time 12069930 ps
CPU time 0.73 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:49 PM UTC 24
Peak memory 213536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911762003 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3911762003
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.3014420734
Short name T103
Test name
Test status
Simulation time 140800702 ps
CPU time 3.07 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014420734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3014420734
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.1223232077
Short name T27
Test name
Test status
Simulation time 38657196 ps
CPU time 3.34 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223232077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1223232077
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.843449047
Short name T80
Test name
Test status
Simulation time 60081963 ps
CPU time 3.35 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 230868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843449047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.843449047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.1418746556
Short name T150
Test name
Test status
Simulation time 58393152 ps
CPU time 3.88 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418746556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1418746556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_random.3529325726
Short name T189
Test name
Test status
Simulation time 644650320 ps
CPU time 4.17 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529325726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3529325726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.820550956
Short name T160
Test name
Test status
Simulation time 38872230 ps
CPU time 1.7 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:49 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820550956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.820550956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.1446305570
Short name T203
Test name
Test status
Simulation time 70506065 ps
CPU time 2.17 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446305570 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1446305570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.3118010860
Short name T401
Test name
Test status
Simulation time 859868978 ps
CPU time 19.7 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:32:07 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118010860 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3118010860
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.1723956619
Short name T283
Test name
Test status
Simulation time 2634902623 ps
CPU time 13.05 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 218088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723956619 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1723956619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.2233273177
Short name T219
Test name
Test status
Simulation time 180517167 ps
CPU time 2.65 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233273177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2233273177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.375756619
Short name T463
Test name
Test status
Simulation time 3159774821 ps
CPU time 13.6 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375756619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.375756619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.2059066890
Short name T82
Test name
Test status
Simulation time 95661640 ps
CPU time 4.32 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059066890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2059066890
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.2573020673
Short name T40
Test name
Test status
Simulation time 72915540 ps
CPU time 1.88 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 216188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573020673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2573020673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.250502543
Short name T528
Test name
Test status
Simulation time 12752268 ps
CPU time 0.93 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:38 PM UTC 24
Peak memory 213536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250502543 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.250502543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.2242099832
Short name T152
Test name
Test status
Simulation time 243095539 ps
CPU time 2.88 seconds
Started Sep 01 01:32:35 PM UTC 24
Finished Sep 01 01:32:39 PM UTC 24
Peak memory 224024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242099832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2242099832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.3430476874
Short name T60
Test name
Test status
Simulation time 893257673 ps
CPU time 25.71 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 226464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430476874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3430476874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.1589469484
Short name T336
Test name
Test status
Simulation time 111574835 ps
CPU time 2.4 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589469484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1589469484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.650379167
Short name T228
Test name
Test status
Simulation time 235566797 ps
CPU time 6.71 seconds
Started Sep 01 01:32:35 PM UTC 24
Finished Sep 01 01:32:42 PM UTC 24
Peak memory 232512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650379167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.650379167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_random.3883373791
Short name T533
Test name
Test status
Simulation time 333607949 ps
CPU time 4.34 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883373791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3883373791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.2245185928
Short name T314
Test name
Test status
Simulation time 129056964 ps
CPU time 3.99 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:39 PM UTC 24
Peak memory 218252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245185928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2245185928
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.936088565
Short name T434
Test name
Test status
Simulation time 159634557 ps
CPU time 5.28 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936088565 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.936088565
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.853688125
Short name T527
Test name
Test status
Simulation time 535635157 ps
CPU time 2.89 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:38 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853688125 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.853688125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.239199198
Short name T532
Test name
Test status
Simulation time 220119878 ps
CPU time 4.4 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239199198 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.239199198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.2675083270
Short name T541
Test name
Test status
Simulation time 664703820 ps
CPU time 5.08 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:42 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675083270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2675083270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.1718123885
Short name T522
Test name
Test status
Simulation time 131055199 ps
CPU time 4.03 seconds
Started Sep 01 01:32:34 PM UTC 24
Finished Sep 01 01:32:39 PM UTC 24
Peak memory 217816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718123885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1718123885
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.735065033
Short name T232
Test name
Test status
Simulation time 5636196645 ps
CPU time 55.74 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:33:34 PM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735065033 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.735065033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.255456032
Short name T409
Test name
Test status
Simulation time 257377744 ps
CPU time 14.05 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 232700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=255456032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr
_stress_all_with_rand_reset.255456032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.3368421577
Short name T537
Test name
Test status
Simulation time 77861940 ps
CPU time 3.61 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 215720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368421577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3368421577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.1153348305
Short name T530
Test name
Test status
Simulation time 54185925 ps
CPU time 2.53 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 218092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153348305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1153348305
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.1381800137
Short name T539
Test name
Test status
Simulation time 15825717 ps
CPU time 1.08 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381800137 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1381800137
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.3827802082
Short name T334
Test name
Test status
Simulation time 202973086 ps
CPU time 3.2 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827802082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3827802082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.345511244
Short name T428
Test name
Test status
Simulation time 147360741 ps
CPU time 5.21 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 230280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345511244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.345511244
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.3847508476
Short name T59
Test name
Test status
Simulation time 1022917867 ps
CPU time 6.47 seconds
Started Sep 01 01:32:37 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847508476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3847508476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.1009769899
Short name T295
Test name
Test status
Simulation time 52011867 ps
CPU time 4.1 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009769899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1009769899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.3802837573
Short name T234
Test name
Test status
Simulation time 1027654570 ps
CPU time 4.66 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:42 PM UTC 24
Peak memory 230196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802837573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3802837573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_random.2747298274
Short name T589
Test name
Test status
Simulation time 736394701 ps
CPU time 17.95 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747298274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2747298274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.1191618842
Short name T540
Test name
Test status
Simulation time 62778233 ps
CPU time 3.87 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 218316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191618842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1191618842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.2820793796
Short name T529
Test name
Test status
Simulation time 127740723 ps
CPU time 2.31 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820793796 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2820793796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.2672382665
Short name T538
Test name
Test status
Simulation time 101503249 ps
CPU time 3.32 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:41 PM UTC 24
Peak memory 215952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672382665 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2672382665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.1320937192
Short name T535
Test name
Test status
Simulation time 53887156 ps
CPU time 2.72 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:40 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320937192 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1320937192
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.3054734185
Short name T551
Test name
Test status
Simulation time 118387934 ps
CPU time 4.96 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:45 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054734185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3054734185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.2681936701
Short name T544
Test name
Test status
Simulation time 597445575 ps
CPU time 5.62 seconds
Started Sep 01 01:32:36 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681936701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2681936701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all_with_rand_reset.3655763908
Short name T562
Test name
Test status
Simulation time 117939171 ps
CPU time 7.11 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:47 PM UTC 24
Peak memory 230456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3655763908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymg
r_stress_all_with_rand_reset.3655763908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.1283009001
Short name T543
Test name
Test status
Simulation time 81465753 ps
CPU time 4.88 seconds
Started Sep 01 01:32:37 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 224328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283009001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1283009001
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.1550244052
Short name T548
Test name
Test status
Simulation time 21339870 ps
CPU time 1.33 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550244052 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1550244052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.2358307883
Short name T442
Test name
Test status
Simulation time 189571116 ps
CPU time 4.08 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358307883 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2358307883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.1302802282
Short name T571
Test name
Test status
Simulation time 909305832 ps
CPU time 6.49 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:49 PM UTC 24
Peak memory 232592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302802282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1302802282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.2156793580
Short name T296
Test name
Test status
Simulation time 717282611 ps
CPU time 5.11 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:48 PM UTC 24
Peak memory 224304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156793580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2156793580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.3065437456
Short name T226
Test name
Test status
Simulation time 465586924 ps
CPU time 3.8 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065437456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3065437456
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_random.2433633489
Short name T550
Test name
Test status
Simulation time 306862852 ps
CPU time 4.11 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433633489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2433633489
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.736886723
Short name T430
Test name
Test status
Simulation time 248300277 ps
CPU time 7.29 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:47 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736886723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.736886723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.3089782927
Short name T542
Test name
Test status
Simulation time 75596611 ps
CPU time 2.32 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089782927 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3089782927
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.506633952
Short name T545
Test name
Test status
Simulation time 39924552 ps
CPU time 3.07 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 215784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506633952 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.506633952
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3895696333
Short name T622
Test name
Test status
Simulation time 7834587658 ps
CPU time 33.68 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:33:14 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895696333 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3895696333
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.3025385040
Short name T554
Test name
Test status
Simulation time 131068190 ps
CPU time 2.68 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:45 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025385040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3025385040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.2844823116
Short name T546
Test name
Test status
Simulation time 58616294 ps
CPU time 3.22 seconds
Started Sep 01 01:32:39 PM UTC 24
Finished Sep 01 01:32:43 PM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844823116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2844823116
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.501359243
Short name T547
Test name
Test status
Simulation time 20729171 ps
CPU time 1.42 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 213660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501359243 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.501359243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.3406625354
Short name T572
Test name
Test status
Simulation time 942245295 ps
CPU time 7.38 seconds
Started Sep 01 01:32:41 PM UTC 24
Finished Sep 01 01:32:50 PM UTC 24
Peak memory 217908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406625354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3406625354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.3118438980
Short name T549
Test name
Test status
Simulation time 24331227 ps
CPU time 1.61 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:44 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118438980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3118438980
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.2833246782
Short name T557
Test name
Test status
Simulation time 203082826 ps
CPU time 0.95 seconds
Started Sep 01 01:32:44 PM UTC 24
Finished Sep 01 01:32:46 PM UTC 24
Peak memory 213560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833246782 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2833246782
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.1413454806
Short name T437
Test name
Test status
Simulation time 642386517 ps
CPU time 12.01 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413454806 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1413454806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.3418482712
Short name T564
Test name
Test status
Simulation time 228906510 ps
CPU time 3.13 seconds
Started Sep 01 01:32:43 PM UTC 24
Finished Sep 01 01:32:48 PM UTC 24
Peak memory 231476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418482712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3418482712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1904300306
Short name T563
Test name
Test status
Simulation time 174101698 ps
CPU time 4.28 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:48 PM UTC 24
Peak memory 230260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904300306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1904300306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.733157410
Short name T50
Test name
Test status
Simulation time 109741866 ps
CPU time 5.32 seconds
Started Sep 01 01:32:43 PM UTC 24
Finished Sep 01 01:32:50 PM UTC 24
Peak memory 231596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733157410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.733157410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.1207695179
Short name T300
Test name
Test status
Simulation time 154404711 ps
CPU time 4.36 seconds
Started Sep 01 01:32:43 PM UTC 24
Finished Sep 01 01:32:49 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207695179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1207695179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.4100303122
Short name T233
Test name
Test status
Simulation time 144000392 ps
CPU time 2.36 seconds
Started Sep 01 01:32:43 PM UTC 24
Finished Sep 01 01:32:47 PM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100303122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4100303122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_random.3887542990
Short name T575
Test name
Test status
Simulation time 1021732379 ps
CPU time 7.84 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:51 PM UTC 24
Peak memory 217468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887542990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3887542990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.2145479908
Short name T555
Test name
Test status
Simulation time 148900805 ps
CPU time 2.74 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:46 PM UTC 24
Peak memory 216148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145479908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2145479908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.462066722
Short name T553
Test name
Test status
Simulation time 44376735 ps
CPU time 2.14 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:45 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462066722 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.462066722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.2383545977
Short name T559
Test name
Test status
Simulation time 62800719 ps
CPU time 3.1 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:46 PM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383545977 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2383545977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.3336922632
Short name T556
Test name
Test status
Simulation time 42451533 ps
CPU time 2.59 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:46 PM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336922632 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3336922632
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.114449377
Short name T373
Test name
Test status
Simulation time 9550322794 ps
CPU time 42.11 seconds
Started Sep 01 01:32:44 PM UTC 24
Finished Sep 01 01:33:27 PM UTC 24
Peak memory 224232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114449377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.114449377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.1820704793
Short name T566
Test name
Test status
Simulation time 190475313 ps
CPU time 5.29 seconds
Started Sep 01 01:32:42 PM UTC 24
Finished Sep 01 01:32:48 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820704793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1820704793
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.388965483
Short name T581
Test name
Test status
Simulation time 1130457413 ps
CPU time 8.88 seconds
Started Sep 01 01:32:43 PM UTC 24
Finished Sep 01 01:32:53 PM UTC 24
Peak memory 219932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388965483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.388965483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.4232041696
Short name T568
Test name
Test status
Simulation time 19133825 ps
CPU time 1.08 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:49 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232041696 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4232041696
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.1610658173
Short name T325
Test name
Test status
Simulation time 764998806 ps
CPU time 10.02 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 226340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610658173 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1610658173
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.3352645936
Short name T43
Test name
Test status
Simulation time 721982968 ps
CPU time 9.38 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352645936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3352645936
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.3920047079
Short name T153
Test name
Test status
Simulation time 1148960046 ps
CPU time 5.48 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920047079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3920047079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.2394514576
Short name T62
Test name
Test status
Simulation time 309112570 ps
CPU time 3.45 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:50 PM UTC 24
Peak memory 230972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394514576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2394514576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.3731789972
Short name T570
Test name
Test status
Simulation time 138717404 ps
CPU time 2.59 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:49 PM UTC 24
Peak memory 218160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731789972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3731789972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.1860474698
Short name T144
Test name
Test status
Simulation time 118331666 ps
CPU time 4.11 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:50 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860474698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1860474698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_random.2130063678
Short name T569
Test name
Test status
Simulation time 103147450 ps
CPU time 2.81 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:49 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130063678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2130063678
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.4174159998
Short name T612
Test name
Test status
Simulation time 610971717 ps
CPU time 16.41 seconds
Started Sep 01 01:32:44 PM UTC 24
Finished Sep 01 01:33:01 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174159998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4174159998
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1492319888
Short name T580
Test name
Test status
Simulation time 525621641 ps
CPU time 6.52 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:53 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492319888 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1492319888
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.2397654884
Short name T565
Test name
Test status
Simulation time 80339488 ps
CPU time 2.12 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:48 PM UTC 24
Peak memory 216024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397654884 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2397654884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.632285209
Short name T567
Test name
Test status
Simulation time 48266789 ps
CPU time 2.33 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:48 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632285209 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.632285209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.3035219511
Short name T328
Test name
Test status
Simulation time 611552338 ps
CPU time 3.01 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:50 PM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035219511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3035219511
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.623539657
Short name T574
Test name
Test status
Simulation time 501892174 ps
CPU time 4.75 seconds
Started Sep 01 01:32:44 PM UTC 24
Finished Sep 01 01:32:50 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623539657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.623539657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.3084676908
Short name T320
Test name
Test status
Simulation time 172440177 ps
CPU time 4.92 seconds
Started Sep 01 01:32:45 PM UTC 24
Finished Sep 01 01:32:51 PM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084676908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3084676908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.2016464505
Short name T573
Test name
Test status
Simulation time 59832575 ps
CPU time 1.73 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:49 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016464505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2016464505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1651910429
Short name T578
Test name
Test status
Simulation time 34278125 ps
CPU time 0.86 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651910429 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1651910429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.1314368161
Short name T441
Test name
Test status
Simulation time 120203369 ps
CPU time 4.44 seconds
Started Sep 01 01:32:48 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314368161 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1314368161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.2226184802
Short name T42
Test name
Test status
Simulation time 41501670 ps
CPU time 2.66 seconds
Started Sep 01 01:32:49 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226184802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2226184802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.2574852961
Short name T393
Test name
Test status
Simulation time 61427851 ps
CPU time 3.59 seconds
Started Sep 01 01:32:48 PM UTC 24
Finished Sep 01 01:32:53 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574852961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2574852961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.527242219
Short name T264
Test name
Test status
Simulation time 170554029 ps
CPU time 4.54 seconds
Started Sep 01 01:32:48 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 230784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527242219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.527242219
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.4062159977
Short name T584
Test name
Test status
Simulation time 149898507 ps
CPU time 4.72 seconds
Started Sep 01 01:32:48 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062159977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4062159977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_random.766938911
Short name T591
Test name
Test status
Simulation time 334162665 ps
CPU time 8.04 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766938911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.766938911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.3576132576
Short name T558
Test name
Test status
Simulation time 205112118 ps
CPU time 2.93 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:51 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576132576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3576132576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.137087770
Short name T579
Test name
Test status
Simulation time 292962664 ps
CPU time 4.12 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137087770 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.137087770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.1311624166
Short name T577
Test name
Test status
Simulation time 59912526 ps
CPU time 3.92 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311624166 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1311624166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.722844361
Short name T429
Test name
Test status
Simulation time 859628990 ps
CPU time 3.63 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722844361 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.722844361
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.2672623986
Short name T582
Test name
Test status
Simulation time 38183791 ps
CPU time 2.55 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:53 PM UTC 24
Peak memory 224200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672623986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2672623986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3545178155
Short name T531
Test name
Test status
Simulation time 944899878 ps
CPU time 3.36 seconds
Started Sep 01 01:32:47 PM UTC 24
Finished Sep 01 01:32:51 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545178155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3545178155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.2568864690
Short name T329
Test name
Test status
Simulation time 315194093 ps
CPU time 13.15 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:33:04 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568864690 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2568864690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.4058889117
Short name T619
Test name
Test status
Simulation time 5947587253 ps
CPU time 15.23 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:33:06 PM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4058889117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymg
r_stress_all_with_rand_reset.4058889117
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.3461064156
Short name T332
Test name
Test status
Simulation time 172740902 ps
CPU time 4.17 seconds
Started Sep 01 01:32:48 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 218308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461064156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3461064156
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.1687365627
Short name T586
Test name
Test status
Simulation time 10388092 ps
CPU time 1.04 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687365627 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1687365627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.2562759136
Short name T588
Test name
Test status
Simulation time 95130112 ps
CPU time 2.8 seconds
Started Sep 01 01:32:52 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562759136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2562759136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.9005052
Short name T617
Test name
Test status
Simulation time 1440928196 ps
CPU time 11.44 seconds
Started Sep 01 01:32:51 PM UTC 24
Finished Sep 01 01:33:04 PM UTC 24
Peak memory 230296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9005052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.9005052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.185237961
Short name T302
Test name
Test status
Simulation time 303665712 ps
CPU time 2.95 seconds
Started Sep 01 01:32:52 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185237961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.185237961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.238592453
Short name T339
Test name
Test status
Simulation time 193086670 ps
CPU time 3.08 seconds
Started Sep 01 01:32:51 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 232476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238592453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.238592453
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_random.2578480046
Short name T592
Test name
Test status
Simulation time 181115399 ps
CPU time 3.95 seconds
Started Sep 01 01:32:51 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578480046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2578480046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.2671255543
Short name T598
Test name
Test status
Simulation time 192233371 ps
CPU time 5.89 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:57 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671255543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2671255543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.2741938483
Short name T583
Test name
Test status
Simulation time 240314718 ps
CPU time 2.44 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:54 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741938483 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2741938483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.893280143
Short name T596
Test name
Test status
Simulation time 2798361157 ps
CPU time 5.71 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:57 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893280143 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.893280143
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.368967129
Short name T624
Test name
Test status
Simulation time 1693961053 ps
CPU time 29.46 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:33:21 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368967129 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.368967129
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.1233823186
Short name T587
Test name
Test status
Simulation time 35033263 ps
CPU time 1.45 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233823186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1233823186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.2832928282
Short name T585
Test name
Test status
Simulation time 613547928 ps
CPU time 3.54 seconds
Started Sep 01 01:32:50 PM UTC 24
Finished Sep 01 01:32:55 PM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832928282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2832928282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.320378458
Short name T362
Test name
Test status
Simulation time 439830116 ps
CPU time 11.99 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:33:06 PM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320378458 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.320378458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all_with_rand_reset.457216424
Short name T193
Test name
Test status
Simulation time 549565759 ps
CPU time 17.8 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:33:12 PM UTC 24
Peak memory 232588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=457216424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr
_stress_all_with_rand_reset.457216424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.2104251299
Short name T349
Test name
Test status
Simulation time 673597300 ps
CPU time 19.22 seconds
Started Sep 01 01:32:51 PM UTC 24
Finished Sep 01 01:33:12 PM UTC 24
Peak memory 217476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104251299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2104251299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.2451201407
Short name T593
Test name
Test status
Simulation time 48076460 ps
CPU time 2.52 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451201407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2451201407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.2226036382
Short name T597
Test name
Test status
Simulation time 22587069 ps
CPU time 1.19 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:32:57 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226036382 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2226036382
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.472829670
Short name T600
Test name
Test status
Simulation time 302926852 ps
CPU time 2.2 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:32:58 PM UTC 24
Peak memory 230248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472829670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.472829670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.376807309
Short name T413
Test name
Test status
Simulation time 3402730115 ps
CPU time 9.13 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:33:04 PM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376807309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.376807309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.720719221
Short name T601
Test name
Test status
Simulation time 29644682 ps
CPU time 2.39 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:32:58 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720719221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.720719221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.3605112021
Short name T604
Test name
Test status
Simulation time 165168541 ps
CPU time 3.03 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:32:59 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605112021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3605112021
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.86561467
Short name T605
Test name
Test status
Simulation time 717829579 ps
CPU time 5.08 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:59 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86561467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.86561467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_random.5775290
Short name T607
Test name
Test status
Simulation time 137656804 ps
CPU time 5.24 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:33:00 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5775290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.5775290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.177993195
Short name T590
Test name
Test status
Simulation time 36462874 ps
CPU time 1.96 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:56 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177993195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.177993195
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2577127512
Short name T603
Test name
Test status
Simulation time 890012160 ps
CPU time 4.37 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:59 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577127512 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2577127512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.2528633054
Short name T595
Test name
Test status
Simulation time 134024925 ps
CPU time 2.35 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:57 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528633054 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2528633054
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.3995441773
Short name T623
Test name
Test status
Simulation time 1404662935 ps
CPU time 21.18 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:33:16 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995441773 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3995441773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.9675421
Short name T611
Test name
Test status
Simulation time 251110706 ps
CPU time 5.42 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:33:01 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9675421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.9675421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.964456705
Short name T599
Test name
Test status
Simulation time 68031040 ps
CPU time 3.49 seconds
Started Sep 01 01:32:53 PM UTC 24
Finished Sep 01 01:32:58 PM UTC 24
Peak memory 218136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964456705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.964456705
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.3958323375
Short name T677
Test name
Test status
Simulation time 4265593094 ps
CPU time 64.12 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 232656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958323375 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3958323375
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.2684225517
Short name T616
Test name
Test status
Simulation time 509306680 ps
CPU time 7.73 seconds
Started Sep 01 01:32:54 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684225517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2684225517
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.3344511943
Short name T618
Test name
Test status
Simulation time 1150427708 ps
CPU time 9.72 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:33:05 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344511943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3344511943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.3266697507
Short name T424
Test name
Test status
Simulation time 37340285 ps
CPU time 2.59 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:00 PM UTC 24
Peak memory 226012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266697507 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3266697507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1733507888
Short name T613
Test name
Test status
Simulation time 278897039 ps
CPU time 4.74 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:02 PM UTC 24
Peak memory 232556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733507888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1733507888
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.1460750905
Short name T412
Test name
Test status
Simulation time 74900815 ps
CPU time 1.76 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:32:59 PM UTC 24
Peak memory 216220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460750905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1460750905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.3864301152
Short name T63
Test name
Test status
Simulation time 34119822 ps
CPU time 2.47 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:00 PM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864301152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3864301152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.1011949417
Short name T614
Test name
Test status
Simulation time 176026892 ps
CPU time 5.33 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 224304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011949417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1011949417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.2523323842
Short name T245
Test name
Test status
Simulation time 344204773 ps
CPU time 5.38 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523323842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2523323842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_random.85536978
Short name T610
Test name
Test status
Simulation time 368436899 ps
CPU time 3.63 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:01 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85536978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.85536978
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.1736803890
Short name T615
Test name
Test status
Simulation time 899953125 ps
CPU time 7.05 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:33:03 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736803890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1736803890
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.2723435444
Short name T594
Test name
Test status
Simulation time 331730432 ps
CPU time 9.94 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:07 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723435444 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2723435444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.721318564
Short name T609
Test name
Test status
Simulation time 701088151 ps
CPU time 3.16 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:00 PM UTC 24
Peak memory 217832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721318564 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.721318564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.4196250357
Short name T608
Test name
Test status
Simulation time 41473753 ps
CPU time 2.81 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:00 PM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196250357 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4196250357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.3842742534
Short name T606
Test name
Test status
Simulation time 110216857 ps
CPU time 1.96 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:32:59 PM UTC 24
Peak memory 227668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842742534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3842742534
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.4072261795
Short name T602
Test name
Test status
Simulation time 407145951 ps
CPU time 2.55 seconds
Started Sep 01 01:32:55 PM UTC 24
Finished Sep 01 01:32:58 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072261795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4072261795
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.168636426
Short name T826
Test name
Test status
Simulation time 4407136607 ps
CPU time 66.82 seconds
Started Sep 01 01:32:58 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168636426 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.168636426
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.4131636739
Short name T621
Test name
Test status
Simulation time 1039618039 ps
CPU time 11.22 seconds
Started Sep 01 01:32:56 PM UTC 24
Finished Sep 01 01:33:09 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131636739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.4131636739
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.3577246376
Short name T630
Test name
Test status
Simulation time 65686420 ps
CPU time 0.8 seconds
Started Sep 01 01:33:01 PM UTC 24
Finished Sep 01 01:33:53 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577246376 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3577246376
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.2589603188
Short name T24
Test name
Test status
Simulation time 33979672 ps
CPU time 2.23 seconds
Started Sep 01 01:32:59 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589603188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2589603188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.3640795807
Short name T355
Test name
Test status
Simulation time 241180097 ps
CPU time 3.42 seconds
Started Sep 01 01:32:59 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640795807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3640795807
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.1426138977
Short name T651
Test name
Test status
Simulation time 87359008 ps
CPU time 4.17 seconds
Started Sep 01 01:32:59 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426138977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1426138977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.3220823045
Short name T633
Test name
Test status
Simulation time 154359178 ps
CPU time 1.84 seconds
Started Sep 01 01:32:59 PM UTC 24
Finished Sep 01 01:33:53 PM UTC 24
Peak memory 223656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220823045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3220823045
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.1963314749
Short name T626
Test name
Test status
Simulation time 229983268 ps
CPU time 5.1 seconds
Started Sep 01 01:32:58 PM UTC 24
Finished Sep 01 01:33:34 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963314749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1963314749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3477834257
Short name T635
Test name
Test status
Simulation time 39372788 ps
CPU time 2.43 seconds
Started Sep 01 01:33:00 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477834257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3477834257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.3089809601
Short name T155
Test name
Test status
Simulation time 370391195 ps
CPU time 13.15 seconds
Started Sep 01 01:33:01 PM UTC 24
Finished Sep 01 01:33:45 PM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089809601 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3089809601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2094114712
Short name T665
Test name
Test status
Simulation time 582362971 ps
CPU time 5.52 seconds
Started Sep 01 01:32:59 PM UTC 24
Finished Sep 01 01:33:57 PM UTC 24
Peak memory 230272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094114712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2094114712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.1053336033
Short name T639
Test name
Test status
Simulation time 77610435 ps
CPU time 3.23 seconds
Started Sep 01 01:33:01 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053336033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1053336033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.574619182
Short name T204
Test name
Test status
Simulation time 95031207 ps
CPU time 0.94 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 213596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574619182 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.574619182
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.4218737669
Short name T28
Test name
Test status
Simulation time 196263576 ps
CPU time 2.93 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218737669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4218737669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.1674823770
Short name T134
Test name
Test status
Simulation time 190380677 ps
CPU time 4.03 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674823770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1674823770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.1466215423
Short name T54
Test name
Test status
Simulation time 126584190 ps
CPU time 3.42 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 232456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466215423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1466215423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_random.2618918421
Short name T83
Test name
Test status
Simulation time 80156474 ps
CPU time 4.21 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618918421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2618918421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.652823977
Short name T48
Test name
Test status
Simulation time 1965075630 ps
CPU time 34.54 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:32:23 PM UTC 24
Peak memory 260252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652823977 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.652823977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.832294986
Short name T207
Test name
Test status
Simulation time 36384787 ps
CPU time 2.36 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 218260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832294986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.832294986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.3282457999
Short name T105
Test name
Test status
Simulation time 331678491 ps
CPU time 2.9 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282457999 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3282457999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.211795378
Short name T107
Test name
Test status
Simulation time 84681299 ps
CPU time 2.94 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211795378 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.211795378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.1152244900
Short name T205
Test name
Test status
Simulation time 85809886 ps
CPU time 1.71 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152244900 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1152244900
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.3825548374
Short name T192
Test name
Test status
Simulation time 127386432 ps
CPU time 3.61 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825548374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3825548374
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.2435416481
Short name T208
Test name
Test status
Simulation time 240360089 ps
CPU time 2.29 seconds
Started Sep 01 01:31:46 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435416481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2435416481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.2256766502
Short name T216
Test name
Test status
Simulation time 341570506 ps
CPU time 3.61 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256766502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2256766502
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.470456161
Short name T37
Test name
Test status
Simulation time 242020195 ps
CPU time 2.31 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470456161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.470456161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.1183458948
Short name T634
Test name
Test status
Simulation time 10385695 ps
CPU time 0.88 seconds
Started Sep 01 01:33:05 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 213064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183458948 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1183458948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.1664081629
Short name T660
Test name
Test status
Simulation time 368826920 ps
CPU time 4.62 seconds
Started Sep 01 01:33:03 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 224668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664081629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1664081629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.553010331
Short name T57
Test name
Test status
Simulation time 11286026303 ps
CPU time 35.45 seconds
Started Sep 01 01:33:03 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 230896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553010331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.553010331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.1186939956
Short name T377
Test name
Test status
Simulation time 239773680 ps
CPU time 2.73 seconds
Started Sep 01 01:33:03 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 223976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186939956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1186939956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_random.2980521278
Short name T666
Test name
Test status
Simulation time 136164666 ps
CPU time 4.4 seconds
Started Sep 01 01:33:02 PM UTC 24
Finished Sep 01 01:33:58 PM UTC 24
Peak memory 228172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980521278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2980521278
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.950295370
Short name T627
Test name
Test status
Simulation time 67791207 ps
CPU time 2.48 seconds
Started Sep 01 01:33:01 PM UTC 24
Finished Sep 01 01:33:34 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950295370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.950295370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.2851962979
Short name T661
Test name
Test status
Simulation time 80307346 ps
CPU time 3.22 seconds
Started Sep 01 01:33:02 PM UTC 24
Finished Sep 01 01:33:57 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851962979 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2851962979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.699904646
Short name T638
Test name
Test status
Simulation time 404654639 ps
CPU time 2.52 seconds
Started Sep 01 01:33:01 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699904646 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.699904646
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.2254462675
Short name T662
Test name
Test status
Simulation time 368666272 ps
CPU time 6.53 seconds
Started Sep 01 01:33:02 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254462675 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2254462675
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.4026673840
Short name T643
Test name
Test status
Simulation time 134672712 ps
CPU time 3.51 seconds
Started Sep 01 01:33:03 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 228580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026673840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4026673840
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.3015648717
Short name T670
Test name
Test status
Simulation time 191829926 ps
CPU time 5.29 seconds
Started Sep 01 01:33:05 PM UTC 24
Finished Sep 01 01:33:58 PM UTC 24
Peak memory 232044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015648717 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3015648717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3434245961
Short name T620
Test name
Test status
Simulation time 114606486 ps
CPU time 3.91 seconds
Started Sep 01 01:33:03 PM UTC 24
Finished Sep 01 01:33:08 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434245961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3434245961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.770222103
Short name T637
Test name
Test status
Simulation time 50942481 ps
CPU time 0.85 seconds
Started Sep 01 01:33:16 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770222103 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.770222103
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.487808514
Short name T425
Test name
Test status
Simulation time 131102991 ps
CPU time 2.62 seconds
Started Sep 01 01:33:07 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487808514 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.487808514
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.4057550019
Short name T631
Test name
Test status
Simulation time 101359050 ps
CPU time 1.69 seconds
Started Sep 01 01:33:07 PM UTC 24
Finished Sep 01 01:33:53 PM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057550019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4057550019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.3680992248
Short name T51
Test name
Test status
Simulation time 1000348180 ps
CPU time 6.45 seconds
Started Sep 01 01:33:08 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680992248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3680992248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.3440354287
Short name T659
Test name
Test status
Simulation time 449321160 ps
CPU time 4.86 seconds
Started Sep 01 01:33:09 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440354287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3440354287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.2813127270
Short name T250
Test name
Test status
Simulation time 189800126 ps
CPU time 3.13 seconds
Started Sep 01 01:33:07 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813127270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2813127270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_random.1669469004
Short name T681
Test name
Test status
Simulation time 742352412 ps
CPU time 4.48 seconds
Started Sep 01 01:33:06 PM UTC 24
Finished Sep 01 01:34:02 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669469004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1669469004
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.290821889
Short name T658
Test name
Test status
Simulation time 231782269 ps
CPU time 3.32 seconds
Started Sep 01 01:33:05 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290821889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.290821889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.560112626
Short name T647
Test name
Test status
Simulation time 64781899 ps
CPU time 2.47 seconds
Started Sep 01 01:33:05 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560112626 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.560112626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.3709901947
Short name T648
Test name
Test status
Simulation time 116758231 ps
CPU time 2.52 seconds
Started Sep 01 01:33:05 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709901947 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3709901947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.4268536655
Short name T676
Test name
Test status
Simulation time 92676578 ps
CPU time 3.07 seconds
Started Sep 01 01:33:06 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268536655 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4268536655
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.3817157682
Short name T405
Test name
Test status
Simulation time 450955559 ps
CPU time 2.7 seconds
Started Sep 01 01:33:09 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 218028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817157682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3817157682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.1250813860
Short name T642
Test name
Test status
Simulation time 384314043 ps
CPU time 2.3 seconds
Started Sep 01 01:33:05 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 217904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250813860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1250813860
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.1966568331
Short name T201
Test name
Test status
Simulation time 865724463 ps
CPU time 20.54 seconds
Started Sep 01 01:33:12 PM UTC 24
Finished Sep 01 01:34:12 PM UTC 24
Peak memory 230172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966568331 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1966568331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.180094335
Short name T653
Test name
Test status
Simulation time 210632447 ps
CPU time 4.54 seconds
Started Sep 01 01:33:07 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180094335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.180094335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.845617263
Short name T181
Test name
Test status
Simulation time 102057018 ps
CPU time 2.43 seconds
Started Sep 01 01:33:11 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 220056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845617263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.845617263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.2127463458
Short name T632
Test name
Test status
Simulation time 30324058 ps
CPU time 1.04 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:33:53 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127463458 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2127463458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.3108403279
Short name T449
Test name
Test status
Simulation time 53403485 ps
CPU time 4.02 seconds
Started Sep 01 01:33:34 PM UTC 24
Finished Sep 01 01:33:57 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108403279 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3108403279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.1020107579
Short name T239
Test name
Test status
Simulation time 99996742 ps
CPU time 3.04 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 232532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020107579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1020107579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.2308689123
Short name T664
Test name
Test status
Simulation time 88270781 ps
CPU time 3.53 seconds
Started Sep 01 01:33:35 PM UTC 24
Finished Sep 01 01:33:57 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308689123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2308689123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1380327251
Short name T650
Test name
Test status
Simulation time 59590166 ps
CPU time 3.66 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380327251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1380327251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.2851081395
Short name T663
Test name
Test status
Simulation time 126846338 ps
CPU time 4.81 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:33:57 PM UTC 24
Peak memory 232076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851081395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2851081395
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.426417891
Short name T654
Test name
Test status
Simulation time 60018872 ps
CPU time 2.43 seconds
Started Sep 01 01:33:35 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 228164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426417891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.426417891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_random.1580601747
Short name T656
Test name
Test status
Simulation time 694039367 ps
CPU time 2.83 seconds
Started Sep 01 01:33:32 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580601747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1580601747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.3562199194
Short name T641
Test name
Test status
Simulation time 118542921 ps
CPU time 3.11 seconds
Started Sep 01 01:33:20 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562199194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3562199194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.828012755
Short name T644
Test name
Test status
Simulation time 120804948 ps
CPU time 3.4 seconds
Started Sep 01 01:33:28 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828012755 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.828012755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.27108690
Short name T649
Test name
Test status
Simulation time 57794154 ps
CPU time 2.64 seconds
Started Sep 01 01:33:22 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27108690 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.27108690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.1896914138
Short name T652
Test name
Test status
Simulation time 35131823 ps
CPU time 2.65 seconds
Started Sep 01 01:33:29 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896914138 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1896914138
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.2702090419
Short name T636
Test name
Test status
Simulation time 747192219 ps
CPU time 2.38 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:33:54 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702090419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2702090419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.4060101967
Short name T678
Test name
Test status
Simulation time 994846836 ps
CPU time 3.23 seconds
Started Sep 01 01:33:17 PM UTC 24
Finished Sep 01 01:34:01 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060101967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4060101967
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.2080002310
Short name T404
Test name
Test status
Simulation time 1151250361 ps
CPU time 27.56 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:34:20 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080002310 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2080002310
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.469002612
Short name T640
Test name
Test status
Simulation time 625385252 ps
CPU time 3.48 seconds
Started Sep 01 01:33:37 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469002612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.469002612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.601540757
Short name T200
Test name
Test status
Simulation time 386629960 ps
CPU time 5.48 seconds
Started Sep 01 01:33:40 PM UTC 24
Finished Sep 01 01:33:58 PM UTC 24
Peak memory 220052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601540757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.601540757
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.3135506954
Short name T667
Test name
Test status
Simulation time 17922157 ps
CPU time 0.7 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:58 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135506954 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3135506954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.4261728125
Short name T456
Test name
Test status
Simulation time 159037649 ps
CPU time 2.73 seconds
Started Sep 01 01:33:46 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261728125 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4261728125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.1137342631
Short name T669
Test name
Test status
Simulation time 117477373 ps
CPU time 2.3 seconds
Started Sep 01 01:33:54 PM UTC 24
Finished Sep 01 01:33:58 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137342631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1137342631
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.1019331664
Short name T671
Test name
Test status
Simulation time 269110167 ps
CPU time 1.78 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 223524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019331664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1019331664
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.745378935
Short name T675
Test name
Test status
Simulation time 96857994 ps
CPU time 4.05 seconds
Started Sep 01 01:33:54 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745378935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.745378935
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_random.3672291221
Short name T657
Test name
Test status
Simulation time 84953774 ps
CPU time 2.59 seconds
Started Sep 01 01:33:45 PM UTC 24
Finished Sep 01 01:33:56 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672291221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3672291221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.3207436078
Short name T810
Test name
Test status
Simulation time 1683593591 ps
CPU time 39.58 seconds
Started Sep 01 01:33:42 PM UTC 24
Finished Sep 01 01:34:33 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207436078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3207436078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.124235543
Short name T699
Test name
Test status
Simulation time 6116293382 ps
CPU time 13.45 seconds
Started Sep 01 01:33:44 PM UTC 24
Finished Sep 01 01:34:06 PM UTC 24
Peak memory 217944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124235543 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.124235543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.428011878
Short name T646
Test name
Test status
Simulation time 667767651 ps
CPU time 4.09 seconds
Started Sep 01 01:33:43 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428011878 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.428011878
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.2057505425
Short name T756
Test name
Test status
Simulation time 3328368353 ps
CPU time 29.43 seconds
Started Sep 01 01:33:44 PM UTC 24
Finished Sep 01 01:34:22 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057505425 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2057505425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.2508748827
Short name T668
Test name
Test status
Simulation time 129877024 ps
CPU time 1.28 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:58 PM UTC 24
Peak memory 215640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508748827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2508748827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.245972462
Short name T645
Test name
Test status
Simulation time 80839664 ps
CPU time 3.17 seconds
Started Sep 01 01:33:41 PM UTC 24
Finished Sep 01 01:33:55 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245972462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.245972462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3081039739
Short name T235
Test name
Test status
Simulation time 2292994572 ps
CPU time 45.71 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:43 PM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081039739 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3081039739
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.399101644
Short name T706
Test name
Test status
Simulation time 515142400 ps
CPU time 11.65 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 232496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=399101644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr
_stress_all_with_rand_reset.399101644
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.2562439879
Short name T721
Test name
Test status
Simulation time 795450537 ps
CPU time 15.78 seconds
Started Sep 01 01:33:54 PM UTC 24
Finished Sep 01 01:34:12 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562439879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2562439879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.3727322371
Short name T672
Test name
Test status
Simulation time 101218278 ps
CPU time 1.89 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 219616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727322371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3727322371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.1111702253
Short name T680
Test name
Test status
Simulation time 42390645 ps
CPU time 0.73 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:02 PM UTC 24
Peak memory 213572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111702253 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1111702253
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.774337385
Short name T444
Test name
Test status
Simulation time 69758837 ps
CPU time 2.55 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 224392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774337385 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.774337385
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.1023589140
Short name T684
Test name
Test status
Simulation time 312505567 ps
CPU time 2.6 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:02 PM UTC 24
Peak memory 228536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023589140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1023589140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.2068759865
Short name T356
Test name
Test status
Simulation time 598539112 ps
CPU time 14.37 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:12 PM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068759865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2068759865
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.2536179294
Short name T687
Test name
Test status
Simulation time 147853941 ps
CPU time 3.25 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:03 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536179294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2536179294
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.3504160119
Short name T693
Test name
Test status
Simulation time 151805542 ps
CPU time 4.66 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504160119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3504160119
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.2235022886
Short name T700
Test name
Test status
Simulation time 2145115225 ps
CPU time 6.84 seconds
Started Sep 01 01:33:58 PM UTC 24
Finished Sep 01 01:34:06 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235022886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2235022886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_random.3033637636
Short name T674
Test name
Test status
Simulation time 172677468 ps
CPU time 2.72 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:00 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033637636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3033637636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2074034621
Short name T685
Test name
Test status
Simulation time 1069359302 ps
CPU time 5.5 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:03 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074034621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2074034621
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.1048125234
Short name T655
Test name
Test status
Simulation time 105056526 ps
CPU time 2.34 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048125234 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1048125234
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.3161035320
Short name T727
Test name
Test status
Simulation time 2384118021 ps
CPU time 16.34 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:34:14 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161035320 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3161035320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.889599680
Short name T673
Test name
Test status
Simulation time 43780075 ps
CPU time 2.11 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 217908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889599680 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.889599680
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.1505555816
Short name T682
Test name
Test status
Simulation time 108321980 ps
CPU time 2.16 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:02 PM UTC 24
Peak memory 218028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505555816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1505555816
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.3339501231
Short name T628
Test name
Test status
Simulation time 92852337 ps
CPU time 2.11 seconds
Started Sep 01 01:33:56 PM UTC 24
Finished Sep 01 01:33:59 PM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339501231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3339501231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1255846123
Short name T407
Test name
Test status
Simulation time 1523478346 ps
CPU time 15.96 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255846123 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1255846123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.3259079819
Short name T735
Test name
Test status
Simulation time 519426876 ps
CPU time 16.44 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 228448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259079819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3259079819
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.2122123754
Short name T679
Test name
Test status
Simulation time 34787369 ps
CPU time 1.51 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:01 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122123754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2122123754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.1050098494
Short name T683
Test name
Test status
Simulation time 55725091 ps
CPU time 0.81 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:02 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050098494 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1050098494
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.1912674410
Short name T445
Test name
Test status
Simulation time 1140694716 ps
CPU time 7.96 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912674410 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1912674410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.1969507667
Short name T691
Test name
Test status
Simulation time 58963555 ps
CPU time 2.5 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 231496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969507667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1969507667
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.1030571155
Short name T156
Test name
Test status
Simulation time 255614132 ps
CPU time 3 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030571155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1030571155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3964460581
Short name T768
Test name
Test status
Simulation time 1441361239 ps
CPU time 22.68 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 231100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964460581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3964460581
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.1905740425
Short name T692
Test name
Test status
Simulation time 55268174 ps
CPU time 2.76 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 228068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905740425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1905740425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.25890553
Short name T698
Test name
Test status
Simulation time 191503890 ps
CPU time 4.29 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:06 PM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25890553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.25890553
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_random.1267094859
Short name T689
Test name
Test status
Simulation time 156446845 ps
CPU time 2.47 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267094859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1267094859
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.758337689
Short name T686
Test name
Test status
Simulation time 68346312 ps
CPU time 1.93 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:03 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758337689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.758337689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.3779222932
Short name T752
Test name
Test status
Simulation time 810944957 ps
CPU time 17.9 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:19 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779222932 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3779222932
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.854552742
Short name T808
Test name
Test status
Simulation time 4046262779 ps
CPU time 31.66 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:33 PM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854552742 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.854552742
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.3519806035
Short name T695
Test name
Test status
Simulation time 295148617 ps
CPU time 3.49 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:05 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519806035 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3519806035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.260446738
Short name T690
Test name
Test status
Simulation time 376342745 ps
CPU time 2.23 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260446738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.260446738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.1441919864
Short name T688
Test name
Test status
Simulation time 386755296 ps
CPU time 2.72 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:04 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441919864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1441919864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.195012055
Short name T901
Test name
Test status
Simulation time 81118454299 ps
CPU time 216.19 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:37:40 PM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195012055 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.195012055
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.3497357377
Short name T720
Test name
Test status
Simulation time 1087933370 ps
CPU time 9.12 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:11 PM UTC 24
Peak memory 232160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3497357377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymg
r_stress_all_with_rand_reset.3497357377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.3568633880
Short name T374
Test name
Test status
Simulation time 2724338748 ps
CPU time 8.24 seconds
Started Sep 01 01:33:59 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 230232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568633880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3568633880
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2319338461
Short name T701
Test name
Test status
Simulation time 10743732 ps
CPU time 0.94 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:07 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319338461 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2319338461
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.164953635
Short name T452
Test name
Test status
Simulation time 491065788 ps
CPU time 7.57 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:13 PM UTC 24
Peak memory 226196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164953635 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.164953635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.4254224551
Short name T26
Test name
Test status
Simulation time 262433048 ps
CPU time 2.18 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:08 PM UTC 24
Peak memory 224696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254224551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4254224551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.3334672516
Short name T708
Test name
Test status
Simulation time 244480482 ps
CPU time 2.82 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334672516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3334672516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.1747013490
Short name T725
Test name
Test status
Simulation time 204643643 ps
CPU time 6.72 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:13 PM UTC 24
Peak memory 230172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747013490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1747013490
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.2655503261
Short name T293
Test name
Test status
Simulation time 101465031 ps
CPU time 2.1 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:08 PM UTC 24
Peak memory 216060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655503261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2655503261
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.256100124
Short name T298
Test name
Test status
Simulation time 36163465 ps
CPU time 3.35 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256100124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.256100124
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_random.969229909
Short name T713
Test name
Test status
Simulation time 144785556 ps
CPU time 3.71 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 215792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969229909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.969229909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.2234223321
Short name T705
Test name
Test status
Simulation time 303825004 ps
CPU time 2.95 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234223321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2234223321
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.949466447
Short name T736
Test name
Test status
Simulation time 4132669879 ps
CPU time 10.31 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949466447 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.949466447
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.4158643005
Short name T696
Test name
Test status
Simulation time 55224113 ps
CPU time 2.83 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:05 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158643005 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4158643005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.1209824901
Short name T702
Test name
Test status
Simulation time 26048423 ps
CPU time 2 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:08 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209824901 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1209824901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.1819129001
Short name T712
Test name
Test status
Simulation time 255358821 ps
CPU time 2.9 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819129001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1819129001
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.3447098467
Short name T694
Test name
Test status
Simulation time 38328011 ps
CPU time 1.92 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:05 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447098467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3447098467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.4173657048
Short name T794
Test name
Test status
Simulation time 1602493411 ps
CPU time 23.82 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:30 PM UTC 24
Peak memory 231964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173657048 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4173657048
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.2582193393
Short name T710
Test name
Test status
Simulation time 860139893 ps
CPU time 2.98 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 215316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582193393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2582193393
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.202091583
Short name T711
Test name
Test status
Simulation time 78647665 ps
CPU time 2.74 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202091583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.202091583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.1233788937
Short name T703
Test name
Test status
Simulation time 24019828 ps
CPU time 0.94 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:08 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233788937 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1233788937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.2076390386
Short name T10
Test name
Test status
Simulation time 85764240 ps
CPU time 3.14 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 232484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076390386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2076390386
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.2019700944
Short name T157
Test name
Test status
Simulation time 54799993 ps
CPU time 3.42 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019700944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2019700944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.2658296814
Short name T342
Test name
Test status
Simulation time 246712300 ps
CPU time 6.24 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:12 PM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658296814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2658296814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.2338563390
Short name T716
Test name
Test status
Simulation time 295358352 ps
CPU time 3.62 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338563390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2338563390
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_random.1333455447
Short name T843
Test name
Test status
Simulation time 4517603663 ps
CPU time 28.59 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333455447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1333455447
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2352702859
Short name T707
Test name
Test status
Simulation time 79492841 ps
CPU time 2.25 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352702859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2352702859
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.3186371390
Short name T728
Test name
Test status
Simulation time 62305214 ps
CPU time 2.68 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:14 PM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186371390 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3186371390
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.1493151803
Short name T704
Test name
Test status
Simulation time 163742218 ps
CPU time 1.96 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:08 PM UTC 24
Peak memory 215988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493151803 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1493151803
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.2491667809
Short name T732
Test name
Test status
Simulation time 63561259 ps
CPU time 3.89 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:15 PM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491667809 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2491667809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1911431204
Short name T709
Test name
Test status
Simulation time 59194400 ps
CPU time 2.48 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:09 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911431204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1911431204
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.3429496657
Short name T717
Test name
Test status
Simulation time 229438638 ps
CPU time 3.23 seconds
Started Sep 01 01:34:02 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 218156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429496657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3429496657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.4270184014
Short name T897
Test name
Test status
Simulation time 7927232062 ps
CPU time 91.57 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:35:39 PM UTC 24
Peak memory 232276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270184014 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4270184014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.2792326017
Short name T723
Test name
Test status
Simulation time 241835043 ps
CPU time 5.81 seconds
Started Sep 01 01:34:04 PM UTC 24
Finished Sep 01 01:34:12 PM UTC 24
Peak memory 228448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792326017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2792326017
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.229763648
Short name T714
Test name
Test status
Simulation time 286182787 ps
CPU time 2.83 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229763648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.229763648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.8382629
Short name T726
Test name
Test status
Simulation time 51206347 ps
CPU time 1 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:13 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8382629 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.8382629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.2758426831
Short name T333
Test name
Test status
Simulation time 235170287 ps
CPU time 4.75 seconds
Started Sep 01 01:34:07 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758426831 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2758426831
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.1658323554
Short name T246
Test name
Test status
Simulation time 78210130 ps
CPU time 3.84 seconds
Started Sep 01 01:34:09 PM UTC 24
Finished Sep 01 01:34:20 PM UTC 24
Peak memory 219992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658323554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1658323554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.3993317919
Short name T388
Test name
Test status
Simulation time 202224349 ps
CPU time 4.44 seconds
Started Sep 01 01:34:07 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993317919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3993317919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.4190933769
Short name T697
Test name
Test status
Simulation time 238278810 ps
CPU time 3.55 seconds
Started Sep 01 01:34:07 PM UTC 24
Finished Sep 01 01:34:15 PM UTC 24
Peak memory 231032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190933769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4190933769
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.1216772870
Short name T754
Test name
Test status
Simulation time 195184844 ps
CPU time 4.25 seconds
Started Sep 01 01:34:09 PM UTC 24
Finished Sep 01 01:34:20 PM UTC 24
Peak memory 230724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216772870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1216772870
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.473776957
Short name T722
Test name
Test status
Simulation time 968864711 ps
CPU time 4.03 seconds
Started Sep 01 01:34:07 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 220364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473776957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.473776957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_random.3601238841
Short name T370
Test name
Test status
Simulation time 401986187 ps
CPU time 8.86 seconds
Started Sep 01 01:34:07 PM UTC 24
Finished Sep 01 01:34:20 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601238841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3601238841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.1834159020
Short name T718
Test name
Test status
Simulation time 73587842 ps
CPU time 2.86 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834159020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1834159020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.1924477380
Short name T715
Test name
Test status
Simulation time 46582921 ps
CPU time 2.62 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924477380 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1924477380
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.2967384685
Short name T719
Test name
Test status
Simulation time 385863920 ps
CPU time 2.96 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:10 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967384685 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2967384685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.3827329628
Short name T724
Test name
Test status
Simulation time 376191392 ps
CPU time 5.4 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:12 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827329628 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3827329628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.245978217
Short name T755
Test name
Test status
Simulation time 196009065 ps
CPU time 5.19 seconds
Started Sep 01 01:34:09 PM UTC 24
Finished Sep 01 01:34:21 PM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245978217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.245978217
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.1280824954
Short name T742
Test name
Test status
Simulation time 561297413 ps
CPU time 10.55 seconds
Started Sep 01 01:34:06 PM UTC 24
Finished Sep 01 01:34:17 PM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280824954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1280824954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.309833177
Short name T740
Test name
Test status
Simulation time 2571984443 ps
CPU time 17.05 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 231132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309833177 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.309833177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.4125173368
Short name T194
Test name
Test status
Simulation time 375592174 ps
CPU time 7.27 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:19 PM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4125173368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg
r_stress_all_with_rand_reset.4125173368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.3953447549
Short name T739
Test name
Test status
Simulation time 129280225 ps
CPU time 5.4 seconds
Started Sep 01 01:34:07 PM UTC 24
Finished Sep 01 01:34:17 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953447549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3953447549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.3673504820
Short name T751
Test name
Test status
Simulation time 110469639 ps
CPU time 3.09 seconds
Started Sep 01 01:34:09 PM UTC 24
Finished Sep 01 01:34:19 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673504820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3673504820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.1807434341
Short name T738
Test name
Test status
Simulation time 8941315 ps
CPU time 0.73 seconds
Started Sep 01 01:34:12 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807434341 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1807434341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.2454311194
Short name T450
Test name
Test status
Simulation time 100933407 ps
CPU time 4.15 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:17 PM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454311194 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2454311194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.661654340
Short name T238
Test name
Test status
Simulation time 78431336 ps
CPU time 3.12 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661654340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.661654340
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.2041467458
Short name T731
Test name
Test status
Simulation time 18926613 ps
CPU time 2 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:14 PM UTC 24
Peak memory 227708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041467458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2041467458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.2978857845
Short name T807
Test name
Test status
Simulation time 1237192963 ps
CPU time 20.17 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:33 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978857845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2978857845
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.3255568223
Short name T397
Test name
Test status
Simulation time 278595439 ps
CPU time 2.54 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:15 PM UTC 24
Peak memory 232272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255568223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3255568223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.1525179416
Short name T247
Test name
Test status
Simulation time 240672513 ps
CPU time 2.74 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:15 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525179416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1525179416
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_random.3424841134
Short name T744
Test name
Test status
Simulation time 1146704560 ps
CPU time 5.22 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:18 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424841134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3424841134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.4275783149
Short name T771
Test name
Test status
Simulation time 1937163755 ps
CPU time 12.67 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275783149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4275783149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.3268683855
Short name T733
Test name
Test status
Simulation time 160222505 ps
CPU time 2.61 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:15 PM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268683855 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3268683855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.1340442288
Short name T729
Test name
Test status
Simulation time 68306150 ps
CPU time 1.68 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:14 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340442288 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1340442288
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.2427261835
Short name T750
Test name
Test status
Simulation time 207138994 ps
CPU time 6.73 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:19 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427261835 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2427261835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.3316515104
Short name T396
Test name
Test status
Simulation time 73484781 ps
CPU time 2.43 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:15 PM UTC 24
Peak memory 228516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316515104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3316515104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.2735802313
Short name T741
Test name
Test status
Simulation time 1529332433 ps
CPU time 5.21 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:17 PM UTC 24
Peak memory 217116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735802313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2735802313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.2035796847
Short name T876
Test name
Test status
Simulation time 14055168416 ps
CPU time 31.92 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:48 PM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035796847 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2035796847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.380014011
Short name T195
Test name
Test status
Simulation time 1074025718 ps
CPU time 10.59 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=380014011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr
_stress_all_with_rand_reset.380014011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.603955275
Short name T734
Test name
Test status
Simulation time 68817859 ps
CPU time 3.36 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:16 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603955275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.603955275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.538721963
Short name T730
Test name
Test status
Simulation time 281871458 ps
CPU time 1.75 seconds
Started Sep 01 01:34:11 PM UTC 24
Finished Sep 01 01:34:14 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538721963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.538721963
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.3607759426
Short name T85
Test name
Test status
Simulation time 9780679 ps
CPU time 0.8 seconds
Started Sep 01 01:31:51 PM UTC 24
Finished Sep 01 01:31:53 PM UTC 24
Peak memory 213536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607759426 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3607759426
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.2923417869
Short name T30
Test name
Test status
Simulation time 299978630 ps
CPU time 9.53 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923417869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2923417869
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.551428215
Short name T86
Test name
Test status
Simulation time 64908863 ps
CPU time 2.15 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:53 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551428215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.551428215
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2885329160
Short name T73
Test name
Test status
Simulation time 108058568 ps
CPU time 3.34 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:55 PM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885329160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2885329160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_random.1373616161
Short name T20
Test name
Test status
Simulation time 707637201 ps
CPU time 5.7 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:54 PM UTC 24
Peak memory 215884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373616161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1373616161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.625780645
Short name T47
Test name
Test status
Simulation time 590318583 ps
CPU time 10.44 seconds
Started Sep 01 01:31:51 PM UTC 24
Finished Sep 01 01:32:02 PM UTC 24
Peak memory 254568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625780645 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.625780645
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.1459677811
Short name T309
Test name
Test status
Simulation time 3393032465 ps
CPU time 21.65 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:32:10 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459677811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1459677811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.3544817092
Short name T221
Test name
Test status
Simulation time 97737247 ps
CPU time 1.86 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:50 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544817092 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3544817092
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.4115523532
Short name T106
Test name
Test status
Simulation time 58867203 ps
CPU time 2.03 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115523532 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4115523532
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.1115832972
Short name T191
Test name
Test status
Simulation time 110840590 ps
CPU time 2.93 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:52 PM UTC 24
Peak memory 215788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115832972 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1115832972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.491737918
Short name T158
Test name
Test status
Simulation time 268228540 ps
CPU time 3.13 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:55 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491737918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.491737918
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.1545060615
Short name T187
Test name
Test status
Simulation time 66719503 ps
CPU time 2.71 seconds
Started Sep 01 01:31:47 PM UTC 24
Finished Sep 01 01:31:51 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545060615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1545060615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.3946065408
Short name T215
Test name
Test status
Simulation time 248976444 ps
CPU time 7.69 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946065408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3946065408
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.611402022
Short name T45
Test name
Test status
Simulation time 202138693 ps
CPU time 1.89 seconds
Started Sep 01 01:31:50 PM UTC 24
Finished Sep 01 01:31:53 PM UTC 24
Peak memory 219616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611402022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.611402022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.3324550896
Short name T745
Test name
Test status
Simulation time 47335094 ps
CPU time 0.79 seconds
Started Sep 01 01:34:15 PM UTC 24
Finished Sep 01 01:34:18 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324550896 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3324550896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.3442682010
Short name T253
Test name
Test status
Simulation time 157639957 ps
CPU time 3.6 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 232504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442682010 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3442682010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.333770427
Short name T761
Test name
Test status
Simulation time 268650578 ps
CPU time 6.03 seconds
Started Sep 01 01:34:15 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 220092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333770427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.333770427
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.1764075158
Short name T350
Test name
Test status
Simulation time 175612507 ps
CPU time 3.05 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:28 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764075158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1764075158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.3113956359
Short name T779
Test name
Test status
Simulation time 50222586 ps
CPU time 1.78 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:26 PM UTC 24
Peak memory 223608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113956359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3113956359
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.2458606704
Short name T748
Test name
Test status
Simulation time 374275449 ps
CPU time 1.99 seconds
Started Sep 01 01:34:15 PM UTC 24
Finished Sep 01 01:34:19 PM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458606704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2458606704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.3372119774
Short name T788
Test name
Test status
Simulation time 232544360 ps
CPU time 3.72 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:28 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372119774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3372119774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_random.1096154687
Short name T781
Test name
Test status
Simulation time 129587761 ps
CPU time 2.6 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 225848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096154687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1096154687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.1691470166
Short name T757
Test name
Test status
Simulation time 715829898 ps
CPU time 6.51 seconds
Started Sep 01 01:34:12 PM UTC 24
Finished Sep 01 01:34:22 PM UTC 24
Peak memory 217692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691470166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1691470166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.945280039
Short name T747
Test name
Test status
Simulation time 38625717 ps
CPU time 2.34 seconds
Started Sep 01 01:34:12 PM UTC 24
Finished Sep 01 01:34:18 PM UTC 24
Peak memory 215824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945280039 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.945280039
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.969303
Short name T743
Test name
Test status
Simulation time 23780308 ps
CPU time 1.61 seconds
Started Sep 01 01:34:12 PM UTC 24
Finished Sep 01 01:34:17 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969303 -assert nopostproc +UVM_TESTNAME=keymgr_base_t
est +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.969303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.3605852824
Short name T811
Test name
Test status
Simulation time 702327829 ps
CPU time 8.96 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:33 PM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605852824 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3605852824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.3755549730
Short name T795
Test name
Test status
Simulation time 776691018 ps
CPU time 13.38 seconds
Started Sep 01 01:34:15 PM UTC 24
Finished Sep 01 01:34:30 PM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755549730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3755549730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.3565194635
Short name T746
Test name
Test status
Simulation time 273608365 ps
CPU time 1.91 seconds
Started Sep 01 01:34:12 PM UTC 24
Finished Sep 01 01:34:18 PM UTC 24
Peak memory 215336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565194635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3565194635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.84546348
Short name T408
Test name
Test status
Simulation time 258160171 ps
CPU time 12.37 seconds
Started Sep 01 01:34:15 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84546348 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.84546348
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.1705800483
Short name T805
Test name
Test status
Simulation time 1145635591 ps
CPU time 7.26 seconds
Started Sep 01 01:34:13 PM UTC 24
Finished Sep 01 01:34:32 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705800483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1705800483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.3242249525
Short name T749
Test name
Test status
Simulation time 158489586 ps
CPU time 1.92 seconds
Started Sep 01 01:34:15 PM UTC 24
Finished Sep 01 01:34:19 PM UTC 24
Peak memory 219412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242249525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3242249525
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.2603355014
Short name T766
Test name
Test status
Simulation time 20888689 ps
CPU time 1.06 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603355014 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2603355014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.181476460
Short name T438
Test name
Test status
Simulation time 108966956 ps
CPU time 3.39 seconds
Started Sep 01 01:34:17 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181476460 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.181476460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.135020258
Short name T236
Test name
Test status
Simulation time 28700614 ps
CPU time 1.77 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 217540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135020258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.135020258
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.996659189
Short name T769
Test name
Test status
Simulation time 359390936 ps
CPU time 3.73 seconds
Started Sep 01 01:34:17 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 223952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996659189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.996659189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.645486738
Short name T378
Test name
Test status
Simulation time 468715130 ps
CPU time 4.51 seconds
Started Sep 01 01:34:18 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645486738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.645486738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.1191495098
Short name T341
Test name
Test status
Simulation time 50049601 ps
CPU time 2.92 seconds
Started Sep 01 01:34:18 PM UTC 24
Finished Sep 01 01:34:26 PM UTC 24
Peak memory 232096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191495098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1191495098
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.1885406777
Short name T243
Test name
Test status
Simulation time 185083790 ps
CPU time 5.48 seconds
Started Sep 01 01:34:17 PM UTC 24
Finished Sep 01 01:34:30 PM UTC 24
Peak memory 218036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885406777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1885406777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_random.2240256276
Short name T753
Test name
Test status
Simulation time 207290562 ps
CPU time 4.42 seconds
Started Sep 01 01:34:17 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 227912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240256276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2240256276
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.1578498593
Short name T759
Test name
Test status
Simulation time 40218961 ps
CPU time 2.05 seconds
Started Sep 01 01:34:16 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578498593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1578498593
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.3892838407
Short name T763
Test name
Test status
Simulation time 70316217 ps
CPU time 2.81 seconds
Started Sep 01 01:34:16 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892838407 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3892838407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.2804782407
Short name T760
Test name
Test status
Simulation time 31929909 ps
CPU time 1.98 seconds
Started Sep 01 01:34:16 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804782407 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2804782407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.1926256279
Short name T765
Test name
Test status
Simulation time 76413566 ps
CPU time 3.18 seconds
Started Sep 01 01:34:16 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926256279 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1926256279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.3908406493
Short name T773
Test name
Test status
Simulation time 190382060 ps
CPU time 2.22 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908406493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3908406493
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.3558996953
Short name T782
Test name
Test status
Simulation time 103307838 ps
CPU time 2.44 seconds
Started Sep 01 01:34:16 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558996953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3558996953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.3973494341
Short name T895
Test name
Test status
Simulation time 5618053577 ps
CPU time 63.04 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:35:27 PM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973494341 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3973494341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.2602632613
Short name T237
Test name
Test status
Simulation time 2050932834 ps
CPU time 16.09 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:39 PM UTC 24
Peak memory 232636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2602632613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymg
r_stress_all_with_rand_reset.2602632613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.725432295
Short name T791
Test name
Test status
Simulation time 107646573 ps
CPU time 4.44 seconds
Started Sep 01 01:34:17 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725432295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.725432295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.436564206
Short name T178
Test name
Test status
Simulation time 32175630 ps
CPU time 1.82 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436564206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.436564206
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.21513907
Short name T767
Test name
Test status
Simulation time 33262422 ps
CPU time 1.08 seconds
Started Sep 01 01:34:22 PM UTC 24
Finished Sep 01 01:34:24 PM UTC 24
Peak memory 213668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21513907 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.21513907
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.4161452921
Short name T439
Test name
Test status
Simulation time 318193072 ps
CPU time 15.11 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161452921 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.4161452921
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.1530404866
Short name T775
Test name
Test status
Simulation time 320712131 ps
CPU time 4.1 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:26 PM UTC 24
Peak memory 228496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530404866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1530404866
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.3196727815
Short name T758
Test name
Test status
Simulation time 429098474 ps
CPU time 1.37 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 215764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196727815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3196727815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.417037934
Short name T774
Test name
Test status
Simulation time 90071090 ps
CPU time 3.56 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417037934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.417037934
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.1015389608
Short name T294
Test name
Test status
Simulation time 51470210 ps
CPU time 3.07 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015389608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1015389608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.555756469
Short name T770
Test name
Test status
Simulation time 126783477 ps
CPU time 3.3 seconds
Started Sep 01 01:34:20 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555756469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.555756469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_random.2328440052
Short name T787
Test name
Test status
Simulation time 138642966 ps
CPU time 4.61 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:28 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328440052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2328440052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.627790946
Short name T872
Test name
Test status
Simulation time 948732691 ps
CPU time 23.52 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:47 PM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627790946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.627790946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.2011141480
Short name T894
Test name
Test status
Simulation time 7097424785 ps
CPU time 58.89 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:35:23 PM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011141480 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2011141480
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.1492374622
Short name T778
Test name
Test status
Simulation time 297966820 ps
CPU time 3.26 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:26 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492374622 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1492374622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.3553686049
Short name T777
Test name
Test status
Simulation time 65275534 ps
CPU time 2.96 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:26 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553686049 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3553686049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.508301207
Short name T764
Test name
Test status
Simulation time 221668011 ps
CPU time 1.77 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:23 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508301207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.508301207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.1123456765
Short name T772
Test name
Test status
Simulation time 113375518 ps
CPU time 1.94 seconds
Started Sep 01 01:34:19 PM UTC 24
Finished Sep 01 01:34:25 PM UTC 24
Peak memory 214116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123456765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1123456765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.2641577901
Short name T870
Test name
Test status
Simulation time 1369747924 ps
CPU time 24.24 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:46 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641577901 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2641577901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.3156326479
Short name T879
Test name
Test status
Simulation time 1243728361 ps
CPU time 27.62 seconds
Started Sep 01 01:34:20 PM UTC 24
Finished Sep 01 01:34:49 PM UTC 24
Peak memory 220264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156326479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3156326479
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.3040607082
Short name T184
Test name
Test status
Simulation time 1534931759 ps
CPU time 6.8 seconds
Started Sep 01 01:34:21 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 219680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040607082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3040607082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.3624108959
Short name T786
Test name
Test status
Simulation time 11908418 ps
CPU time 0.96 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:28 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624108959 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3624108959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.1068835365
Short name T381
Test name
Test status
Simulation time 67261286 ps
CPU time 3.87 seconds
Started Sep 01 01:34:25 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 220352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068835365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1068835365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.3047773526
Short name T785
Test name
Test status
Simulation time 56020516 ps
CPU time 2.55 seconds
Started Sep 01 01:34:24 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047773526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3047773526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.896349084
Short name T814
Test name
Test status
Simulation time 985225114 ps
CPU time 7.41 seconds
Started Sep 01 01:34:25 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 224348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896349084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.896349084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1730896037
Short name T799
Test name
Test status
Simulation time 89459294 ps
CPU time 4.08 seconds
Started Sep 01 01:34:25 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730896037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1730896037
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.1880994547
Short name T790
Test name
Test status
Simulation time 751959039 ps
CPU time 4.52 seconds
Started Sep 01 01:34:24 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880994547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1880994547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_random.940124829
Short name T796
Test name
Test status
Simulation time 429943606 ps
CPU time 5.72 seconds
Started Sep 01 01:34:23 PM UTC 24
Finished Sep 01 01:34:30 PM UTC 24
Peak memory 228196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940124829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.940124829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.3730416084
Short name T776
Test name
Test status
Simulation time 196640524 ps
CPU time 2.84 seconds
Started Sep 01 01:34:22 PM UTC 24
Finished Sep 01 01:34:26 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730416084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3730416084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.2489498592
Short name T856
Test name
Test status
Simulation time 1557035526 ps
CPU time 19.86 seconds
Started Sep 01 01:34:22 PM UTC 24
Finished Sep 01 01:34:43 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489498592 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2489498592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.530643906
Short name T784
Test name
Test status
Simulation time 391986986 ps
CPU time 4.05 seconds
Started Sep 01 01:34:22 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530643906 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.530643906
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.2810899120
Short name T783
Test name
Test status
Simulation time 65004427 ps
CPU time 2.66 seconds
Started Sep 01 01:34:23 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810899120 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2810899120
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.1234317007
Short name T737
Test name
Test status
Simulation time 142062981 ps
CPU time 2.04 seconds
Started Sep 01 01:34:25 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 218260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234317007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1234317007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.464680337
Short name T780
Test name
Test status
Simulation time 95026315 ps
CPU time 3.46 seconds
Started Sep 01 01:34:22 PM UTC 24
Finished Sep 01 01:34:27 PM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464680337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.464680337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.4184730473
Short name T896
Test name
Test status
Simulation time 4599892041 ps
CPU time 66.34 seconds
Started Sep 01 01:34:24 PM UTC 24
Finished Sep 01 01:35:32 PM UTC 24
Peak memory 218272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184730473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4184730473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.1051487270
Short name T793
Test name
Test status
Simulation time 214582095 ps
CPU time 3.45 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:30 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051487270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1051487270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.580476046
Short name T800
Test name
Test status
Simulation time 47923435 ps
CPU time 1.27 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580476046 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.580476046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.1119604820
Short name T455
Test name
Test status
Simulation time 81008130 ps
CPU time 2.92 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:32 PM UTC 24
Peak memory 225784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119604820 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1119604820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.3648499011
Short name T836
Test name
Test status
Simulation time 1590350135 ps
CPU time 7.83 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648499011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3648499011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.2291866950
Short name T801
Test name
Test status
Simulation time 117941557 ps
CPU time 2.35 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 217480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291866950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2291866950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.3334335116
Short name T818
Test name
Test status
Simulation time 495412674 ps
CPU time 4.98 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334335116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3334335116
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.3274854680
Short name T812
Test name
Test status
Simulation time 102834393 ps
CPU time 4.44 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274854680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3274854680
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.1982076506
Short name T804
Test name
Test status
Simulation time 232754299 ps
CPU time 2.67 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:32 PM UTC 24
Peak memory 230268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982076506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1982076506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_random.153460243
Short name T816
Test name
Test status
Simulation time 341832686 ps
CPU time 6.99 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153460243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.153460243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.1269869640
Short name T762
Test name
Test status
Simulation time 263669900 ps
CPU time 2.48 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 216104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269869640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1269869640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.1085898719
Short name T797
Test name
Test status
Simulation time 442665804 ps
CPU time 3.53 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085898719 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1085898719
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.1568596816
Short name T798
Test name
Test status
Simulation time 134241966 ps
CPU time 3.61 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568596816 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1568596816
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.1593997802
Short name T803
Test name
Test status
Simulation time 226268761 ps
CPU time 4.35 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593997802 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1593997802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1607934800
Short name T819
Test name
Test status
Simulation time 597752401 ps
CPU time 5.37 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607934800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1607934800
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.837182306
Short name T789
Test name
Test status
Simulation time 190836485 ps
CPU time 2.41 seconds
Started Sep 01 01:34:26 PM UTC 24
Finished Sep 01 01:34:29 PM UTC 24
Peak memory 216096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837182306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.837182306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.2081952133
Short name T899
Test name
Test status
Simulation time 20261230484 ps
CPU time 82.89 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:35:53 PM UTC 24
Peak memory 232340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081952133 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2081952133
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all_with_rand_reset.2476312599
Short name T863
Test name
Test status
Simulation time 390508752 ps
CPU time 14.68 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 232636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2476312599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymg
r_stress_all_with_rand_reset.2476312599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.2143286291
Short name T820
Test name
Test status
Simulation time 2129101215 ps
CPU time 5.61 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143286291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2143286291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.1946487202
Short name T802
Test name
Test status
Simulation time 100538070 ps
CPU time 1.98 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:31 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946487202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1946487202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.906046380
Short name T809
Test name
Test status
Simulation time 10610560 ps
CPU time 0.84 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:33 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906046380 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.906046380
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.1011818781
Short name T813
Test name
Test status
Simulation time 278233829 ps
CPU time 2.45 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011818781 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1011818781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.3026686948
Short name T861
Test name
Test status
Simulation time 2328368859 ps
CPU time 11.76 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 230720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026686948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3026686948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.1231775884
Short name T849
Test name
Test status
Simulation time 362298307 ps
CPU time 8.68 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231775884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1231775884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.2923512519
Short name T395
Test name
Test status
Simulation time 348180729 ps
CPU time 4.25 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923512519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2923512519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.2123588486
Short name T821
Test name
Test status
Simulation time 67699036 ps
CPU time 3.37 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123588486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2123588486
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_random.2926519288
Short name T824
Test name
Test status
Simulation time 93134407 ps
CPU time 3.74 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926519288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2926519288
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.424866489
Short name T806
Test name
Test status
Simulation time 112614793 ps
CPU time 2.81 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:32 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424866489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.424866489
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.1803037251
Short name T817
Test name
Test status
Simulation time 492053362 ps
CPU time 2.75 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803037251 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1803037251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.2582597028
Short name T887
Test name
Test status
Simulation time 1773807920 ps
CPU time 28.55 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:35:00 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582597028 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2582597028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.1438030590
Short name T823
Test name
Test status
Simulation time 73548759 ps
CPU time 3.69 seconds
Started Sep 01 01:34:30 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438030590 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1438030590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.3498864377
Short name T815
Test name
Test status
Simulation time 361323357 ps
CPU time 2.06 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:34 PM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498864377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3498864377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.525636137
Short name T822
Test name
Test status
Simulation time 265583258 ps
CPU time 5.56 seconds
Started Sep 01 01:34:28 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 217912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525636137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.525636137
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.1618376843
Short name T883
Test name
Test status
Simulation time 398479285 ps
CPU time 17.79 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:50 PM UTC 24
Peak memory 226108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618376843 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1618376843
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.802995271
Short name T825
Test name
Test status
Simulation time 217187489 ps
CPU time 3.69 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:35 PM UTC 24
Peak memory 220032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802995271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.802995271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.2454674637
Short name T827
Test name
Test status
Simulation time 383886298 ps
CPU time 4.07 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 219992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454674637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2454674637
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.1831907929
Short name T830
Test name
Test status
Simulation time 24521971 ps
CPU time 0.74 seconds
Started Sep 01 01:34:34 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831907929 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1831907929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.3560911318
Short name T893
Test name
Test status
Simulation time 4762472244 ps
CPU time 43.16 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:35:18 PM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560911318 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3560911318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.817465898
Short name T837
Test name
Test status
Simulation time 222342034 ps
CPU time 3.07 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817465898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.817465898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.2323854144
Short name T416
Test name
Test status
Simulation time 184626918 ps
CPU time 2.87 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 232484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323854144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2323854144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.1076726824
Short name T832
Test name
Test status
Simulation time 129192344 ps
CPU time 2.46 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076726824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1076726824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.2970548721
Short name T230
Test name
Test status
Simulation time 94460179 ps
CPU time 2.54 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970548721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2970548721
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_random.2729847132
Short name T841
Test name
Test status
Simulation time 148616570 ps
CPU time 5.34 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 220064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729847132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2729847132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.1138912481
Short name T829
Test name
Test status
Simulation time 179903138 ps
CPU time 2.27 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 218160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138912481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1138912481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.1589821425
Short name T844
Test name
Test status
Simulation time 297838346 ps
CPU time 5.95 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589821425 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1589821425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.2494242100
Short name T828
Test name
Test status
Simulation time 238650726 ps
CPU time 2.12 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:36 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494242100 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2494242100
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.3732828123
Short name T831
Test name
Test status
Simulation time 221140084 ps
CPU time 2.6 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 216200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732828123 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3732828123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.1302719305
Short name T839
Test name
Test status
Simulation time 95957658 ps
CPU time 2.8 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:38 PM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302719305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1302719305
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.345893722
Short name T835
Test name
Test status
Simulation time 156093491 ps
CPU time 4.84 seconds
Started Sep 01 01:34:31 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345893722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.345893722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.2232834312
Short name T389
Test name
Test status
Simulation time 8600149732 ps
CPU time 53.06 seconds
Started Sep 01 01:34:34 PM UTC 24
Finished Sep 01 01:35:29 PM UTC 24
Peak memory 230964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232834312 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2232834312
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.2831002152
Short name T385
Test name
Test status
Simulation time 576157011 ps
CPU time 7.91 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:42 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831002152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2831002152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.1608601371
Short name T833
Test name
Test status
Simulation time 60523210 ps
CPU time 2.35 seconds
Started Sep 01 01:34:33 PM UTC 24
Finished Sep 01 01:34:37 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608601371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1608601371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.4013385637
Short name T848
Test name
Test status
Simulation time 104267207 ps
CPU time 0.9 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013385637 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4013385637
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.3481526299
Short name T454
Test name
Test status
Simulation time 497636139 ps
CPU time 6 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:43 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481526299 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3481526299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.3985558864
Short name T842
Test name
Test status
Simulation time 242128662 ps
CPU time 2.77 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985558864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3985558864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.501095469
Short name T851
Test name
Test status
Simulation time 489092263 ps
CPU time 4.34 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:41 PM UTC 24
Peak memory 230676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501095469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.501095469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.3095681060
Short name T847
Test name
Test status
Simulation time 2071183900 ps
CPU time 3.31 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095681060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3095681060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.2283106927
Short name T846
Test name
Test status
Simulation time 237238664 ps
CPU time 3.15 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 224240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283106927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2283106927
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.2471480275
Short name T845
Test name
Test status
Simulation time 144176195 ps
CPU time 3.23 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:40 PM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471480275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2471480275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_random.395224753
Short name T898
Test name
Test status
Simulation time 8505306703 ps
CPU time 65.22 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:35:43 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395224753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.395224753
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.2082516726
Short name T858
Test name
Test status
Simulation time 817842236 ps
CPU time 7.66 seconds
Started Sep 01 01:34:34 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082516726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2082516726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.639052925
Short name T792
Test name
Test status
Simulation time 159073565 ps
CPU time 5.17 seconds
Started Sep 01 01:34:35 PM UTC 24
Finished Sep 01 01:34:42 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639052925 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.639052925
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.3259256171
Short name T840
Test name
Test status
Simulation time 82033520 ps
CPU time 2.2 seconds
Started Sep 01 01:34:35 PM UTC 24
Finished Sep 01 01:34:39 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259256171 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3259256171
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.475310033
Short name T881
Test name
Test status
Simulation time 502680700 ps
CPU time 12.89 seconds
Started Sep 01 01:34:35 PM UTC 24
Finished Sep 01 01:34:50 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475310033 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.475310033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.1172849060
Short name T850
Test name
Test status
Simulation time 121388506 ps
CPU time 3.66 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:34:41 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172849060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1172849060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.3423300691
Short name T838
Test name
Test status
Simulation time 143133776 ps
CPU time 1.92 seconds
Started Sep 01 01:34:34 PM UTC 24
Finished Sep 01 01:34:38 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423300691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3423300691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.2345269721
Short name T888
Test name
Test status
Simulation time 2548495472 ps
CPU time 26.42 seconds
Started Sep 01 01:34:36 PM UTC 24
Finished Sep 01 01:35:04 PM UTC 24
Peak memory 228184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345269721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2345269721
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2547488763
Short name T862
Test name
Test status
Simulation time 64609575 ps
CPU time 0.92 seconds
Started Sep 01 01:34:39 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 213720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547488763 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2547488763
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.777841622
Short name T453
Test name
Test status
Simulation time 35532155 ps
CPU time 2.77 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:45 PM UTC 24
Peak memory 224312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777841622 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.777841622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.3295849324
Short name T884
Test name
Test status
Simulation time 1443834619 ps
CPU time 10.06 seconds
Started Sep 01 01:34:39 PM UTC 24
Finished Sep 01 01:34:51 PM UTC 24
Peak memory 224700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295849324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3295849324
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2040313193
Short name T868
Test name
Test status
Simulation time 132939580 ps
CPU time 2.95 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:45 PM UTC 24
Peak memory 220276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040313193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2040313193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.2210320497
Short name T415
Test name
Test status
Simulation time 163336898 ps
CPU time 3.55 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 226400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210320497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2210320497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.2423993140
Short name T859
Test name
Test status
Simulation time 140743768 ps
CPU time 2.54 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423993140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2423993140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.1165828127
Short name T867
Test name
Test status
Simulation time 155638133 ps
CPU time 2.81 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:45 PM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165828127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1165828127
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_random.2493185896
Short name T878
Test name
Test status
Simulation time 491611049 ps
CPU time 5.63 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:48 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493185896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2493185896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.2600513715
Short name T855
Test name
Test status
Simulation time 1093913852 ps
CPU time 3.43 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:43 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600513715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2600513715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.854329429
Short name T889
Test name
Test status
Simulation time 2766882319 ps
CPU time 23.12 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:35:06 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854329429 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.854329429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3028587035
Short name T871
Test name
Test status
Simulation time 2067038631 ps
CPU time 4.28 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:47 PM UTC 24
Peak memory 218312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028587035 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3028587035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.1784721451
Short name T866
Test name
Test status
Simulation time 215257616 ps
CPU time 2.6 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:45 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784721451 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1784721451
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.2699748321
Short name T854
Test name
Test status
Simulation time 118660769 ps
CPU time 1.89 seconds
Started Sep 01 01:34:39 PM UTC 24
Finished Sep 01 01:34:43 PM UTC 24
Peak memory 217624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699748321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2699748321
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.2409252686
Short name T852
Test name
Test status
Simulation time 216440848 ps
CPU time 2.42 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:42 PM UTC 24
Peak memory 216104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409252686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2409252686
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.855303245
Short name T343
Test name
Test status
Simulation time 2685682527 ps
CPU time 42.73 seconds
Started Sep 01 01:34:39 PM UTC 24
Finished Sep 01 01:35:26 PM UTC 24
Peak memory 231408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855303245 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.855303245
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.181982223
Short name T886
Test name
Test status
Simulation time 545598173 ps
CPU time 10.14 seconds
Started Sep 01 01:34:39 PM UTC 24
Finished Sep 01 01:34:53 PM UTC 24
Peak memory 230316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=181982223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr
_stress_all_with_rand_reset.181982223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.1672487693
Short name T885
Test name
Test status
Simulation time 468337301 ps
CPU time 10.86 seconds
Started Sep 01 01:34:38 PM UTC 24
Finished Sep 01 01:34:52 PM UTC 24
Peak memory 230276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672487693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1672487693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.2204982040
Short name T853
Test name
Test status
Simulation time 181559513 ps
CPU time 1.21 seconds
Started Sep 01 01:34:39 PM UTC 24
Finished Sep 01 01:34:42 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204982040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2204982040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.3688764746
Short name T877
Test name
Test status
Simulation time 15840821 ps
CPU time 0.8 seconds
Started Sep 01 01:34:43 PM UTC 24
Finished Sep 01 01:34:48 PM UTC 24
Peak memory 213600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688764746 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3688764746
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.2009106526
Short name T869
Test name
Test status
Simulation time 55120417 ps
CPU time 3.85 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:46 PM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009106526 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2009106526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.3349399015
Short name T874
Test name
Test status
Simulation time 256118219 ps
CPU time 3.06 seconds
Started Sep 01 01:34:42 PM UTC 24
Finished Sep 01 01:34:47 PM UTC 24
Peak memory 231436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349399015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3349399015
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.2406769171
Short name T865
Test name
Test status
Simulation time 288808967 ps
CPU time 3.09 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:45 PM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406769171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2406769171
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.2032311780
Short name T299
Test name
Test status
Simulation time 79968390 ps
CPU time 3.62 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:45 PM UTC 24
Peak memory 230240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032311780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2032311780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.1338611167
Short name T873
Test name
Test status
Simulation time 709004516 ps
CPU time 2.76 seconds
Started Sep 01 01:34:42 PM UTC 24
Finished Sep 01 01:34:47 PM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338611167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1338611167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_random.4150869240
Short name T880
Test name
Test status
Simulation time 330627756 ps
CPU time 7.77 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:49 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150869240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4150869240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.641048030
Short name T860
Test name
Test status
Simulation time 63665785 ps
CPU time 2.33 seconds
Started Sep 01 01:34:40 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641048030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.641048030
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.4210090860
Short name T864
Test name
Test status
Simulation time 166208139 ps
CPU time 2.72 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:44 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210090860 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4210090860
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.3584179203
Short name T892
Test name
Test status
Simulation time 5914372614 ps
CPU time 32.82 seconds
Started Sep 01 01:34:40 PM UTC 24
Finished Sep 01 01:35:15 PM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584179203 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3584179203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.1138730084
Short name T857
Test name
Test status
Simulation time 35974627 ps
CPU time 1.92 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:43 PM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138730084 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1138730084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.3980568583
Short name T890
Test name
Test status
Simulation time 3223542109 ps
CPU time 24.21 seconds
Started Sep 01 01:34:40 PM UTC 24
Finished Sep 01 01:35:06 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980568583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3980568583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.937943165
Short name T891
Test name
Test status
Simulation time 497253670 ps
CPU time 20.83 seconds
Started Sep 01 01:34:43 PM UTC 24
Finished Sep 01 01:35:08 PM UTC 24
Peak memory 232424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=937943165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr
_stress_all_with_rand_reset.937943165
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.1559041225
Short name T875
Test name
Test status
Simulation time 373287149 ps
CPU time 5.89 seconds
Started Sep 01 01:34:41 PM UTC 24
Finished Sep 01 01:34:48 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559041225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1559041225
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.3672686266
Short name T882
Test name
Test status
Simulation time 392728751 ps
CPU time 2.59 seconds
Started Sep 01 01:34:43 PM UTC 24
Finished Sep 01 01:34:50 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672686266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3672686266
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.1125291905
Short name T458
Test name
Test status
Simulation time 45104223 ps
CPU time 0.72 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:56 PM UTC 24
Peak memory 213388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125291905 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1125291905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.154976016
Short name T29
Test name
Test status
Simulation time 111635730 ps
CPU time 2.65 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154976016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.154976016
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.231949670
Short name T131
Test name
Test status
Simulation time 93764476 ps
CPU time 2.32 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231949670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.231949670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.2460173957
Short name T55
Test name
Test status
Simulation time 101452086 ps
CPU time 1.72 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 223308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460173957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2460173957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_random.1449807604
Short name T274
Test name
Test status
Simulation time 1221884221 ps
CPU time 7.33 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:32:02 PM UTC 24
Peak memory 228488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449807604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1449807604
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.1818659945
Short name T110
Test name
Test status
Simulation time 179153778 ps
CPU time 2.86 seconds
Started Sep 01 01:31:51 PM UTC 24
Finished Sep 01 01:31:55 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818659945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1818659945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.3253078183
Short name T436
Test name
Test status
Simulation time 1788281537 ps
CPU time 33.5 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:32:28 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253078183 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3253078183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.2192303175
Short name T460
Test name
Test status
Simulation time 720531600 ps
CPU time 4.88 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192303175 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2192303175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.1738474632
Short name T488
Test name
Test status
Simulation time 2155453094 ps
CPU time 24.32 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:32:19 PM UTC 24
Peak memory 217864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738474632 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1738474632
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.3406348723
Short name T222
Test name
Test status
Simulation time 43323418 ps
CPU time 2.68 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 218124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406348723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3406348723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.737108588
Short name T561
Test name
Test status
Simulation time 10343897316 ps
CPU time 54.07 seconds
Started Sep 01 01:31:51 PM UTC 24
Finished Sep 01 01:32:47 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737108588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.737108588
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.3888303337
Short name T79
Test name
Test status
Simulation time 489339650 ps
CPU time 9.27 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3888303337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr
_stress_all_with_rand_reset.3888303337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.3576343481
Short name T261
Test name
Test status
Simulation time 1285626063 ps
CPU time 5.59 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:32:00 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576343481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3576343481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.1461659663
Short name T46
Test name
Test status
Simulation time 137571658 ps
CPU time 2.12 seconds
Started Sep 01 01:31:53 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461659663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1461659663
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.570430039
Short name T459
Test name
Test status
Simulation time 82777638 ps
CPU time 0.92 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 213412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570430039 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.570430039
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.279634512
Short name T125
Test name
Test status
Simulation time 37392994 ps
CPU time 3.24 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 226224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279634512 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.279634512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.1921671421
Short name T35
Test name
Test status
Simulation time 40686053 ps
CPU time 2.38 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 217800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921671421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1921671421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.752674602
Short name T139
Test name
Test status
Simulation time 244412837 ps
CPU time 2.14 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752674602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.752674602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.1378208005
Short name T81
Test name
Test status
Simulation time 838137056 ps
CPU time 3.76 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378208005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1378208005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.3824685620
Short name T7
Test name
Test status
Simulation time 110407625 ps
CPU time 4.11 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:00 PM UTC 24
Peak memory 230248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824685620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3824685620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_random.2964880389
Short name T297
Test name
Test status
Simulation time 1746169134 ps
CPU time 56.66 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:52 PM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964880389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2964880389
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.863487066
Short name T211
Test name
Test status
Simulation time 228762100 ps
CPU time 2.41 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:57 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863487066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.863487066
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.2363379603
Short name T304
Test name
Test status
Simulation time 54422717 ps
CPU time 2.5 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363379603 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2363379603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.2670465292
Short name T361
Test name
Test status
Simulation time 378896083 ps
CPU time 6.65 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:02 PM UTC 24
Peak memory 218036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670465292 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2670465292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.180094362
Short name T363
Test name
Test status
Simulation time 95551793 ps
CPU time 3.57 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:59 PM UTC 24
Peak memory 224240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180094362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.180094362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.82430392
Short name T485
Test name
Test status
Simulation time 5952691559 ps
CPU time 22.74 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:18 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82430392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.82430392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.1972031001
Short name T446
Test name
Test status
Simulation time 579445020 ps
CPU time 7.92 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972031001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1972031001
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.336588649
Short name T206
Test name
Test status
Simulation time 46362228 ps
CPU time 2.13 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336588649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.336588649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.4100628462
Short name T465
Test name
Test status
Simulation time 26026392 ps
CPU time 0.95 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100628462 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4100628462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.1224351016
Short name T132
Test name
Test status
Simulation time 109376981 ps
CPU time 2.55 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:00 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224351016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1224351016
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.1826672939
Short name T266
Test name
Test status
Simulation time 66306611 ps
CPU time 2.03 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:00 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826672939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1826672939
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.2402896814
Short name T138
Test name
Test status
Simulation time 122076869 ps
CPU time 5.74 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 232324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402896814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2402896814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.3519633744
Short name T281
Test name
Test status
Simulation time 220450760 ps
CPU time 2.21 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:31:58 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519633744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3519633744
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.2249175053
Short name T462
Test name
Test status
Simulation time 88194319 ps
CPU time 3.13 seconds
Started Sep 01 01:31:56 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249175053 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2249175053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.648755023
Short name T330
Test name
Test status
Simulation time 59261018 ps
CPU time 2.53 seconds
Started Sep 01 01:31:56 PM UTC 24
Finished Sep 01 01:32:00 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648755023 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.648755023
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.1331604404
Short name T461
Test name
Test status
Simulation time 203969572 ps
CPU time 2.99 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331604404 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1331604404
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.4012077414
Short name T213
Test name
Test status
Simulation time 191313163 ps
CPU time 2.67 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:01 PM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012077414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4012077414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.173474254
Short name T427
Test name
Test status
Simulation time 3140349573 ps
CPU time 28.19 seconds
Started Sep 01 01:31:54 PM UTC 24
Finished Sep 01 01:32:24 PM UTC 24
Peak memory 218388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173474254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.173474254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.945526186
Short name T151
Test name
Test status
Simulation time 4254409685 ps
CPU time 35.25 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:36 PM UTC 24
Peak memory 232560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945526186 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.945526186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.3421104221
Short name T76
Test name
Test status
Simulation time 664813807 ps
CPU time 8.89 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:09 PM UTC 24
Peak memory 232304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3421104221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr
_stress_all_with_rand_reset.3421104221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.3101939021
Short name T277
Test name
Test status
Simulation time 240761905 ps
CPU time 6.81 seconds
Started Sep 01 01:31:57 PM UTC 24
Finished Sep 01 01:32:05 PM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101939021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3101939021
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.4001420672
Short name T468
Test name
Test status
Simulation time 13485434 ps
CPU time 0.85 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001420672 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4001420672
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.934713625
Short name T133
Test name
Test status
Simulation time 116768752 ps
CPU time 1.6 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:02 PM UTC 24
Peak memory 217692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934713625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.934713625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.2532404910
Short name T58
Test name
Test status
Simulation time 166496582 ps
CPU time 4.71 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:05 PM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532404910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2532404910
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.17989286
Short name T317
Test name
Test status
Simulation time 53022020 ps
CPU time 3.02 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17989286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.17989286
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.2274702819
Short name T224
Test name
Test status
Simulation time 41286037 ps
CPU time 2.78 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 230044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274702819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2274702819
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_random.851095439
Short name T447
Test name
Test status
Simulation time 97006428 ps
CPU time 3.75 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851095439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.851095439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.2802132901
Short name T256
Test name
Test status
Simulation time 352523576 ps
CPU time 3.98 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:04 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802132901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2802132901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.1700323702
Short name T400
Test name
Test status
Simulation time 191961742 ps
CPU time 6.55 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:07 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700323702 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1700323702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.3232656407
Short name T466
Test name
Test status
Simulation time 139100678 ps
CPU time 2.16 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232656407 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3232656407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.1227904558
Short name T371
Test name
Test status
Simulation time 66773910 ps
CPU time 2.89 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227904558 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1227904558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3830888743
Short name T435
Test name
Test status
Simulation time 72285766 ps
CPU time 2.52 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 218100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830888743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3830888743
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.283384772
Short name T467
Test name
Test status
Simulation time 101689366 ps
CPU time 3.17 seconds
Started Sep 01 01:31:59 PM UTC 24
Finished Sep 01 01:32:03 PM UTC 24
Peak memory 215764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283384772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.283384772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.3046218428
Short name T75
Test name
Test status
Simulation time 338404949 ps
CPU time 6.73 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 230372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3046218428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr
_stress_all_with_rand_reset.3046218428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.2334989141
Short name T286
Test name
Test status
Simulation time 352457029 ps
CPU time 5.71 seconds
Started Sep 01 01:32:00 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334989141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2334989141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.3828467289
Short name T469
Test name
Test status
Simulation time 29925298 ps
CPU time 1.13 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:05 PM UTC 24
Peak memory 213716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828467289 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3828467289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.570253547
Short name T218
Test name
Test status
Simulation time 42187147 ps
CPU time 2.76 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 226516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570253547 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.570253547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.473545941
Short name T31
Test name
Test status
Simulation time 328764702 ps
CPU time 3.14 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:07 PM UTC 24
Peak memory 232468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473545941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.473545941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.4178990989
Short name T335
Test name
Test status
Simulation time 69141326 ps
CPU time 2.56 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 219932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178990989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4178990989
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.3316389236
Short name T65
Test name
Test status
Simulation time 467627593 ps
CPU time 4.54 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316389236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3316389236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.1951397602
Short name T212
Test name
Test status
Simulation time 675500946 ps
CPU time 4.5 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 230916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951397602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1951397602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.1001470161
Short name T269
Test name
Test status
Simulation time 210889627 ps
CPU time 2.85 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 220048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001470161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1001470161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_random.913491809
Short name T301
Test name
Test status
Simulation time 133536724 ps
CPU time 2.87 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 217516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913491809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.913491809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.663205959
Short name T282
Test name
Test status
Simulation time 172660713 ps
CPU time 4.97 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663205959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.663205959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.1152103488
Short name T289
Test name
Test status
Simulation time 357100969 ps
CPU time 5.19 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152103488 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1152103488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.778666487
Short name T470
Test name
Test status
Simulation time 112769929 ps
CPU time 2.21 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:05 PM UTC 24
Peak memory 215564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778666487 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.778666487
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.4146994460
Short name T471
Test name
Test status
Simulation time 430726198 ps
CPU time 2.64 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146994460 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.4146994460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.3063840723
Short name T402
Test name
Test status
Simulation time 954909099 ps
CPU time 4.73 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:08 PM UTC 24
Peak memory 230356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063840723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3063840723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.332219539
Short name T473
Test name
Test status
Simulation time 856031051 ps
CPU time 2.99 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 218264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332219539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.332219539
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.3715141896
Short name T257
Test name
Test status
Simulation time 2101541351 ps
CPU time 20.13 seconds
Started Sep 01 01:32:02 PM UTC 24
Finished Sep 01 01:32:24 PM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715141896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3715141896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1244442301
Short name T140
Test name
Test status
Simulation time 45818228 ps
CPU time 2.57 seconds
Started Sep 01 01:32:03 PM UTC 24
Finished Sep 01 01:32:06 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244442301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1244442301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest
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