Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3062811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

621920

1

T1

145

T2

242

T3

388

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3267991	1			T1	283		T2	347		T3	440
values[0x0]	206896	1			T1	38		T2	95		T3	135
values[0x1]	209844	1			T1	41		T2	107		T3	125

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2102084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1582647

1

T1

205

T2

329

T3

453

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11202	1			T15	4		T16	2		T17	4
valid_sources[0x01]	16061	1			T1	18		T5	124		T16	20
valid_sources[0x02]	10978	1			T16	5		T19	4		T37	2
valid_sources[0x03]	43379	1			T16	12		T17	1		T19	5
valid_sources[0x04]	13281	1			T16	7		T19	1		T37	14
valid_sources[0x05]	11974	1			T3	5		T16	17		T19	2
valid_sources[0x06]	11995	1			T16	20		T17	4		T19	7
valid_sources[0x07]	11403	1			T16	3		T17	3		T19	2
valid_sources[0x08]	11508	1			T16	8		T17	3		T37	17
valid_sources[0x09]	11334	1			T3	14		T16	4		T17	2
valid_sources[0x0a]	12884	1			T16	1		T19	2		T37	13
valid_sources[0x0b]	18584	1			T3	19		T16	5		T17	2
valid_sources[0x0c]	11140	1			T1	5		T16	11		T17	2
valid_sources[0x0d]	12990	1			T1	7		T16	5		T19	4
valid_sources[0x0e]	11588	1			T16	3		T17	3		T19	14
valid_sources[0x0f]	10928	1			T1	20		T16	17		T19	2
valid_sources[0x10]	11431	1			T16	6		T19	2		T37	8
valid_sources[0x11]	11622	1			T16	18		T19	3		T37	35
valid_sources[0x12]	11287	1			T3	5		T16	12		T19	2
valid_sources[0x13]	18177	1			T3	9		T16	14		T19	2
valid_sources[0x14]	10787	1			T1	5		T16	4		T17	4
valid_sources[0x15]	12428	1			T16	17		T37	17		T20	7
valid_sources[0x16]	11529	1			T1	1		T16	1		T19	3
valid_sources[0x17]	12076	1			T1	2		T16	7		T19	1
valid_sources[0x18]	27838	1			T16	9		T17	1		T19	1
valid_sources[0x19]	20057	1			T16	4		T19	1		T38	1
valid_sources[0x1a]	11446	1			T3	31		T16	13		T19	1
valid_sources[0x1b]	11673	1			T16	7		T37	64		T20	3
valid_sources[0x1c]	27110	1			T4	995		T16	1		T17	5
valid_sources[0x1d]	12672	1			T16	13		T17	1		T19	3
valid_sources[0x1e]	11489	1			T17	15		T19	1		T37	30
valid_sources[0x1f]	11670	1			T16	5		T17	1		T19	1
valid_sources[0x20]	11991	1			T16	9		T17	2		T19	2
valid_sources[0x21]	12536	1			T16	6		T19	2		T37	6
valid_sources[0x22]	11531	1			T5	55		T16	3		T17	1
valid_sources[0x23]	11567	1			T3	2		T16	7		T19	2
valid_sources[0x24]	15429	1			T15	1		T16	13		T17	3
valid_sources[0x25]	16234	1			T16	1		T17	2		T19	4
valid_sources[0x26]	14626	1			T16	3		T19	3		T37	2
valid_sources[0x27]	14545	1			T1	5		T19	1		T37	22
valid_sources[0x28]	13635	1			T16	3		T17	1		T19	3
valid_sources[0x29]	12485	1			T1	13		T16	16		T19	1
valid_sources[0x2a]	11298	1			T37	16		T38	3		T27	5
valid_sources[0x2b]	11435	1			T16	9		T17	3		T19	2
valid_sources[0x2c]	12442	1			T16	1		T19	9		T37	10
valid_sources[0x2d]	12062	1			T16	10		T17	3		T19	1
valid_sources[0x2e]	12072	1			T3	11		T16	4		T19	1
valid_sources[0x2f]	13320	1			T16	9		T19	1		T37	15
valid_sources[0x30]	11880	1			T16	3		T17	1		T19	5
valid_sources[0x31]	13794	1			T16	8		T17	1		T19	6
valid_sources[0x32]	15226	1			T16	2		T17	1		T37	20
valid_sources[0x33]	12182	1			T16	6		T17	11		T19	2
valid_sources[0x34]	15934	1			T16	3		T17	3		T19	4
valid_sources[0x35]	12421	1			T16	12		T17	4		T19	1
valid_sources[0x36]	12690	1			T16	12		T19	4		T37	33
valid_sources[0x37]	11143	1			T16	15		T17	1		T19	2
valid_sources[0x38]	13452	1			T16	3		T19	4		T37	26
valid_sources[0x39]	12265	1			T37	5		T20	3		T38	1
valid_sources[0x3a]	12482	1			T15	1		T16	4		T19	2
valid_sources[0x3b]	11442	1			T16	7		T37	14		T20	57
valid_sources[0x3c]	51435	1			T16	8		T17	6		T19	2
valid_sources[0x3d]	11743	1			T16	2		T17	3		T19	1
valid_sources[0x3e]	13043	1			T1	2		T16	9		T17	1
valid_sources[0x3f]	14287	1			T16	4		T19	4		T37	17
valid_sources[0x40]	11693	1			T1	10		T16	8		T19	1
valid_sources[0x41]	22191	1			T5	352		T16	5		T17	1
valid_sources[0x42]	13113	1			T1	11		T15	1		T16	1
valid_sources[0x43]	11978	1			T16	21		T19	5		T37	11
valid_sources[0x44]	12013	1			T3	66		T16	6		T17	1
valid_sources[0x45]	81612	1			T1	2		T16	1		T19	4
valid_sources[0x46]	11627	1			T16	3		T17	7		T37	27
valid_sources[0x47]	23586	1			T16	1		T19	1		T37	36
valid_sources[0x48]	12052	1			T1	17		T17	1		T19	2
valid_sources[0x49]	36763	1			T16	1		T17	1		T19	4
valid_sources[0x4a]	13457	1			T1	1		T16	2		T19	2
valid_sources[0x4b]	14627	1			T3	21		T16	3		T37	43
valid_sources[0x4c]	12181	1			T1	6		T16	2		T17	4
valid_sources[0x4d]	12963	1			T1	2		T16	6		T19	2
valid_sources[0x4e]	12534	1			T17	2		T37	30		T38	1
valid_sources[0x4f]	11376	1			T1	6		T16	4		T17	4
valid_sources[0x50]	11761	1			T19	4		T37	14		T20	11
valid_sources[0x51]	15834	1			T1	5		T16	7		T19	2
valid_sources[0x52]	11783	1			T3	20		T16	4		T19	3
valid_sources[0x53]	12380	1			T3	9		T16	2		T17	1
valid_sources[0x54]	12740	1			T3	18		T16	4		T17	5
valid_sources[0x55]	13261	1			T16	11		T19	3		T37	5
valid_sources[0x56]	12642	1			T16	10		T19	1		T37	3
valid_sources[0x57]	14013	1			T1	17		T16	6		T19	3
valid_sources[0x58]	16084	1			T16	14		T19	2		T37	18
valid_sources[0x59]	12130	1			T1	3		T16	3		T19	2
valid_sources[0x5a]	12623	1			T5	212		T16	12		T17	2
valid_sources[0x5b]	12006	1			T16	13		T19	5		T37	3
valid_sources[0x5c]	12270	1			T15	3		T16	15		T17	2
valid_sources[0x5d]	11547	1			T3	5		T16	4		T17	1
valid_sources[0x5e]	11755	1			T16	1		T19	3		T37	32
valid_sources[0x5f]	11539	1			T5	53		T16	3		T17	8
valid_sources[0x60]	11405	1			T16	1		T17	1		T37	19
valid_sources[0x61]	12056	1			T3	4		T16	3		T17	1
valid_sources[0x62]	12971	1			T16	9		T17	1		T19	1
valid_sources[0x63]	13290	1			T1	12		T16	7		T19	1
valid_sources[0x64]	12419	1			T16	1		T19	1		T37	47
valid_sources[0x65]	11914	1			T16	11		T17	3		T19	7
valid_sources[0x66]	15819	1			T16	22		T19	4		T37	25
valid_sources[0x67]	11282	1			T3	9		T16	1		T17	1
valid_sources[0x68]	12673	1			T16	2		T19	3		T37	24
valid_sources[0x69]	11425	1			T16	12		T19	6		T37	29
valid_sources[0x6a]	14167	1			T1	4		T16	6		T17	2
valid_sources[0x6b]	15505	1			T17	1		T37	16		T38	2
valid_sources[0x6c]	21585	1			T1	2		T3	5		T16	24
valid_sources[0x6d]	14749	1			T16	17		T17	5		T19	4
valid_sources[0x6e]	65263	1			T16	6		T19	4		T37	38
valid_sources[0x6f]	13185	1			T16	8		T19	2		T37	23
valid_sources[0x70]	11570	1			T1	10		T3	2		T16	3
valid_sources[0x71]	11163	1			T16	3		T19	1		T37	17
valid_sources[0x72]	13233	1			T3	2		T16	2		T37	44
valid_sources[0x73]	11795	1			T16	10		T17	2		T19	4
valid_sources[0x74]	12124	1			T16	3		T19	1		T37	36
valid_sources[0x75]	12265	1			T1	10		T3	15		T17	1
valid_sources[0x76]	12858	1			T16	3		T17	5		T19	1
valid_sources[0x77]	13385	1			T1	7		T16	12		T17	1
valid_sources[0x78]	11436	1			T16	3		T19	1		T37	15
valid_sources[0x79]	12408	1			T17	2		T19	1		T37	6
valid_sources[0x7a]	11985	1			T16	13		T17	1		T19	4
valid_sources[0x7b]	12096	1			T3	39		T16	2		T19	1
valid_sources[0x7c]	11559	1			T16	1		T17	1		T37	36
valid_sources[0x7d]	14102	1			T1	14		T16	6		T19	6
valid_sources[0x7e]	11867	1			T16	4		T17	3		T19	2
valid_sources[0x7f]	17172	1			T16	1		T37	24		T20	6
valid_sources[0x80]	11963	1			T16	12		T17	2		T19	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

340007

1

T1

116

T2

103

T3

186

values[0x0]

all_enables

biggest_size

148362

1

T1

19

T2

67

T3

108

values[0x1]

all_enables

biggest_size

133551

1

T1

10

T2

72

T3

94