Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 3/3 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7902 |
7902 |
0 |
0 |
T1 |
9 |
9 |
0 |
0 |
T2 |
9 |
9 |
0 |
0 |
T3 |
9 |
9 |
0 |
0 |
T4 |
9 |
9 |
0 |
0 |
T5 |
9 |
9 |
0 |
0 |
T15 |
9 |
9 |
0 |
0 |
T16 |
9 |
9 |
0 |
0 |
T17 |
9 |
9 |
0 |
0 |
T18 |
9 |
9 |
0 |
0 |
T19 |
9 |
9 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
202129200 |
200661858 |
0 |
0 |
T1 |
31581 |
31113 |
0 |
0 |
T2 |
46071 |
45468 |
0 |
0 |
T3 |
52623 |
51975 |
0 |
0 |
T4 |
89694 |
88848 |
0 |
0 |
T5 |
113724 |
112995 |
0 |
0 |
T15 |
8910 |
8424 |
0 |
0 |
T16 |
208773 |
208224 |
0 |
0 |
T17 |
56232 |
55764 |
0 |
0 |
T18 |
94815 |
94068 |
0 |
0 |
T19 |
93114 |
91503 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
202129200 |
200661858 |
0 |
0 |
T1 |
31581 |
31113 |
0 |
0 |
T2 |
46071 |
45468 |
0 |
0 |
T3 |
52623 |
51975 |
0 |
0 |
T4 |
89694 |
88848 |
0 |
0 |
T5 |
113724 |
112995 |
0 |
0 |
T15 |
8910 |
8424 |
0 |
0 |
T16 |
208773 |
208224 |
0 |
0 |
T17 |
56232 |
55764 |
0 |
0 |
T18 |
94815 |
94068 |
0 |
0 |
T19 |
93114 |
91503 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 3/3 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
878 |
878 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22458800 |
22295762 |
0 |
0 |
T1 |
3509 |
3457 |
0 |
0 |
T2 |
5119 |
5052 |
0 |
0 |
T3 |
5847 |
5775 |
0 |
0 |
T4 |
9966 |
9872 |
0 |
0 |
T5 |
12636 |
12555 |
0 |
0 |
T15 |
990 |
936 |
0 |
0 |
T16 |
23197 |
23136 |
0 |
0 |
T17 |
6248 |
6196 |
0 |
0 |
T18 |
10535 |
10452 |
0 |
0 |
T19 |
10346 |
10167 |
0 |
0 |