Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : keymgr_sideload_key
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sideload_ctrl.u_aes_key 95.83 100.00 87.50 100.00
tb.dut.u_sideload_ctrl.u_otbn_key 95.83 100.00 87.50 100.00
tb.dut.u_sideload_ctrl.u_kmac_key 95.83 100.00 87.50 100.00


Module Instance : tb.dut.u_sideload_ctrl.u_aes_key

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sideload_ctrl.u_otbn_key

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sideload_ctrl.u_kmac_key

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 87.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : keymgr_sideload_key
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
ALWAYS3366100.00
ALWAYS4388100.00


28                      
29         1/1            assign valid_o = valid_q & en_i;
           Tests:       T1 T2 T3 
30         1/1            assign key_o = key_q;
           Tests:       T1 T2 T3 
31                      
32                        always_ff @(posedge clk_i or negedge rst_ni) begin
33         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
34         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
35         1/1              end else if (!en_i || clr_i) begin
           Tests:       T1 T2 T3 
36         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
37         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
38         1/1                valid_q <= 1'b1;
           Tests:       T4 T5 T16 
39                          end
                        MISSING_ELSE
40                        end
41                      
42                        always_ff @(posedge clk_i or negedge rst_ni) begin
43         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
44         1/1                key_q <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
46         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T2 T3 T4 
47         1/1                  key_q[i] <= {EntropyCopies{entropy_i[i]}};
           Tests:       T2 T3 T4 
48                            end
49         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
50         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T4 T5 T16 
51         1/1                  key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
           Tests:       T4 T5 T16 
52                            end
53                          end
                        MISSING_ELSE
Cond Coverage for Module : keymgr_sideload_key ( parameter Width=256,EntropyCopies=8 )
Cond Coverage for Module self-instances :
SCORECOND
95.83 87.50
tb.dut.u_sideload_ctrl.u_aes_key

SCORECOND
95.83 87.50
tb.dut.u_sideload_ctrl.u_kmac_key

TotalCoveredPercent
Conditions8787.50
Logical8787.50
Non-Logical00
Event00

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T18,T38 

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3 

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---
-1-StatusTests
0CoveredT12,T13,T46
1CoveredT4,T18,T38
Cond Coverage for Module : keymgr_sideload_key ( parameter Width=384,EntropyCopies=12 )
Cond Coverage for Module self-instances :
SCORECOND
95.83 87.50
tb.dut.u_sideload_ctrl.u_otbn_key

TotalCoveredPercent
Conditions8787.50
Logical8787.50
Non-Logical00
Event00

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T16,T37 

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3 

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---
-1-StatusTests
0CoveredT47
1CoveredT5,T16,T37
Branch Coverage for Module : keymgr_sideload_key
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 33 4 4 100.00
IF 43 4 4 100.00 



33             if (!rst_ni) begin
               -1-  
34               valid_q <= 1'b0;
                 ==>
35             end else if (!en_i || clr_i) begin
                        -2-  
36               valid_q <= 1'b0;
                 ==>
37             end else if (set_i) begin
                        -3-  
38               valid_q <= 1'b1;
                 ==>
39             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T5,T16
0 0 0 Covered T1,T2,T3 



43             if (!rst_ni) begin
               -1-  
44               key_q <= '0;
                 ==>
45             end else if (clr_i) begin
                        -2-  
46               for (int i = 0; i < Shares; i++) begin
                 ==>
47                 key_q[i] <= {EntropyCopies{entropy_i[i]}};
48               end
49             end else if (set_i) begin
                        -3-  
50               for (int i = 0; i < Shares; i++) begin
                 ==>
51                 key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
52               end
53             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T4,T5,T16
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_aes_key
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
ALWAYS3366100.00
ALWAYS4388100.00


28                      
29         1/1            assign valid_o = valid_q & en_i;
           Tests:       T1 T2 T3 
30         1/1            assign key_o = key_q;
           Tests:       T1 T2 T3 
31                      
32                        always_ff @(posedge clk_i or negedge rst_ni) begin
33         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
34         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
35         1/1              end else if (!en_i || clr_i) begin
           Tests:       T1 T2 T3 
36         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
37         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
38         1/1                valid_q <= 1'b1;
           Tests:       T4 T18 T27 
39                          end
                        MISSING_ELSE
40                        end
41                      
42                        always_ff @(posedge clk_i or negedge rst_ni) begin
43         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
44         1/1                key_q <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
46         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T2 T3 T4 
47         1/1                  key_q[i] <= {EntropyCopies{entropy_i[i]}};
           Tests:       T2 T3 T4 
48                            end
49         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
50         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T4 T18 T27 
51         1/1                  key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
           Tests:       T4 T18 T27 
52                            end
53                          end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_sideload_ctrl.u_aes_key
TotalCoveredPercent
Conditions8787.50
Logical8787.50
Non-Logical00
Event00

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T18,T27 

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3 

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---
-1-StatusTests
0CoveredT12
1CoveredT4,T18,T27
Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_aes_key
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 33 4 4 100.00
IF 43 4 4 100.00 



33             if (!rst_ni) begin
               -1-  
34               valid_q <= 1'b0;
                 ==>
35             end else if (!en_i || clr_i) begin
                        -2-  
36               valid_q <= 1'b0;
                 ==>
37             end else if (set_i) begin
                        -3-  
38               valid_q <= 1'b1;
                 ==>
39             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T18,T27
0 0 0 Covered T1,T2,T3 



43             if (!rst_ni) begin
               -1-  
44               key_q <= '0;
                 ==>
45             end else if (clr_i) begin
                        -2-  
46               for (int i = 0; i < Shares; i++) begin
                 ==>
47                 key_q[i] <= {EntropyCopies{entropy_i[i]}};
48               end
49             end else if (set_i) begin
                        -3-  
50               for (int i = 0; i < Shares; i++) begin
                 ==>
51                 key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
52               end
53             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T4,T18,T27
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_otbn_key
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
ALWAYS3366100.00
ALWAYS4388100.00


28                      
29         1/1            assign valid_o = valid_q & en_i;
           Tests:       T1 T2 T3 
30         1/1            assign key_o = key_q;
           Tests:       T1 T2 T3 
31                      
32                        always_ff @(posedge clk_i or negedge rst_ni) begin
33         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
34         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
35         1/1              end else if (!en_i || clr_i) begin
           Tests:       T1 T2 T3 
36         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
37         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
38         1/1                valid_q <= 1'b1;
           Tests:       T5 T16 T37 
39                          end
                        MISSING_ELSE
40                        end
41                      
42                        always_ff @(posedge clk_i or negedge rst_ni) begin
43         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
44         1/1                key_q <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
46         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T2 T3 T4 
47         1/1                  key_q[i] <= {EntropyCopies{entropy_i[i]}};
           Tests:       T2 T3 T4 
48                            end
49         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
50         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T5 T16 T37 
51         1/1                  key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
           Tests:       T5 T16 T37 
52                            end
53                          end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_sideload_ctrl.u_otbn_key
TotalCoveredPercent
Conditions8787.50
Logical8787.50
Non-Logical00
Event00

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T16,T37 

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3 

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---
-1-StatusTests
0CoveredT47
1CoveredT5,T16,T37
Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_otbn_key
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 33 4 4 100.00
IF 43 4 4 100.00 



33             if (!rst_ni) begin
               -1-  
34               valid_q <= 1'b0;
                 ==>
35             end else if (!en_i || clr_i) begin
                        -2-  
36               valid_q <= 1'b0;
                 ==>
37             end else if (set_i) begin
                        -3-  
38               valid_q <= 1'b1;
                 ==>
39             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T5,T16,T37
0 0 0 Covered T1,T2,T3 



43             if (!rst_ni) begin
               -1-  
44               key_q <= '0;
                 ==>
45             end else if (clr_i) begin
                        -2-  
46               for (int i = 0; i < Shares; i++) begin
                 ==>
47                 key_q[i] <= {EntropyCopies{entropy_i[i]}};
48               end
49             end else if (set_i) begin
                        -3-  
50               for (int i = 0; i < Shares; i++) begin
                 ==>
51                 key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
52               end
53             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T5,T16,T37
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_kmac_key
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
ALWAYS3366100.00
ALWAYS4388100.00


28                      
29         1/1            assign valid_o = valid_q & en_i;
           Tests:       T1 T2 T3 
30         1/1            assign key_o = key_q;
           Tests:       T1 T2 T3 
31                      
32                        always_ff @(posedge clk_i or negedge rst_ni) begin
33         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
34         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
35         1/1              end else if (!en_i || clr_i) begin
           Tests:       T1 T2 T3 
36         1/1                valid_q <= 1'b0;
           Tests:       T1 T2 T3 
37         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
38         1/1                valid_q <= 1'b1;
           Tests:       T18 T38 T48 
39                          end
                        MISSING_ELSE
40                        end
41                      
42                        always_ff @(posedge clk_i or negedge rst_ni) begin
43         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
44         1/1                key_q <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
46         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T2 T3 T4 
47         1/1                  key_q[i] <= {EntropyCopies{entropy_i[i]}};
           Tests:       T2 T3 T4 
48                            end
49         1/1              end else if (set_i) begin
           Tests:       T1 T2 T3 
50         1/1                for (int i = 0; i < Shares; i++) begin
           Tests:       T18 T38 T48 
51         1/1                  key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
           Tests:       T18 T38 T48 
52                            end
53                          end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_sideload_ctrl.u_kmac_key
TotalCoveredPercent
Conditions8787.50
Logical8787.50
Non-Logical00
Event00

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT18,T38,T48 

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3 

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---
-1-StatusTests
0CoveredT12,T13,T46
1CoveredT18,T38,T48
Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_kmac_key
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 33 4 4 100.00
IF 43 4 4 100.00 



33             if (!rst_ni) begin
               -1-  
34               valid_q <= 1'b0;
                 ==>
35             end else if (!en_i || clr_i) begin
                        -2-  
36               valid_q <= 1'b0;
                 ==>
37             end else if (set_i) begin
                        -3-  
38               valid_q <= 1'b1;
                 ==>
39             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T38,T48
0 0 0 Covered T1,T2,T3 



43             if (!rst_ni) begin
               -1-  
44               key_q <= '0;
                 ==>
45             end else if (clr_i) begin
                        -2-  
46               for (int i = 0; i < Shares; i++) begin
                 ==>
47                 key_q[i] <= {EntropyCopies{entropy_i[i]}};
48               end
49             end else if (set_i) begin
                        -3-  
50               for (int i = 0; i < Shares; i++) begin
                 ==>
51                 key_q[i] <= set_en_i ? key_i[i] : {EntropyCopies{entropy_i[i]}};
52               end
53             end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T18,T38,T48
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%