Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2991667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

613806

1

T1

155

T2

400

T3

430

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3191233	1			T1	499		T2	442		T3	431
values[0x0]	205669	1			T1	42		T2	173		T3	178
values[0x1]	208571	1			T1	39		T2	195		T3	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2053825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1551648

1

T1

279

T2

503

T3

496

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11506	1			T2	7		T3	2		T4	9
valid_sources[0x01]	11772	1			T1	1		T3	1		T15	2
valid_sources[0x02]	11521	1			T1	2		T3	3		T15	2
valid_sources[0x03]	13827	1			T1	3		T3	1		T4	7
valid_sources[0x04]	11950	1			T1	5		T3	2		T15	1
valid_sources[0x05]	11841	1			T1	3		T2	2		T3	2
valid_sources[0x06]	11704	1			T1	5		T3	2		T19	2
valid_sources[0x07]	11956	1			T1	2		T2	9		T3	5
valid_sources[0x08]	12115	1			T1	3		T2	1		T3	5
valid_sources[0x09]	12540	1			T1	1		T3	3		T4	8
valid_sources[0x0a]	13929	1			T1	1		T15	3		T19	5
valid_sources[0x0b]	31619	1			T3	1		T4	15		T15	6
valid_sources[0x0c]	12232	1			T1	4		T2	2		T3	4
valid_sources[0x0d]	14950	1			T1	5		T3	2		T5	4
valid_sources[0x0e]	19040	1			T1	2		T2	4		T3	6
valid_sources[0x0f]	18780	1			T1	2		T3	6		T15	7
valid_sources[0x10]	22559	1			T1	1		T2	3		T3	2
valid_sources[0x11]	11042	1			T1	2		T3	6		T15	5
valid_sources[0x12]	23630	1			T1	2		T2	7		T3	1
valid_sources[0x13]	26034	1			T1	2		T3	1		T19	3
valid_sources[0x14]	34844	1			T3	6		T5	20		T19	3
valid_sources[0x15]	13651	1			T1	5		T2	2		T3	1
valid_sources[0x16]	22642	1			T1	4		T2	4		T3	3
valid_sources[0x17]	11185	1			T1	3		T2	12		T3	3
valid_sources[0x18]	12699	1			T1	3		T2	5		T3	7
valid_sources[0x19]	10892	1			T1	2		T2	1		T3	8
valid_sources[0x1a]	13511	1			T1	6		T3	1		T4	8
valid_sources[0x1b]	19349	1			T1	2		T2	2		T3	3
valid_sources[0x1c]	12331	1			T1	2		T2	4		T3	1
valid_sources[0x1d]	12384	1			T1	1		T2	9		T3	5
valid_sources[0x1e]	17118	1			T1	6		T3	2		T15	2
valid_sources[0x1f]	11394	1			T1	3		T2	8		T3	1
valid_sources[0x20]	13766	1			T1	2		T3	3		T15	2
valid_sources[0x21]	11820	1			T1	2		T3	3		T4	6
valid_sources[0x22]	12890	1			T1	2		T2	6		T3	8
valid_sources[0x23]	11770	1			T1	2		T2	1		T3	1
valid_sources[0x24]	11401	1			T2	2		T3	7		T19	1
valid_sources[0x25]	10625	1			T3	3		T15	6		T17	7
valid_sources[0x26]	11494	1			T1	2		T3	1		T4	3
valid_sources[0x27]	23117	1			T1	4		T3	3		T15	2
valid_sources[0x28]	11442	1			T1	6		T3	5		T4	8
valid_sources[0x29]	11295	1			T1	4		T2	2		T3	4
valid_sources[0x2a]	12304	1			T1	3		T2	1		T3	10
valid_sources[0x2b]	11614	1			T1	3		T2	13		T3	1
valid_sources[0x2c]	12301	1			T1	3		T2	2		T3	3
valid_sources[0x2d]	11838	1			T3	1		T19	3		T34	2
valid_sources[0x2e]	11826	1			T1	5		T2	2		T3	4
valid_sources[0x2f]	11083	1			T1	5		T3	2		T15	6
valid_sources[0x30]	15480	1			T1	1		T2	7		T3	3
valid_sources[0x31]	11175	1			T1	1		T3	3		T5	3
valid_sources[0x32]	12712	1			T1	5		T2	7		T3	5
valid_sources[0x33]	12683	1			T1	4		T3	3		T15	7
valid_sources[0x34]	17393	1			T1	3		T2	1		T3	2
valid_sources[0x35]	12184	1			T1	4		T3	10		T19	7
valid_sources[0x36]	13562	1			T1	1		T3	1		T19	3
valid_sources[0x37]	11831	1			T1	2		T2	1		T3	5
valid_sources[0x38]	12759	1			T1	2		T2	13		T3	4
valid_sources[0x39]	11045	1			T1	1		T2	6		T3	3
valid_sources[0x3a]	11187	1			T1	2		T2	8		T3	2
valid_sources[0x3b]	13563	1			T1	3		T2	10		T3	1
valid_sources[0x3c]	11411	1			T1	6		T2	1		T3	1
valid_sources[0x3d]	10790	1			T1	4		T3	2		T15	2
valid_sources[0x3e]	10824	1			T1	1		T2	6		T3	6
valid_sources[0x3f]	11379	1			T1	2		T2	6		T3	3
valid_sources[0x40]	13784	1			T1	1		T2	12		T15	3
valid_sources[0x41]	21821	1			T1	4		T3	1		T15	2
valid_sources[0x42]	11272	1			T1	1		T3	8		T5	24
valid_sources[0x43]	11173	1			T1	3		T15	5		T19	4
valid_sources[0x44]	11677	1			T1	1		T2	2		T5	6
valid_sources[0x45]	11624	1			T1	1		T2	4		T15	5
valid_sources[0x46]	13068	1			T1	2		T2	3		T3	2
valid_sources[0x47]	11742	1			T1	1		T2	6		T3	1
valid_sources[0x48]	11375	1			T1	3		T2	2		T3	5
valid_sources[0x49]	12844	1			T3	6		T15	4		T19	2
valid_sources[0x4a]	12409	1			T1	1		T3	8		T4	3
valid_sources[0x4b]	15435	1			T1	4		T3	4		T15	4
valid_sources[0x4c]	14616	1			T1	3		T2	4		T3	2
valid_sources[0x4d]	12150	1			T1	1		T3	5		T19	4
valid_sources[0x4e]	16853	1			T1	1		T2	3		T3	1
valid_sources[0x4f]	12579	1			T1	2		T2	2		T3	1
valid_sources[0x50]	11039	1			T1	1		T3	1		T4	4
valid_sources[0x51]	13397	1			T1	3		T3	3		T4	6
valid_sources[0x52]	12773	1			T1	1		T2	15		T3	1
valid_sources[0x53]	11429	1			T1	1		T3	1		T4	3
valid_sources[0x54]	11194	1			T1	2		T2	7		T3	3
valid_sources[0x55]	14441	1			T3	2		T15	10		T19	3
valid_sources[0x56]	13701	1			T2	2		T3	4		T4	16
valid_sources[0x57]	10822	1			T2	6		T3	3		T4	2
valid_sources[0x58]	11048	1			T1	3		T2	6		T3	3
valid_sources[0x59]	13714	1			T1	4		T2	8		T3	5
valid_sources[0x5a]	13023	1			T1	1		T4	7		T15	4
valid_sources[0x5b]	12223	1			T1	2		T2	11		T3	4
valid_sources[0x5c]	15710	1			T1	2		T3	1		T5	40
valid_sources[0x5d]	11132	1			T1	5		T2	1		T3	5
valid_sources[0x5e]	21809	1			T1	1		T2	5		T3	4
valid_sources[0x5f]	11194	1			T1	2		T5	3		T19	6
valid_sources[0x60]	11694	1			T1	3		T2	3		T3	5
valid_sources[0x61]	11080	1			T1	1		T15	3		T19	2
valid_sources[0x62]	11256	1			T1	2		T2	4		T3	9
valid_sources[0x63]	12344	1			T1	1		T2	10		T3	2
valid_sources[0x64]	12078	1			T1	3		T2	1		T3	4
valid_sources[0x65]	11933	1			T1	3		T3	6		T15	4
valid_sources[0x66]	11901	1			T1	2		T3	3		T4	1
valid_sources[0x67]	13943	1			T1	3		T3	2		T15	4
valid_sources[0x68]	14011	1			T1	1		T2	15		T3	4
valid_sources[0x69]	13346	1			T1	1		T2	1		T3	3
valid_sources[0x6a]	11464	1			T1	1		T3	4		T19	1
valid_sources[0x6b]	11509	1			T1	3		T2	4		T3	3
valid_sources[0x6c]	12787	1			T1	2		T2	6		T3	2
valid_sources[0x6d]	11414	1			T1	2		T2	13		T3	1
valid_sources[0x6e]	14219	1			T1	1		T3	3		T4	12
valid_sources[0x6f]	11606	1			T1	4		T2	12		T3	1
valid_sources[0x70]	11475	1			T1	4		T3	6		T4	5
valid_sources[0x71]	12639	1			T1	4		T3	5		T4	3
valid_sources[0x72]	15128	1			T1	3		T2	7		T3	1
valid_sources[0x73]	35925	1			T1	1		T2	1		T3	2
valid_sources[0x74]	12320	1			T1	3		T3	2		T15	2
valid_sources[0x75]	12707	1			T1	2		T2	9		T3	4
valid_sources[0x76]	12141	1			T1	1		T3	2		T4	6
valid_sources[0x77]	11205	1			T3	8		T15	2		T19	1
valid_sources[0x78]	12033	1			T3	8		T4	3		T19	7
valid_sources[0x79]	11335	1			T1	3		T2	1		T3	5
valid_sources[0x7a]	11366	1			T1	1		T3	2		T4	1
valid_sources[0x7b]	11680	1			T1	3		T2	6		T3	4
valid_sources[0x7c]	11926	1			T2	9		T3	2		T4	5
valid_sources[0x7d]	11946	1			T1	2		T3	1		T15	2
valid_sources[0x7e]	23820	1			T1	1		T2	6		T3	2
valid_sources[0x7f]	14182	1			T1	1		T3	4		T15	4
valid_sources[0x80]	17414	1			T1	2		T3	2		T4	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333718

1

T1

131

T2

187

T3

199

values[0x0]

all_enables

biggest_size

147522

1

T1

16

T2

109

T3

124

values[0x1]

all_enables

biggest_size

132566

1

T1

8

T2

104

T3

107