Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23881912	18337	0	0
attest_sw_binding_0_rd_A	23881912	1700	0	0
attest_sw_binding_1_rd_A	23881912	1679	0	0
attest_sw_binding_2_rd_A	23881912	1706	0	0
attest_sw_binding_3_rd_A	23881912	1593	0	0
attest_sw_binding_4_rd_A	23881912	1669	0	0
attest_sw_binding_5_rd_A	23881912	1642	0	0
attest_sw_binding_6_rd_A	23881912	1812	0	0
attest_sw_binding_7_rd_A	23881912	1784	0	0
intr_enable_rd_A	23881912	2311	0	0
key_version_rd_A	23881912	1639	0	0
max_creator_key_ver_regwen_rd_A	23881912	1589	0	0
max_owner_int_key_ver_regwen_rd_A	23881912	1765	0	0
max_owner_key_ver_regwen_rd_A	23881912	1663	0	0
reseed_interval_regwen_rd_A	23881912	1694	0	0
salt_0_rd_A	23881912	1561	0	0
salt_1_rd_A	23881912	1742	0	0
salt_2_rd_A	23881912	1671	0	0
salt_3_rd_A	23881912	1658	0	0
salt_4_rd_A	23881912	1673	0	0
salt_5_rd_A	23881912	1699	0	0
salt_6_rd_A	23881912	1668	0	0
salt_7_rd_A	23881912	1624	0	0
sealing_sw_binding_0_rd_A	23881912	1638	0	0
sealing_sw_binding_1_rd_A	23881912	1635	0	0
sealing_sw_binding_2_rd_A	23881912	1617	0	0
sealing_sw_binding_3_rd_A	23881912	1738	0	0
sealing_sw_binding_4_rd_A	23881912	1676	0	0
sealing_sw_binding_5_rd_A	23881912	1693	0	0
sealing_sw_binding_6_rd_A	23881912	1638	0	0
sealing_sw_binding_7_rd_A	23881912	1610	0	0
sideload_clear_rd_A	23881912	1631	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	18337	0	0
T14	24238	0	0	0
T24	24264	0	0	0
T39	20292	1	0	0
T61	0	617	0	0
T64	0	798	0	0
T69	0	40	0	0
T84	0	59	0	0
T85	0	339	0	0
T86	0	150	0	0
T87	0	189	0	0
T88	0	214	0	0
T89	0	78	0	0
T99	58536	0	0	0
T100	4984	0	0	0
T101	33897	0	0	0
T102	33211	0	0	0
T103	6831	0	0	0
T104	15642	0	0	0
T105	3543	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1700	0	0
T84	26950	57	0	0
T86	0	21	0	0
T87	0	56	0	0
T88	0	48	0	0
T89	0	39	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	32	0	0
T185	0	25	0	0
T186	0	27	0	0
T187	0	20	0	0
T188	0	6	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1679	0	0
T84	26950	28	0	0
T86	0	55	0	0
T87	0	74	0	0
T88	0	31	0	0
T89	0	30	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	50	0	0
T185	0	13	0	0
T186	0	46	0	0
T187	0	20	0	0
T188	0	6	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1706	0	0
T84	26950	20	0	0
T86	0	25	0	0
T87	0	52	0	0
T88	0	19	0	0
T89	0	53	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	79	0	0
T185	0	14	0	0
T186	0	46	0	0
T187	0	24	0	0
T188	0	19	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1593	0	0
T84	26950	39	0	0
T86	0	30	0	0
T87	0	44	0	0
T88	0	28	0	0
T89	0	25	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	27	0	0
T185	0	11	0	0
T186	0	62	0	0
T187	0	21	0	0
T188	0	30	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1669	0	0
T84	26950	27	0	0
T86	0	30	0	0
T87	0	60	0	0
T88	0	34	0	0
T89	0	44	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	36	0	0
T185	0	24	0	0
T186	0	69	0	0
T187	0	19	0	0
T188	0	19	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1642	0	0
T84	26950	25	0	0
T86	0	22	0	0
T87	0	72	0	0
T88	0	18	0	0
T89	0	55	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	21	0	0
T185	0	18	0	0
T186	0	38	0	0
T187	0	32	0	0
T188	0	9	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1812	0	0
T84	26950	36	0	0
T86	0	64	0	0
T87	0	54	0	0
T88	0	32	0	0
T89	0	41	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	26	0	0
T185	0	22	0	0
T186	0	47	0	0
T187	0	14	0	0
T188	0	21	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1784	0	0
T84	26950	27	0	0
T86	0	38	0	0
T87	0	55	0	0
T88	0	16	0	0
T89	0	43	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	31	0	0
T185	0	27	0	0
T186	0	71	0	0
T187	0	26	0	0
T188	0	9	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	2311	0	0
T84	26950	62	0	0
T86	0	14	0	0
T87	0	45	0	0
T88	0	22	0	0
T89	0	34	0	0
T97	5284	0	0	0
T139	0	27	0	0
T142	0	7	0	0
T145	9049	0	0	0
T150	0	50	0	0
T185	0	31	0	0
T186	0	57	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1639	0	0
T84	26950	49	0	0
T86	0	43	0	0
T87	0	62	0	0
T88	0	29	0	0
T89	0	53	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	30	0	0
T185	0	20	0	0
T186	0	56	0	0
T187	0	6	0	0
T188	0	3	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1589	0	0
T84	26950	36	0	0
T86	0	32	0	0
T87	0	57	0	0
T88	0	34	0	0
T89	0	38	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	11	0	0
T185	0	26	0	0
T186	0	52	0	0
T187	0	25	0	0
T188	0	19	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1765	0	0
T84	26950	55	0	0
T86	0	32	0	0
T87	0	47	0	0
T88	0	25	0	0
T89	0	50	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	29	0	0
T185	0	16	0	0
T186	0	58	0	0
T187	0	32	0	0
T188	0	7	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1663	0	0
T84	26950	40	0	0
T86	0	25	0	0
T87	0	52	0	0
T88	0	39	0	0
T89	0	38	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	34	0	0
T185	0	23	0	0
T186	0	42	0	0
T187	0	17	0	0
T188	0	21	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1694	0	0
T84	26950	25	0	0
T86	0	32	0	0
T87	0	86	0	0
T88	0	21	0	0
T89	0	63	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	27	0	0
T185	0	25	0	0
T186	0	50	0	0
T187	0	25	0	0
T188	0	30	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1561	0	0
T84	26950	30	0	0
T86	0	30	0	0
T87	0	65	0	0
T88	0	30	0	0
T89	0	51	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	30	0	0
T185	0	9	0	0
T186	0	60	0	0
T187	0	28	0	0
T188	0	18	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1742	0	0
T84	26950	38	0	0
T86	0	35	0	0
T87	0	65	0	0
T88	0	28	0	0
T89	0	49	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	53	0	0
T185	0	42	0	0
T186	0	46	0	0
T187	0	14	0	0
T188	0	39	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1671	0	0
T84	26950	46	0	0
T86	0	19	0	0
T87	0	58	0	0
T88	0	20	0	0
T89	0	31	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	36	0	0
T185	0	26	0	0
T186	0	35	0	0
T187	0	20	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0
T196	0	5	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1658	0	0
T84	26950	13	0	0
T86	0	41	0	0
T87	0	58	0	0
T88	0	38	0	0
T89	0	57	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	40	0	0
T185	0	13	0	0
T186	0	56	0	0
T187	0	52	0	0
T188	0	24	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1673	0	0
T84	26950	31	0	0
T86	0	26	0	0
T87	0	49	0	0
T88	0	37	0	0
T89	0	39	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	26	0	0
T185	0	30	0	0
T186	0	63	0	0
T187	0	41	0	0
T188	0	16	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1699	0	0
T84	26950	29	0	0
T86	0	16	0	0
T87	0	33	0	0
T88	0	39	0	0
T89	0	85	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	34	0	0
T185	0	18	0	0
T186	0	62	0	0
T187	0	38	0	0
T188	0	28	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1668	0	0
T84	26950	46	0	0
T86	0	46	0	0
T87	0	60	0	0
T88	0	38	0	0
T89	0	59	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	34	0	0
T185	0	22	0	0
T186	0	42	0	0
T187	0	14	0	0
T188	0	12	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1624	0	0
T84	26950	41	0	0
T86	0	28	0	0
T87	0	54	0	0
T88	0	31	0	0
T89	0	38	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	34	0	0
T185	0	27	0	0
T186	0	33	0	0
T187	0	37	0	0
T188	0	20	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1638	0	0
T84	26950	19	0	0
T86	0	29	0	0
T87	0	48	0	0
T88	0	17	0	0
T89	0	34	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	46	0	0
T185	0	29	0	0
T186	0	55	0	0
T187	0	30	0	0
T188	0	24	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1635	0	0
T84	26950	26	0	0
T86	0	20	0	0
T87	0	55	0	0
T88	0	26	0	0
T89	0	32	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	55	0	0
T185	0	21	0	0
T186	0	59	0	0
T187	0	25	0	0
T188	0	19	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1617	0	0
T84	26950	14	0	0
T86	0	50	0	0
T87	0	36	0	0
T88	0	36	0	0
T89	0	50	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	43	0	0
T185	0	20	0	0
T186	0	60	0	0
T187	0	13	0	0
T188	0	16	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1738	0	0
T84	26950	27	0	0
T86	0	31	0	0
T87	0	110	0	0
T88	0	44	0	0
T89	0	39	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	33	0	0
T185	0	11	0	0
T186	0	65	0	0
T187	0	19	0	0
T188	0	16	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1676	0	0
T84	26950	31	0	0
T86	0	37	0	0
T87	0	78	0	0
T88	0	36	0	0
T89	0	50	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	18	0	0
T185	0	37	0	0
T186	0	44	0	0
T187	0	29	0	0
T188	0	6	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1693	0	0
T84	26950	26	0	0
T86	0	15	0	0
T87	0	74	0	0
T88	0	40	0	0
T89	0	47	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	54	0	0
T185	0	32	0	0
T186	0	40	0	0
T187	0	33	0	0
T188	0	2	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1638	0	0
T84	26950	31	0	0
T86	0	30	0	0
T87	0	50	0	0
T88	0	37	0	0
T89	0	23	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	30	0	0
T185	0	31	0	0
T186	0	50	0	0
T187	0	27	0	0
T188	0	18	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1610	0	0
T84	26950	31	0	0
T86	0	35	0	0
T87	0	62	0	0
T88	0	24	0	0
T89	0	67	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	27	0	0
T185	0	15	0	0
T186	0	51	0	0
T187	0	32	0	0
T188	0	18	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23881912	1631	0	0
T84	26950	44	0	0
T86	0	28	0	0
T87	0	78	0	0
T88	0	19	0	0
T89	0	44	0	0
T97	5284	0	0	0
T145	9049	0	0	0
T150	0	36	0	0
T185	0	22	0	0
T186	0	64	0	0
T187	0	22	0	0
T188	0	5	0	0
T189	44160	0	0	0
T190	31347	0	0	0
T191	32011	0	0	0
T192	5993	0	0	0
T193	6637	0	0	0
T194	10413	0	0	0
T195	4786	0	0	0