Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.04 98.19 98.53 100.00 99.02 98.63 91.22


Total test records in report: 1088
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1008 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.441978642 Sep 09 10:23:31 PM UTC 24 Sep 09 10:23:33 PM UTC 24 49544730 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.1431004921 Sep 09 10:23:31 PM UTC 24 Sep 09 10:23:33 PM UTC 24 12832391 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2520589455 Sep 09 10:23:26 PM UTC 24 Sep 09 10:23:33 PM UTC 24 2189839438 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2095923135 Sep 09 10:23:31 PM UTC 24 Sep 09 10:23:33 PM UTC 24 34571048 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.504084354 Sep 09 10:23:29 PM UTC 24 Sep 09 10:23:34 PM UTC 24 947058650 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.3671578348 Sep 09 10:23:28 PM UTC 24 Sep 09 10:23:34 PM UTC 24 108628438 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.1603253978 Sep 09 10:23:26 PM UTC 24 Sep 09 10:23:34 PM UTC 24 1320724303 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.875291122 Sep 09 10:23:31 PM UTC 24 Sep 09 10:23:34 PM UTC 24 62566560 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2444581281 Sep 09 10:23:27 PM UTC 24 Sep 09 10:23:35 PM UTC 24 738243509 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.1257746273 Sep 09 10:23:29 PM UTC 24 Sep 09 10:23:36 PM UTC 24 190439769 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.4014618109 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:36 PM UTC 24 21139824 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1678728340 Sep 09 10:23:32 PM UTC 24 Sep 09 10:23:37 PM UTC 24 186646085 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.260286319 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:37 PM UTC 24 14842446 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.174045360 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:37 PM UTC 24 25052708 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.836402043 Sep 09 10:23:32 PM UTC 24 Sep 09 10:23:37 PM UTC 24 128164640 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.369581482 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:38 PM UTC 24 72463152 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1599409164 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:38 PM UTC 24 133115485 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.253840009 Sep 09 10:23:36 PM UTC 24 Sep 09 10:23:38 PM UTC 24 173314838 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.217279677 Sep 09 10:23:36 PM UTC 24 Sep 09 10:23:38 PM UTC 24 36697024 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3197840375 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:38 PM UTC 24 40191241 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1411141414 Sep 09 10:23:32 PM UTC 24 Sep 09 10:23:38 PM UTC 24 615257075 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3000799729 Sep 09 10:23:36 PM UTC 24 Sep 09 10:23:39 PM UTC 24 160133519 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2766830834 Sep 09 10:23:36 PM UTC 24 Sep 09 10:23:39 PM UTC 24 75742760 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1770292089 Sep 09 10:23:29 PM UTC 24 Sep 09 10:23:39 PM UTC 24 201166429 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.3819046166 Sep 09 10:23:36 PM UTC 24 Sep 09 10:23:40 PM UTC 24 197843826 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1361793372 Sep 09 10:23:34 PM UTC 24 Sep 09 10:23:40 PM UTC 24 355693354 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3287895250 Sep 09 10:23:39 PM UTC 24 Sep 09 10:23:41 PM UTC 24 19288933 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1682415294 Sep 09 10:23:39 PM UTC 24 Sep 09 10:23:42 PM UTC 24 65602713 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.535676437 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:42 PM UTC 24 9197291 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1037145973 Sep 09 10:23:37 PM UTC 24 Sep 09 10:23:42 PM UTC 24 107516049 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1214181185 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:43 PM UTC 24 498744592 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1632988131 Sep 09 10:23:38 PM UTC 24 Sep 09 10:23:43 PM UTC 24 557979216 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.405465329 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:44 PM UTC 24 101581212 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3275510212 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:44 PM UTC 24 389264373 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2890846954 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:44 PM UTC 24 30988923 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.3639045116 Sep 09 10:23:41 PM UTC 24 Sep 09 10:23:44 PM UTC 24 175237020 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2695214113 Sep 09 10:23:41 PM UTC 24 Sep 09 10:23:44 PM UTC 24 114604486 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2184194954 Sep 09 10:23:41 PM UTC 24 Sep 09 10:23:45 PM UTC 24 49749116 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.706073524 Sep 09 10:23:42 PM UTC 24 Sep 09 10:23:45 PM UTC 24 255550979 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1951393970 Sep 09 10:23:43 PM UTC 24 Sep 09 10:23:45 PM UTC 24 15921971 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2337513364 Sep 09 10:23:43 PM UTC 24 Sep 09 10:23:46 PM UTC 24 136018074 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1472798719 Sep 09 10:23:38 PM UTC 24 Sep 09 10:23:46 PM UTC 24 724157388 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4080652489 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:46 PM UTC 24 86018678 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3598172682 Sep 09 10:23:42 PM UTC 24 Sep 09 10:23:47 PM UTC 24 103152673 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.244258374 Sep 09 10:23:42 PM UTC 24 Sep 09 10:23:47 PM UTC 24 50338678 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3522983323 Sep 09 10:23:43 PM UTC 24 Sep 09 10:23:47 PM UTC 24 36221155 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3542240688 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:47 PM UTC 24 16031478 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.284645593 Sep 09 10:23:43 PM UTC 24 Sep 09 10:23:48 PM UTC 24 54160723 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.4244118994 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:48 PM UTC 24 152081277 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3702414443 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:48 PM UTC 24 27558430 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1639393956 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:49 PM UTC 24 24832331 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.4081382970 Sep 09 10:23:47 PM UTC 24 Sep 09 10:23:49 PM UTC 24 7983222 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.2640399161 Sep 09 10:23:47 PM UTC 24 Sep 09 10:23:49 PM UTC 24 16408106 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.243583651 Sep 09 10:23:47 PM UTC 24 Sep 09 10:23:49 PM UTC 24 38278173 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3744337865 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:49 PM UTC 24 179243690 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.222947605 Sep 09 10:23:47 PM UTC 24 Sep 09 10:23:49 PM UTC 24 23919892 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3159128243 Sep 09 10:23:32 PM UTC 24 Sep 09 10:23:49 PM UTC 24 424450892 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.895589005 Sep 09 10:23:47 PM UTC 24 Sep 09 10:23:49 PM UTC 24 55800868 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2898582369 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:49 PM UTC 24 166962551 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1488218472 Sep 09 10:23:40 PM UTC 24 Sep 09 10:23:50 PM UTC 24 495209718 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.3194994898 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:50 PM UTC 24 9757910 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.2156311285 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:51 PM UTC 24 20542778 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1704534816 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:51 PM UTC 24 22085459 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1580019845 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:51 PM UTC 24 27046751 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.4020707879 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:51 PM UTC 24 11997619 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.4033758051 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:51 PM UTC 24 26705091 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.567487037 Sep 09 10:23:49 PM UTC 24 Sep 09 10:23:51 PM UTC 24 35302766 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.607022751 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:51 PM UTC 24 339525242 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.723330862 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 62567895 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.234442968 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 59194733 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3125847517 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 9759889 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.3787730820 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 10632038 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.194677462 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 93986697 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.380333680 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 34731962 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2400894612 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:53 PM UTC 24 26537997 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.96966800 Sep 09 10:23:52 PM UTC 24 Sep 09 10:23:53 PM UTC 24 10190762 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.4246443253 Sep 09 10:23:51 PM UTC 24 Sep 09 10:23:54 PM UTC 24 59193251 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2121689578 Sep 09 10:23:52 PM UTC 24 Sep 09 10:23:54 PM UTC 24 39143548 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3256148334 Sep 09 10:23:52 PM UTC 24 Sep 09 10:23:54 PM UTC 24 25601689 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1342328922 Sep 09 10:23:52 PM UTC 24 Sep 09 10:23:54 PM UTC 24 9489985 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.289664871 Sep 09 10:23:52 PM UTC 24 Sep 09 10:23:54 PM UTC 24 47226005 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2053318983 Sep 09 10:23:45 PM UTC 24 Sep 09 10:23:55 PM UTC 24 151115953 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1765434295 Sep 09 10:23:54 PM UTC 24 Sep 09 10:23:55 PM UTC 24 15044008 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.2795995491 Sep 09 10:23:54 PM UTC 24 Sep 09 10:23:56 PM UTC 24 35591479 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.1981900806 Sep 09 10:23:54 PM UTC 24 Sep 09 10:23:56 PM UTC 24 30461513 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.2885060996 Sep 09 10:23:54 PM UTC 24 Sep 09 10:23:56 PM UTC 24 34988144 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.2278315666 Sep 09 10:23:54 PM UTC 24 Sep 09 10:23:56 PM UTC 24 47156647 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.981214546 Sep 09 10:23:54 PM UTC 24 Sep 09 10:23:56 PM UTC 24 13288008 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.3268886008
Short name T15
Test name
Test status
Simulation time 48790583 ps
CPU time 3.31 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:44 PM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268886008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3268886008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.1599936682
Short name T111
Test name
Test status
Simulation time 12042026232 ps
CPU time 69.19 seconds
Started Sep 09 09:04:42 PM UTC 24
Finished Sep 09 09:05:53 PM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599936682 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1599936682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.712485168
Short name T20
Test name
Test status
Simulation time 227761227 ps
CPU time 5.38 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:46 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712485168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.712485168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.3697823978
Short name T86
Test name
Test status
Simulation time 2188835729 ps
CPU time 22.32 seconds
Started Sep 09 09:06:06 PM UTC 24
Finished Sep 09 09:06:30 PM UTC 24
Peak memory 230908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3697823978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg
r_stress_all_with_rand_reset.3697823978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.907180142
Short name T12
Test name
Test status
Simulation time 2418589652 ps
CPU time 13.68 seconds
Started Sep 09 09:04:43 PM UTC 24
Finished Sep 09 09:04:58 PM UTC 24
Peak memory 252628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907180142 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.907180142
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.1045160948
Short name T132
Test name
Test status
Simulation time 328479096 ps
CPU time 19.07 seconds
Started Sep 09 09:05:25 PM UTC 24
Finished Sep 09 09:05:45 PM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045160948 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1045160948
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.620219126
Short name T139
Test name
Test status
Simulation time 3112552657 ps
CPU time 58.56 seconds
Started Sep 09 09:05:10 PM UTC 24
Finished Sep 09 09:06:10 PM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620219126 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.620219126
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.3029982784
Short name T108
Test name
Test status
Simulation time 203327348 ps
CPU time 10.29 seconds
Started Sep 09 09:05:14 PM UTC 24
Finished Sep 09 09:05:25 PM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029982784 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3029982784
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.2606813048
Short name T35
Test name
Test status
Simulation time 464318011 ps
CPU time 3.65 seconds
Started Sep 09 09:04:47 PM UTC 24
Finished Sep 09 09:04:52 PM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606813048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2606813048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.2768713887
Short name T3
Test name
Test status
Simulation time 265683974 ps
CPU time 2.63 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:44 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768713887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2768713887
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.624605744
Short name T61
Test name
Test status
Simulation time 189671732 ps
CPU time 16.4 seconds
Started Sep 09 09:04:59 PM UTC 24
Finished Sep 09 09:05:17 PM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=624605744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_
stress_all_with_rand_reset.624605744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.833977509
Short name T9
Test name
Test status
Simulation time 385089729 ps
CPU time 5.98 seconds
Started Sep 09 09:05:58 PM UTC 24
Finished Sep 09 09:06:05 PM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833977509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.833977509
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.315752390
Short name T73
Test name
Test status
Simulation time 1226501738 ps
CPU time 10.72 seconds
Started Sep 09 10:22:39 PM UTC 24
Finished Sep 09 10:22:51 PM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315752390 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.315752390
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.3865814467
Short name T75
Test name
Test status
Simulation time 32609759 ps
CPU time 3.78 seconds
Started Sep 09 09:04:46 PM UTC 24
Finished Sep 09 09:04:51 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865814467 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3865814467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.439938139
Short name T291
Test name
Test status
Simulation time 2278337178 ps
CPU time 111.97 seconds
Started Sep 09 09:06:52 PM UTC 24
Finished Sep 09 09:08:46 PM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439938139 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.439938139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.3018907705
Short name T24
Test name
Test status
Simulation time 495191028 ps
CPU time 9.02 seconds
Started Sep 09 09:04:55 PM UTC 24
Finished Sep 09 09:05:06 PM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018907705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3018907705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.916983290
Short name T427
Test name
Test status
Simulation time 1009301590 ps
CPU time 29.01 seconds
Started Sep 09 09:07:46 PM UTC 24
Finished Sep 09 09:08:17 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916983290 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.916983290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.4137891784
Short name T281
Test name
Test status
Simulation time 90793164 ps
CPU time 3.77 seconds
Started Sep 09 09:05:29 PM UTC 24
Finished Sep 09 09:05:34 PM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137891784 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4137891784
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.3868627421
Short name T36
Test name
Test status
Simulation time 685643681 ps
CPU time 4.44 seconds
Started Sep 09 09:04:41 PM UTC 24
Finished Sep 09 09:04:47 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868627421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3868627421
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3362428207
Short name T79
Test name
Test status
Simulation time 155395352 ps
CPU time 5.57 seconds
Started Sep 09 10:23:01 PM UTC 24
Finished Sep 09 10:23:07 PM UTC 24
Peak memory 226688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362428207 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.3362428207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.1419013383
Short name T76
Test name
Test status
Simulation time 2530806758 ps
CPU time 15.49 seconds
Started Sep 09 09:04:53 PM UTC 24
Finished Sep 09 09:05:10 PM UTC 24
Peak memory 232312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419013383 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1419013383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.1144825061
Short name T428
Test name
Test status
Simulation time 700323637 ps
CPU time 10.78 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:45 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144825061 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1144825061
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.1046434715
Short name T21
Test name
Test status
Simulation time 122266255 ps
CPU time 4.24 seconds
Started Sep 09 09:04:47 PM UTC 24
Finished Sep 09 09:04:52 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046434715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1046434715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.3239537971
Short name T51
Test name
Test status
Simulation time 854634374 ps
CPU time 7.27 seconds
Started Sep 09 09:08:03 PM UTC 24
Finished Sep 09 09:08:11 PM UTC 24
Peak memory 232508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239537971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3239537971
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.1762577451
Short name T333
Test name
Test status
Simulation time 2010227855 ps
CPU time 94.34 seconds
Started Sep 09 09:06:36 PM UTC 24
Finished Sep 09 09:08:13 PM UTC 24
Peak memory 224396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762577451 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1762577451
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.352421134
Short name T109
Test name
Test status
Simulation time 107797433 ps
CPU time 3.86 seconds
Started Sep 09 09:05:22 PM UTC 24
Finished Sep 09 09:05:27 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352421134 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.352421134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.4011141874
Short name T221
Test name
Test status
Simulation time 9890814891 ps
CPU time 41.9 seconds
Started Sep 09 09:07:07 PM UTC 24
Finished Sep 09 09:07:50 PM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011141874 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4011141874
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.920489800
Short name T119
Test name
Test status
Simulation time 147964071 ps
CPU time 3.64 seconds
Started Sep 09 09:06:46 PM UTC 24
Finished Sep 09 09:06:51 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920489800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.920489800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.3144457948
Short name T289
Test name
Test status
Simulation time 448426770 ps
CPU time 3.1 seconds
Started Sep 09 09:05:25 PM UTC 24
Finished Sep 09 09:05:29 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144457948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3144457948
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.1796344725
Short name T32
Test name
Test status
Simulation time 1410238804 ps
CPU time 21.54 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:47 PM UTC 24
Peak memory 228500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796344725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1796344725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.958939512
Short name T142
Test name
Test status
Simulation time 6072950722 ps
CPU time 66.55 seconds
Started Sep 09 09:05:17 PM UTC 24
Finished Sep 09 09:06:26 PM UTC 24
Peak memory 232284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958939512 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.958939512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3269326188
Short name T70
Test name
Test status
Simulation time 47480714 ps
CPU time 3.05 seconds
Started Sep 09 09:05:33 PM UTC 24
Finished Sep 09 09:05:37 PM UTC 24
Peak memory 219968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269326188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3269326188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.1550231634
Short name T23
Test name
Test status
Simulation time 3701619513 ps
CPU time 9.82 seconds
Started Sep 09 09:05:46 PM UTC 24
Finished Sep 09 09:05:57 PM UTC 24
Peak memory 232604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550231634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1550231634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.561078953
Short name T430
Test name
Test status
Simulation time 929605791 ps
CPU time 9.27 seconds
Started Sep 09 09:07:56 PM UTC 24
Finished Sep 09 09:08:06 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561078953 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.561078953
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.2715997118
Short name T253
Test name
Test status
Simulation time 65329296 ps
CPU time 3.11 seconds
Started Sep 09 09:05:24 PM UTC 24
Finished Sep 09 09:05:29 PM UTC 24
Peak memory 223976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715997118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2715997118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.2038998255
Short name T226
Test name
Test status
Simulation time 5908578965 ps
CPU time 55.98 seconds
Started Sep 09 09:06:56 PM UTC 24
Finished Sep 09 09:07:53 PM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038998255 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2038998255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.570642343
Short name T18
Test name
Test status
Simulation time 48599795 ps
CPU time 1.08 seconds
Started Sep 09 09:04:43 PM UTC 24
Finished Sep 09 09:04:45 PM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570642343 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.570642343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.1291751864
Short name T157
Test name
Test status
Simulation time 105244584 ps
CPU time 5 seconds
Started Sep 09 10:22:41 PM UTC 24
Finished Sep 09 10:22:47 PM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291751864 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.1291751864
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.3984277449
Short name T778
Test name
Test status
Simulation time 1928907406 ps
CPU time 39.33 seconds
Started Sep 09 09:08:21 PM UTC 24
Finished Sep 09 09:09:02 PM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984277449 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3984277449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.2778249085
Short name T56
Test name
Test status
Simulation time 140140224 ps
CPU time 5.59 seconds
Started Sep 09 09:04:54 PM UTC 24
Finished Sep 09 09:05:01 PM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778249085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2778249085
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.1214184746
Short name T211
Test name
Test status
Simulation time 260055167 ps
CPU time 3.92 seconds
Started Sep 09 09:04:53 PM UTC 24
Finished Sep 09 09:04:58 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214184746 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1214184746
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.2272441153
Short name T250
Test name
Test status
Simulation time 239016417 ps
CPU time 11.16 seconds
Started Sep 09 09:07:20 PM UTC 24
Finished Sep 09 09:07:33 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272441153 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2272441153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.2024649354
Short name T228
Test name
Test status
Simulation time 1435462136 ps
CPU time 44.08 seconds
Started Sep 09 09:09:23 PM UTC 24
Finished Sep 09 09:10:09 PM UTC 24
Peak memory 231056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024649354 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2024649354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.1441243595
Short name T48
Test name
Test status
Simulation time 4707653965 ps
CPU time 31.21 seconds
Started Sep 09 09:06:59 PM UTC 24
Finished Sep 09 09:07:32 PM UTC 24
Peak memory 230404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441243595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1441243595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.1603253978
Short name T177
Test name
Test status
Simulation time 1320724303 ps
CPU time 7.23 seconds
Started Sep 09 10:23:26 PM UTC 24
Finished Sep 09 10:23:34 PM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603253978 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.1603253978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.2248570574
Short name T99
Test name
Test status
Simulation time 603472774 ps
CPU time 19.1 seconds
Started Sep 09 09:04:45 PM UTC 24
Finished Sep 09 09:05:05 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248570574 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2248570574
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.3461164486
Short name T219
Test name
Test status
Simulation time 3054658527 ps
CPU time 33.2 seconds
Started Sep 09 09:06:46 PM UTC 24
Finished Sep 09 09:07:21 PM UTC 24
Peak memory 232532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461164486 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3461164486
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.2439315866
Short name T443
Test name
Test status
Simulation time 1406854143 ps
CPU time 18.9 seconds
Started Sep 09 09:09:03 PM UTC 24
Finished Sep 09 09:09:23 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439315866 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2439315866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.327811616
Short name T169
Test name
Test status
Simulation time 293935558 ps
CPU time 2.55 seconds
Started Sep 09 09:07:12 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327811616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.327811616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.1971055812
Short name T125
Test name
Test status
Simulation time 100415903 ps
CPU time 2.6 seconds
Started Sep 09 09:04:47 PM UTC 24
Finished Sep 09 09:04:51 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971055812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1971055812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.3434695312
Short name T392
Test name
Test status
Simulation time 74186831 ps
CPU time 2.6 seconds
Started Sep 09 09:06:18 PM UTC 24
Finished Sep 09 09:06:21 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434695312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3434695312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.3011612182
Short name T161
Test name
Test status
Simulation time 356774793 ps
CPU time 5.24 seconds
Started Sep 09 10:23:38 PM UTC 24
Finished Sep 09 10:23:44 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011612182 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.3011612182
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1488218472
Short name T175
Test name
Test status
Simulation time 495209718 ps
CPU time 8.9 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:50 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488218472 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.1488218472
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.1239182024
Short name T44
Test name
Test status
Simulation time 423222444 ps
CPU time 10.46 seconds
Started Sep 09 09:07:11 PM UTC 24
Finished Sep 09 09:07:22 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239182024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1239182024
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.3597982993
Short name T121
Test name
Test status
Simulation time 105001687 ps
CPU time 6.09 seconds
Started Sep 09 09:06:59 PM UTC 24
Finished Sep 09 09:07:07 PM UTC 24
Peak memory 232788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597982993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3597982993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1105842431
Short name T123
Test name
Test status
Simulation time 143055479 ps
CPU time 3.57 seconds
Started Sep 09 09:07:58 PM UTC 24
Finished Sep 09 09:08:03 PM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105842431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1105842431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.306126847
Short name T88
Test name
Test status
Simulation time 374461811 ps
CPU time 14.18 seconds
Started Sep 09 09:06:34 PM UTC 24
Finished Sep 09 09:06:49 PM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=306126847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr
_stress_all_with_rand_reset.306126847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.3446875937
Short name T406
Test name
Test status
Simulation time 99826266 ps
CPU time 4.88 seconds
Started Sep 09 09:07:47 PM UTC 24
Finished Sep 09 09:07:53 PM UTC 24
Peak memory 223968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446875937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3446875937
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.719552185
Short name T390
Test name
Test status
Simulation time 110971973 ps
CPU time 6.87 seconds
Started Sep 09 09:08:07 PM UTC 24
Finished Sep 09 09:08:15 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719552185 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.719552185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.1981510633
Short name T331
Test name
Test status
Simulation time 4335377183 ps
CPU time 92.16 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:10:39 PM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981510633 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1981510633
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.1791708953
Short name T329
Test name
Test status
Simulation time 653907743 ps
CPU time 4.55 seconds
Started Sep 09 09:05:52 PM UTC 24
Finished Sep 09 09:05:58 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791708953 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1791708953
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.8859099
Short name T13
Test name
Test status
Simulation time 2821296359 ps
CPU time 7.93 seconds
Started Sep 09 09:04:52 PM UTC 24
Finished Sep 09 09:05:01 PM UTC 24
Peak memory 252404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8859099 -assert nopostproc +UVM_TESTNAME=keymgr_
base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.8859099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.3819046166
Short name T179
Test name
Test status
Simulation time 197843826 ps
CPU time 3.41 seconds
Started Sep 09 10:23:36 PM UTC 24
Finished Sep 09 10:23:40 PM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819046166 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.3819046166
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.2229967199
Short name T168
Test name
Test status
Simulation time 104342450 ps
CPU time 3.68 seconds
Started Sep 09 10:23:08 PM UTC 24
Finished Sep 09 10:23:13 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229967199 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.2229967199
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.3441159377
Short name T118
Test name
Test status
Simulation time 69088308 ps
CPU time 4.13 seconds
Started Sep 09 09:06:32 PM UTC 24
Finished Sep 09 09:06:38 PM UTC 24
Peak memory 232788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441159377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3441159377
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.2580501279
Short name T124
Test name
Test status
Simulation time 77198592 ps
CPU time 3.18 seconds
Started Sep 09 09:08:04 PM UTC 24
Finished Sep 09 09:08:08 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580501279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2580501279
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3067381130
Short name T5
Test name
Test status
Simulation time 322073869 ps
CPU time 3.31 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:44 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067381130 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3067381130
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_random.1579163116
Short name T34
Test name
Test status
Simulation time 113102326 ps
CPU time 5.24 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:46 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579163116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1579163116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.1633388955
Short name T260
Test name
Test status
Simulation time 53060426 ps
CPU time 4.57 seconds
Started Sep 09 09:06:24 PM UTC 24
Finished Sep 09 09:06:29 PM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633388955 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1633388955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.177521333
Short name T89
Test name
Test status
Simulation time 9693631903 ps
CPU time 24.47 seconds
Started Sep 09 09:06:27 PM UTC 24
Finished Sep 09 09:06:53 PM UTC 24
Peak memory 232544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=177521333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr
_stress_all_with_rand_reset.177521333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.1430267531
Short name T321
Test name
Test status
Simulation time 124924008 ps
CPU time 4.21 seconds
Started Sep 09 09:06:39 PM UTC 24
Finished Sep 09 09:06:44 PM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430267531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1430267531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.384657220
Short name T325
Test name
Test status
Simulation time 2767498893 ps
CPU time 10.74 seconds
Started Sep 09 09:08:31 PM UTC 24
Finished Sep 09 09:08:42 PM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=384657220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr
_stress_all_with_rand_reset.384657220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.2206271757
Short name T366
Test name
Test status
Simulation time 1877118118 ps
CPU time 15.59 seconds
Started Sep 09 09:08:50 PM UTC 24
Finished Sep 09 09:09:07 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206271757 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2206271757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.274751011
Short name T257
Test name
Test status
Simulation time 65905993782 ps
CPU time 184.33 seconds
Started Sep 09 09:06:00 PM UTC 24
Finished Sep 09 09:09:07 PM UTC 24
Peak memory 232680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274751011 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.274751011
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.296588098
Short name T222
Test name
Test status
Simulation time 71423051 ps
CPU time 2.84 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:09:08 PM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296588098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.296588098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.4145253778
Short name T120
Test name
Test status
Simulation time 340894864 ps
CPU time 3.33 seconds
Started Sep 09 09:07:12 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145253778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4145253778
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.171214673
Short name T122
Test name
Test status
Simulation time 135298997 ps
CPU time 3.42 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:08:56 PM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171214673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.171214673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.3285672867
Short name T16
Test name
Test status
Simulation time 27501965 ps
CPU time 2.14 seconds
Started Sep 09 09:04:41 PM UTC 24
Finished Sep 09 09:04:44 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285672867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3285672867
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.2735789959
Short name T296
Test name
Test status
Simulation time 1948784805 ps
CPU time 19.71 seconds
Started Sep 09 09:06:06 PM UTC 24
Finished Sep 09 09:06:27 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735789959 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2735789959
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.713224021
Short name T274
Test name
Test status
Simulation time 109214817 ps
CPU time 3.11 seconds
Started Sep 09 09:06:09 PM UTC 24
Finished Sep 09 09:06:13 PM UTC 24
Peak memory 230912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713224021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.713224021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.2240475430
Short name T85
Test name
Test status
Simulation time 641733388 ps
CPU time 11.01 seconds
Started Sep 09 09:06:13 PM UTC 24
Finished Sep 09 09:06:25 PM UTC 24
Peak memory 232800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2240475430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg
r_stress_all_with_rand_reset.2240475430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.2339368684
Short name T236
Test name
Test status
Simulation time 491217472 ps
CPU time 5.55 seconds
Started Sep 09 09:07:41 PM UTC 24
Finished Sep 09 09:07:48 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339368684 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2339368684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.1296675726
Short name T277
Test name
Test status
Simulation time 120219028 ps
CPU time 3.3 seconds
Started Sep 09 09:08:03 PM UTC 24
Finished Sep 09 09:08:07 PM UTC 24
Peak memory 231456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296675726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1296675726
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.4286305660
Short name T207
Test name
Test status
Simulation time 377410526 ps
CPU time 11.11 seconds
Started Sep 09 09:05:01 PM UTC 24
Finished Sep 09 09:05:14 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286305660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4286305660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.2354339978
Short name T305
Test name
Test status
Simulation time 222443622 ps
CPU time 5.78 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:31 PM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354339978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2354339978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.2694511507
Short name T448
Test name
Test status
Simulation time 1153011730 ps
CPU time 36.15 seconds
Started Sep 09 09:08:46 PM UTC 24
Finished Sep 09 09:09:23 PM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694511507 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2694511507
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.1292021562
Short name T244
Test name
Test status
Simulation time 189922995 ps
CPU time 12.08 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:31 PM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1292021562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymg
r_stress_all_with_rand_reset.1292021562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.284645593
Short name T181
Test name
Test status
Simulation time 54160723 ps
CPU time 3.66 seconds
Started Sep 09 10:23:43 PM UTC 24
Finished Sep 09 10:23:48 PM UTC 24
Peak memory 226008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284645593 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.284645593
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.3169078186
Short name T165
Test name
Test status
Simulation time 354384485 ps
CPU time 5.34 seconds
Started Sep 09 10:22:49 PM UTC 24
Finished Sep 09 10:22:56 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169078186 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.3169078186
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.1117151998
Short name T176
Test name
Test status
Simulation time 214490641 ps
CPU time 4.36 seconds
Started Sep 09 10:23:15 PM UTC 24
Finished Sep 09 10:23:21 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117151998 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.1117151998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.1116664222
Short name T170
Test name
Test status
Simulation time 98804550 ps
CPU time 5.46 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:24 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116664222 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.1116664222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.366191543
Short name T173
Test name
Test status
Simulation time 106599021 ps
CPU time 3.24 seconds
Started Sep 09 10:23:20 PM UTC 24
Finished Sep 09 10:23:24 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366191543 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.366191543
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.3500289502
Short name T14
Test name
Test status
Simulation time 504978860 ps
CPU time 8.82 seconds
Started Sep 09 09:04:59 PM UTC 24
Finished Sep 09 09:05:09 PM UTC 24
Peak memory 260328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500289502 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3500289502
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.400846621
Short name T166
Test name
Test status
Simulation time 2185822613 ps
CPU time 11.49 seconds
Started Sep 09 09:07:34 PM UTC 24
Finished Sep 09 09:07:47 PM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400846621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.400846621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_random.3270020552
Short name T198
Test name
Test status
Simulation time 195879114 ps
CPU time 7.17 seconds
Started Sep 09 09:04:46 PM UTC 24
Finished Sep 09 09:04:54 PM UTC 24
Peak memory 219948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270020552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3270020552
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.63351974
Short name T159
Test name
Test status
Simulation time 631554894 ps
CPU time 4.94 seconds
Started Sep 09 09:04:45 PM UTC 24
Finished Sep 09 09:04:51 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63351974 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.63351974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.1019489830
Short name T512
Test name
Test status
Simulation time 1912862434 ps
CPU time 47.06 seconds
Started Sep 09 09:06:09 PM UTC 24
Finished Sep 09 09:06:58 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019489830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1019489830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.450021556
Short name T365
Test name
Test status
Simulation time 345686739 ps
CPU time 6.57 seconds
Started Sep 09 09:06:31 PM UTC 24
Finished Sep 09 09:06:39 PM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450021556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.450021556
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.2703374904
Short name T315
Test name
Test status
Simulation time 1695768300 ps
CPU time 32.34 seconds
Started Sep 09 09:06:34 PM UTC 24
Finished Sep 09 09:07:07 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703374904 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2703374904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.2494503812
Short name T271
Test name
Test status
Simulation time 48268658 ps
CPU time 2.98 seconds
Started Sep 09 09:06:59 PM UTC 24
Finished Sep 09 09:07:03 PM UTC 24
Peak memory 230188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494503812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2494503812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.4083615345
Short name T232
Test name
Test status
Simulation time 423622320 ps
CPU time 3.13 seconds
Started Sep 09 09:06:58 PM UTC 24
Finished Sep 09 09:07:02 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083615345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4083615345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.3844610430
Short name T220
Test name
Test status
Simulation time 248951706 ps
CPU time 4.43 seconds
Started Sep 09 09:07:04 PM UTC 24
Finished Sep 09 09:07:10 PM UTC 24
Peak memory 230292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844610430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3844610430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.3264961809
Short name T375
Test name
Test status
Simulation time 488356109 ps
CPU time 11.43 seconds
Started Sep 09 09:07:10 PM UTC 24
Finished Sep 09 09:07:22 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264961809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3264961809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.1441185581
Short name T311
Test name
Test status
Simulation time 552044722 ps
CPU time 6.83 seconds
Started Sep 09 09:07:40 PM UTC 24
Finished Sep 09 09:07:48 PM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441185581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1441185581
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.4039849209
Short name T368
Test name
Test status
Simulation time 135022550 ps
CPU time 4.86 seconds
Started Sep 09 09:07:53 PM UTC 24
Finished Sep 09 09:07:59 PM UTC 24
Peak memory 219988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039849209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4039849209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.965549472
Short name T264
Test name
Test status
Simulation time 91750410 ps
CPU time 2.84 seconds
Started Sep 09 09:08:23 PM UTC 24
Finished Sep 09 09:08:26 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965549472 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.965549472
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.2204261364
Short name T340
Test name
Test status
Simulation time 70391946 ps
CPU time 3.07 seconds
Started Sep 09 09:08:29 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204261364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2204261364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.3736163471
Short name T378
Test name
Test status
Simulation time 49010043 ps
CPU time 3.57 seconds
Started Sep 09 09:08:59 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736163471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3736163471
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all_with_rand_reset.3623390902
Short name T397
Test name
Test status
Simulation time 356805507 ps
CPU time 7.09 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:09:22 PM UTC 24
Peak memory 230628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3623390902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymg
r_stress_all_with_rand_reset.3623390902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.1651438261
Short name T930
Test name
Test status
Simulation time 4889756083 ps
CPU time 12.36 seconds
Started Sep 09 10:22:43 PM UTC 24
Finished Sep 09 10:22:56 PM UTC 24
Peak memory 215996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651438261 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1651438261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2526447980
Short name T937
Test name
Test status
Simulation time 9557710434 ps
CPU time 18.28 seconds
Started Sep 09 10:22:42 PM UTC 24
Finished Sep 09 10:23:02 PM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526447980 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2526447980
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1803028020
Short name T164
Test name
Test status
Simulation time 21383605 ps
CPU time 1.36 seconds
Started Sep 09 10:22:41 PM UTC 24
Finished Sep 09 10:22:43 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803028020 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1803028020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2237971079
Short name T182
Test name
Test status
Simulation time 136973058 ps
CPU time 2.41 seconds
Started Sep 09 10:22:44 PM UTC 24
Finished Sep 09 10:22:48 PM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2237971079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w
ith_rand_reset.2237971079
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1803039772
Short name T163
Test name
Test status
Simulation time 68795372 ps
CPU time 1.22 seconds
Started Sep 09 10:22:41 PM UTC 24
Finished Sep 09 10:22:43 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803039772 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1803039772
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.1042872759
Short name T920
Test name
Test status
Simulation time 61187811 ps
CPU time 1.19 seconds
Started Sep 09 10:22:41 PM UTC 24
Finished Sep 09 10:22:43 PM UTC 24
Peak memory 214876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042872759 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1042872759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1386162998
Short name T112
Test name
Test status
Simulation time 185476284 ps
CPU time 2.58 seconds
Started Sep 09 10:22:43 PM UTC 24
Finished Sep 09 10:22:46 PM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386162998 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1386162998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2953682648
Short name T72
Test name
Test status
Simulation time 347654223 ps
CPU time 3.79 seconds
Started Sep 09 10:22:39 PM UTC 24
Finished Sep 09 10:22:44 PM UTC 24
Peak memory 226520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953682648 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.2953682648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.1892813553
Short name T921
Test name
Test status
Simulation time 69614493 ps
CPU time 3.06 seconds
Started Sep 09 10:22:39 PM UTC 24
Finished Sep 09 10:22:43 PM UTC 24
Peak memory 226244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892813553 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1892813553
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.403851441
Short name T116
Test name
Test status
Simulation time 128156835 ps
CPU time 7.27 seconds
Started Sep 09 10:22:48 PM UTC 24
Finished Sep 09 10:22:57 PM UTC 24
Peak memory 216064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403851441 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.403851441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1267157903
Short name T932
Test name
Test status
Simulation time 2549597494 ps
CPU time 9.93 seconds
Started Sep 09 10:22:47 PM UTC 24
Finished Sep 09 10:22:58 PM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267157903 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1267157903
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4055218325
Short name T923
Test name
Test status
Simulation time 32062952 ps
CPU time 1.63 seconds
Started Sep 09 10:22:46 PM UTC 24
Finished Sep 09 10:22:48 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055218325 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4055218325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2915863407
Short name T925
Test name
Test status
Simulation time 53640224 ps
CPU time 1.69 seconds
Started Sep 09 10:22:49 PM UTC 24
Finished Sep 09 10:22:52 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2915863407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w
ith_rand_reset.2915863407
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.960398688
Short name T113
Test name
Test status
Simulation time 28366870 ps
CPU time 1.48 seconds
Started Sep 09 10:22:46 PM UTC 24
Finished Sep 09 10:22:48 PM UTC 24
Peak memory 213184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960398688 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.960398688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.1160141265
Short name T922
Test name
Test status
Simulation time 46765415 ps
CPU time 1.02 seconds
Started Sep 09 10:22:44 PM UTC 24
Finished Sep 09 10:22:47 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160141265 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1160141265
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3520883227
Short name T114
Test name
Test status
Simulation time 93093912 ps
CPU time 2.14 seconds
Started Sep 09 10:22:48 PM UTC 24
Finished Sep 09 10:22:52 PM UTC 24
Peak memory 216076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520883227 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.3520883227
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2727917427
Short name T77
Test name
Test status
Simulation time 489336105 ps
CPU time 3.19 seconds
Started Sep 09 10:22:44 PM UTC 24
Finished Sep 09 10:22:48 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727917427 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.2727917427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.180666592
Short name T74
Test name
Test status
Simulation time 214479353 ps
CPU time 7.08 seconds
Started Sep 09 10:22:44 PM UTC 24
Finished Sep 09 10:22:52 PM UTC 24
Peak memory 232648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180666592 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.180666592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.3860650995
Short name T924
Test name
Test status
Simulation time 44376982 ps
CPU time 2.81 seconds
Started Sep 09 10:22:44 PM UTC 24
Finished Sep 09 10:22:48 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860650995 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3860650995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.3743880048
Short name T158
Test name
Test status
Simulation time 305207232 ps
CPU time 5.24 seconds
Started Sep 09 10:22:44 PM UTC 24
Finished Sep 09 10:22:51 PM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743880048 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.3743880048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.47432123
Short name T991
Test name
Test status
Simulation time 57349482 ps
CPU time 2.04 seconds
Started Sep 09 10:23:24 PM UTC 24
Finished Sep 09 10:23:27 PM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=47432123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_wi
th_rand_reset.47432123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.1090077250
Short name T988
Test name
Test status
Simulation time 25919790 ps
CPU time 1.35 seconds
Started Sep 09 10:23:24 PM UTC 24
Finished Sep 09 10:23:27 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090077250 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1090077250
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.84031097
Short name T986
Test name
Test status
Simulation time 13534847 ps
CPU time 1.02 seconds
Started Sep 09 10:23:24 PM UTC 24
Finished Sep 09 10:23:26 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84031097 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.84031097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.134331562
Short name T993
Test name
Test status
Simulation time 67750183 ps
CPU time 2.53 seconds
Started Sep 09 10:23:24 PM UTC 24
Finished Sep 09 10:23:28 PM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134331562 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.134331562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4033417621
Short name T990
Test name
Test status
Simulation time 342829636 ps
CPU time 3.54 seconds
Started Sep 09 10:23:23 PM UTC 24
Finished Sep 09 10:23:27 PM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033417621 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.4033417621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2790308651
Short name T995
Test name
Test status
Simulation time 272535906 ps
CPU time 4.36 seconds
Started Sep 09 10:23:23 PM UTC 24
Finished Sep 09 10:23:28 PM UTC 24
Peak memory 226604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790308651 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.2790308651
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.1940342730
Short name T983
Test name
Test status
Simulation time 102876597 ps
CPU time 2.09 seconds
Started Sep 09 10:23:23 PM UTC 24
Finished Sep 09 10:23:26 PM UTC 24
Peak memory 226272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940342730 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1940342730
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.946283819
Short name T989
Test name
Test status
Simulation time 94981619 ps
CPU time 3.03 seconds
Started Sep 09 10:23:23 PM UTC 24
Finished Sep 09 10:23:27 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946283819 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.946283819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1604207247
Short name T999
Test name
Test status
Simulation time 38129333 ps
CPU time 1.56 seconds
Started Sep 09 10:23:27 PM UTC 24
Finished Sep 09 10:23:30 PM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1604207247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_
with_rand_reset.1604207247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.228881651
Short name T996
Test name
Test status
Simulation time 28517598 ps
CPU time 1.58 seconds
Started Sep 09 10:23:26 PM UTC 24
Finished Sep 09 10:23:28 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228881651 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.228881651
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.3754050084
Short name T994
Test name
Test status
Simulation time 15544391 ps
CPU time 1.05 seconds
Started Sep 09 10:23:26 PM UTC 24
Finished Sep 09 10:23:28 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754050084 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3754050084
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1249121615
Short name T1000
Test name
Test status
Simulation time 44789877 ps
CPU time 1.54 seconds
Started Sep 09 10:23:27 PM UTC 24
Finished Sep 09 10:23:30 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249121615 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.1249121615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2766106303
Short name T992
Test name
Test status
Simulation time 57010518 ps
CPU time 2.39 seconds
Started Sep 09 10:23:24 PM UTC 24
Finished Sep 09 10:23:28 PM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766106303 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.2766106303
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1365242596
Short name T998
Test name
Test status
Simulation time 279563501 ps
CPU time 4.04 seconds
Started Sep 09 10:23:24 PM UTC 24
Finished Sep 09 10:23:30 PM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365242596 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.1365242596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2520589455
Short name T1010
Test name
Test status
Simulation time 2189839438 ps
CPU time 6.14 seconds
Started Sep 09 10:23:26 PM UTC 24
Finished Sep 09 10:23:33 PM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520589455 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2520589455
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2125389064
Short name T1005
Test name
Test status
Simulation time 83922484 ps
CPU time 1.94 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:32 PM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2125389064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_
with_rand_reset.2125389064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.766280079
Short name T1004
Test name
Test status
Simulation time 42343768 ps
CPU time 1.43 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:32 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766280079 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.766280079
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.1238798125
Short name T1002
Test name
Test status
Simulation time 13416112 ps
CPU time 0.96 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:31 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238798125 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1238798125
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1670039876
Short name T1007
Test name
Test status
Simulation time 146265850 ps
CPU time 2.35 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:32 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670039876 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.1670039876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.881901792
Short name T1001
Test name
Test status
Simulation time 74294750 ps
CPU time 2.23 seconds
Started Sep 09 10:23:27 PM UTC 24
Finished Sep 09 10:23:31 PM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881901792 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.881901792
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2444581281
Short name T1015
Test name
Test status
Simulation time 738243509 ps
CPU time 6.14 seconds
Started Sep 09 10:23:27 PM UTC 24
Finished Sep 09 10:23:35 PM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444581281 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.2444581281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.2654310063
Short name T1003
Test name
Test status
Simulation time 63036558 ps
CPU time 2.65 seconds
Started Sep 09 10:23:28 PM UTC 24
Finished Sep 09 10:23:31 PM UTC 24
Peak memory 226272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654310063 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2654310063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.3671578348
Short name T1013
Test name
Test status
Simulation time 108628438 ps
CPU time 4.98 seconds
Started Sep 09 10:23:28 PM UTC 24
Finished Sep 09 10:23:34 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671578348 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.3671578348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2095923135
Short name T1011
Test name
Test status
Simulation time 34571048 ps
CPU time 1.36 seconds
Started Sep 09 10:23:31 PM UTC 24
Finished Sep 09 10:23:33 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2095923135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_
with_rand_reset.2095923135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.1431004921
Short name T1009
Test name
Test status
Simulation time 12832391 ps
CPU time 1.09 seconds
Started Sep 09 10:23:31 PM UTC 24
Finished Sep 09 10:23:33 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431004921 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1431004921
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.441978642
Short name T1008
Test name
Test status
Simulation time 49544730 ps
CPU time 1.02 seconds
Started Sep 09 10:23:31 PM UTC 24
Finished Sep 09 10:23:33 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441978642 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.441978642
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.875291122
Short name T1014
Test name
Test status
Simulation time 62566560 ps
CPU time 2.6 seconds
Started Sep 09 10:23:31 PM UTC 24
Finished Sep 09 10:23:34 PM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875291122 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.875291122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.504084354
Short name T1012
Test name
Test status
Simulation time 947058650 ps
CPU time 3.22 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:34 PM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504084354 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.504084354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1770292089
Short name T1028
Test name
Test status
Simulation time 201166429 ps
CPU time 9.2 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:39 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770292089 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.1770292089
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.2083869066
Short name T1006
Test name
Test status
Simulation time 383546574 ps
CPU time 1.9 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:32 PM UTC 24
Peak memory 226288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083869066 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2083869066
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.1257746273
Short name T162
Test name
Test status
Simulation time 190439769 ps
CPU time 5.61 seconds
Started Sep 09 10:23:29 PM UTC 24
Finished Sep 09 10:23:36 PM UTC 24
Peak memory 226348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257746273 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.1257746273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.174045360
Short name T1018
Test name
Test status
Simulation time 25052708 ps
CPU time 2.01 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:37 PM UTC 24
Peak memory 225772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=174045360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_w
ith_rand_reset.174045360
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.260286319
Short name T1017
Test name
Test status
Simulation time 14842446 ps
CPU time 1.64 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:37 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260286319 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.260286319
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.4014618109
Short name T1016
Test name
Test status
Simulation time 21139824 ps
CPU time 1.09 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:36 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014618109 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4014618109
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.369581482
Short name T1020
Test name
Test status
Simulation time 72463152 ps
CPU time 2.51 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:38 PM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369581482 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.369581482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.836402043
Short name T1019
Test name
Test status
Simulation time 128164640 ps
CPU time 4.13 seconds
Started Sep 09 10:23:32 PM UTC 24
Finished Sep 09 10:23:37 PM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836402043 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.836402043
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3159128243
Short name T1059
Test name
Test status
Simulation time 424450892 ps
CPU time 15.7 seconds
Started Sep 09 10:23:32 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159128243 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.3159128243
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1411141414
Short name T1025
Test name
Test status
Simulation time 615257075 ps
CPU time 5.06 seconds
Started Sep 09 10:23:32 PM UTC 24
Finished Sep 09 10:23:38 PM UTC 24
Peak memory 226196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411141414 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1411141414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1678728340
Short name T401
Test name
Test status
Simulation time 186646085 ps
CPU time 3.15 seconds
Started Sep 09 10:23:32 PM UTC 24
Finished Sep 09 10:23:37 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678728340 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.1678728340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3000799729
Short name T1026
Test name
Test status
Simulation time 160133519 ps
CPU time 1.79 seconds
Started Sep 09 10:23:36 PM UTC 24
Finished Sep 09 10:23:39 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3000799729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_
with_rand_reset.3000799729
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.217279677
Short name T1023
Test name
Test status
Simulation time 36697024 ps
CPU time 1.28 seconds
Started Sep 09 10:23:36 PM UTC 24
Finished Sep 09 10:23:38 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217279677 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.217279677
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.253840009
Short name T1022
Test name
Test status
Simulation time 173314838 ps
CPU time 1.14 seconds
Started Sep 09 10:23:36 PM UTC 24
Finished Sep 09 10:23:38 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253840009 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.253840009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2766830834
Short name T1027
Test name
Test status
Simulation time 75742760 ps
CPU time 2.08 seconds
Started Sep 09 10:23:36 PM UTC 24
Finished Sep 09 10:23:39 PM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766830834 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.2766830834
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1599409164
Short name T1021
Test name
Test status
Simulation time 133115485 ps
CPU time 2.36 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:38 PM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599409164 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.1599409164
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1361793372
Short name T1029
Test name
Test status
Simulation time 355693354 ps
CPU time 5.18 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:40 PM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361793372 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.1361793372
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3197840375
Short name T1024
Test name
Test status
Simulation time 40191241 ps
CPU time 3.1 seconds
Started Sep 09 10:23:34 PM UTC 24
Finished Sep 09 10:23:38 PM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197840375 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3197840375
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2890846954
Short name T1038
Test name
Test status
Simulation time 30988923 ps
CPU time 3.23 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:44 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2890846954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_
with_rand_reset.2890846954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1682415294
Short name T1031
Test name
Test status
Simulation time 65602713 ps
CPU time 1.27 seconds
Started Sep 09 10:23:39 PM UTC 24
Finished Sep 09 10:23:42 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682415294 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1682415294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3287895250
Short name T1030
Test name
Test status
Simulation time 19288933 ps
CPU time 0.96 seconds
Started Sep 09 10:23:39 PM UTC 24
Finished Sep 09 10:23:41 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287895250 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3287895250
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.405465329
Short name T1036
Test name
Test status
Simulation time 101581212 ps
CPU time 2.93 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:44 PM UTC 24
Peak memory 226108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405465329 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.405465329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1037145973
Short name T1033
Test name
Test status
Simulation time 107516049 ps
CPU time 3.63 seconds
Started Sep 09 10:23:37 PM UTC 24
Finished Sep 09 10:23:42 PM UTC 24
Peak memory 226608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037145973 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.1037145973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1472798719
Short name T1045
Test name
Test status
Simulation time 724157388 ps
CPU time 7.31 seconds
Started Sep 09 10:23:38 PM UTC 24
Finished Sep 09 10:23:46 PM UTC 24
Peak memory 232664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472798719 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.1472798719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1632988131
Short name T1035
Test name
Test status
Simulation time 557979216 ps
CPU time 4.49 seconds
Started Sep 09 10:23:38 PM UTC 24
Finished Sep 09 10:23:43 PM UTC 24
Peak memory 228132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632988131 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1632988131
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2695214113
Short name T1040
Test name
Test status
Simulation time 114604486 ps
CPU time 1.91 seconds
Started Sep 09 10:23:41 PM UTC 24
Finished Sep 09 10:23:44 PM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2695214113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_
with_rand_reset.2695214113
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.3639045116
Short name T1039
Test name
Test status
Simulation time 175237020 ps
CPU time 1.52 seconds
Started Sep 09 10:23:41 PM UTC 24
Finished Sep 09 10:23:44 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639045116 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3639045116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.535676437
Short name T1032
Test name
Test status
Simulation time 9197291 ps
CPU time 0.99 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:42 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535676437 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.535676437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2184194954
Short name T1041
Test name
Test status
Simulation time 49749116 ps
CPU time 2.38 seconds
Started Sep 09 10:23:41 PM UTC 24
Finished Sep 09 10:23:45 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184194954 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.2184194954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1214181185
Short name T1034
Test name
Test status
Simulation time 498744592 ps
CPU time 2.31 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:43 PM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214181185 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.1214181185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4080652489
Short name T1046
Test name
Test status
Simulation time 86018678 ps
CPU time 5.66 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:46 PM UTC 24
Peak memory 226740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080652489 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.4080652489
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3275510212
Short name T1037
Test name
Test status
Simulation time 389264373 ps
CPU time 2.73 seconds
Started Sep 09 10:23:40 PM UTC 24
Finished Sep 09 10:23:44 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275510212 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3275510212
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3702414443
Short name T1052
Test name
Test status
Simulation time 27558430 ps
CPU time 2.18 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:48 PM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3702414443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_
with_rand_reset.3702414443
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2337513364
Short name T1044
Test name
Test status
Simulation time 136018074 ps
CPU time 1.52 seconds
Started Sep 09 10:23:43 PM UTC 24
Finished Sep 09 10:23:46 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337513364 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2337513364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1951393970
Short name T1043
Test name
Test status
Simulation time 15921971 ps
CPU time 0.99 seconds
Started Sep 09 10:23:43 PM UTC 24
Finished Sep 09 10:23:45 PM UTC 24
Peak memory 213436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951393970 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1951393970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3522983323
Short name T1049
Test name
Test status
Simulation time 36221155 ps
CPU time 2.43 seconds
Started Sep 09 10:23:43 PM UTC 24
Finished Sep 09 10:23:47 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522983323 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3522983323
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.706073524
Short name T1042
Test name
Test status
Simulation time 255550979 ps
CPU time 2.3 seconds
Started Sep 09 10:23:42 PM UTC 24
Finished Sep 09 10:23:45 PM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706073524 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.706073524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3598172682
Short name T1047
Test name
Test status
Simulation time 103152673 ps
CPU time 3.92 seconds
Started Sep 09 10:23:42 PM UTC 24
Finished Sep 09 10:23:47 PM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598172682 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.3598172682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.244258374
Short name T1048
Test name
Test status
Simulation time 50338678 ps
CPU time 3.85 seconds
Started Sep 09 10:23:42 PM UTC 24
Finished Sep 09 10:23:47 PM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244258374 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.244258374
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.895589005
Short name T1060
Test name
Test status
Simulation time 55800868 ps
CPU time 1.57 seconds
Started Sep 09 10:23:47 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 213416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=895589005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_w
ith_rand_reset.895589005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.4244118994
Short name T1051
Test name
Test status
Simulation time 152081277 ps
CPU time 1.56 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:48 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244118994 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4244118994
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3542240688
Short name T1050
Test name
Test status
Simulation time 16031478 ps
CPU time 1.06 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:47 PM UTC 24
Peak memory 213568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542240688 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3542240688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1639393956
Short name T1053
Test name
Test status
Simulation time 24832331 ps
CPU time 2.21 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639393956 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.1639393956
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3744337865
Short name T1057
Test name
Test status
Simulation time 179243690 ps
CPU time 2.95 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744337865 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.3744337865
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2053318983
Short name T1082
Test name
Test status
Simulation time 151115953 ps
CPU time 8.45 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:55 PM UTC 24
Peak memory 226732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053318983 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.2053318983
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2898582369
Short name T1061
Test name
Test status
Simulation time 166962551 ps
CPU time 3.23 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898582369 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2898582369
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.607022751
Short name T171
Test name
Test status
Simulation time 339525242 ps
CPU time 5.13 seconds
Started Sep 09 10:23:45 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 226164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607022751 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.607022751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.3781265913
Short name T941
Test name
Test status
Simulation time 1006455508 ps
CPU time 9.53 seconds
Started Sep 09 10:22:54 PM UTC 24
Finished Sep 09 10:23:04 PM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781265913 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3781265913
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.903988134
Short name T954
Test name
Test status
Simulation time 854801332 ps
CPU time 17.76 seconds
Started Sep 09 10:22:54 PM UTC 24
Finished Sep 09 10:23:13 PM UTC 24
Peak memory 216128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903988134 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.903988134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3799737963
Short name T928
Test name
Test status
Simulation time 70955674 ps
CPU time 1.46 seconds
Started Sep 09 10:22:52 PM UTC 24
Finished Sep 09 10:22:55 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799737963 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3799737963
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.140889379
Short name T931
Test name
Test status
Simulation time 39529974 ps
CPU time 3.11 seconds
Started Sep 09 10:22:54 PM UTC 24
Finished Sep 09 10:22:58 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=140889379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_wi
th_rand_reset.140889379
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.504773327
Short name T929
Test name
Test status
Simulation time 44599687 ps
CPU time 1.45 seconds
Started Sep 09 10:22:52 PM UTC 24
Finished Sep 09 10:22:55 PM UTC 24
Peak memory 213644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504773327 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.504773327
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.2330045889
Short name T927
Test name
Test status
Simulation time 14750456 ps
CPU time 0.97 seconds
Started Sep 09 10:22:51 PM UTC 24
Finished Sep 09 10:22:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330045889 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2330045889
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3367977526
Short name T115
Test name
Test status
Simulation time 22970930 ps
CPU time 1.64 seconds
Started Sep 09 10:22:54 PM UTC 24
Finished Sep 09 10:22:56 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367977526 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.3367977526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1355825593
Short name T82
Test name
Test status
Simulation time 96837767 ps
CPU time 2.64 seconds
Started Sep 09 10:22:49 PM UTC 24
Finished Sep 09 10:22:53 PM UTC 24
Peak memory 226776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355825593 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1355825593
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.86366274
Short name T83
Test name
Test status
Simulation time 727332756 ps
CPU time 7.23 seconds
Started Sep 09 10:22:49 PM UTC 24
Finished Sep 09 10:22:58 PM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86366274 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.86366274
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3637062119
Short name T926
Test name
Test status
Simulation time 25276024 ps
CPU time 2.26 seconds
Started Sep 09 10:22:49 PM UTC 24
Finished Sep 09 10:22:53 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637062119 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3637062119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.2640399161
Short name T1055
Test name
Test status
Simulation time 16408106 ps
CPU time 0.96 seconds
Started Sep 09 10:23:47 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 213468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640399161 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2640399161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.222947605
Short name T1058
Test name
Test status
Simulation time 23919892 ps
CPU time 1.11 seconds
Started Sep 09 10:23:47 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 213084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222947605 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.222947605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.243583651
Short name T1056
Test name
Test status
Simulation time 38278173 ps
CPU time 0.95 seconds
Started Sep 09 10:23:47 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243583651 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.243583651
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.4081382970
Short name T1054
Test name
Test status
Simulation time 7983222 ps
CPU time 0.85 seconds
Started Sep 09 10:23:47 PM UTC 24
Finished Sep 09 10:23:49 PM UTC 24
Peak memory 213068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081382970 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4081382970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.3194994898
Short name T1062
Test name
Test status
Simulation time 9757910 ps
CPU time 0.87 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:50 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194994898 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3194994898
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1704534816
Short name T1064
Test name
Test status
Simulation time 22085459 ps
CPU time 1.22 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704534816 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1704534816
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.2156311285
Short name T1063
Test name
Test status
Simulation time 20542778 ps
CPU time 0.89 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156311285 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2156311285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1580019845
Short name T1065
Test name
Test status
Simulation time 27046751 ps
CPU time 1.12 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580019845 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1580019845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.4020707879
Short name T1066
Test name
Test status
Simulation time 11997619 ps
CPU time 1.15 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020707879 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4020707879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.567487037
Short name T1068
Test name
Test status
Simulation time 35302766 ps
CPU time 1.1 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567487037 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.567487037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.3414890301
Short name T955
Test name
Test status
Simulation time 641932664 ps
CPU time 13.15 seconds
Started Sep 09 10:22:58 PM UTC 24
Finished Sep 09 10:23:13 PM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414890301 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3414890301
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1253710804
Short name T946
Test name
Test status
Simulation time 556813010 ps
CPU time 8.96 seconds
Started Sep 09 10:22:58 PM UTC 24
Finished Sep 09 10:23:08 PM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253710804 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1253710804
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2832934409
Short name T935
Test name
Test status
Simulation time 123619864 ps
CPU time 1.55 seconds
Started Sep 09 10:22:57 PM UTC 24
Finished Sep 09 10:23:00 PM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832934409 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2832934409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.387792564
Short name T938
Test name
Test status
Simulation time 18483973 ps
CPU time 1.48 seconds
Started Sep 09 10:22:59 PM UTC 24
Finished Sep 09 10:23:02 PM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=387792564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_wi
th_rand_reset.387792564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.4292741213
Short name T117
Test name
Test status
Simulation time 56319822 ps
CPU time 2.01 seconds
Started Sep 09 10:22:57 PM UTC 24
Finished Sep 09 10:23:00 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292741213 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4292741213
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.1034151202
Short name T933
Test name
Test status
Simulation time 12653822 ps
CPU time 1 seconds
Started Sep 09 10:22:57 PM UTC 24
Finished Sep 09 10:22:59 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034151202 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1034151202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3669144427
Short name T939
Test name
Test status
Simulation time 96734774 ps
CPU time 3.41 seconds
Started Sep 09 10:22:58 PM UTC 24
Finished Sep 09 10:23:03 PM UTC 24
Peak memory 216000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669144427 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.3669144427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2437535522
Short name T81
Test name
Test status
Simulation time 719504818 ps
CPU time 4.19 seconds
Started Sep 09 10:22:55 PM UTC 24
Finished Sep 09 10:23:00 PM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437535522 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.2437535522
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2490781676
Short name T78
Test name
Test status
Simulation time 101945586 ps
CPU time 3.72 seconds
Started Sep 09 10:22:56 PM UTC 24
Finished Sep 09 10:23:01 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490781676 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.2490781676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.2992086765
Short name T934
Test name
Test status
Simulation time 42649507 ps
CPU time 2.19 seconds
Started Sep 09 10:22:56 PM UTC 24
Finished Sep 09 10:22:59 PM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992086765 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2992086765
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.3405682960
Short name T174
Test name
Test status
Simulation time 212909638 ps
CPU time 10.6 seconds
Started Sep 09 10:22:57 PM UTC 24
Finished Sep 09 10:23:09 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405682960 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.3405682960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.4033758051
Short name T1067
Test name
Test status
Simulation time 26705091 ps
CPU time 1.06 seconds
Started Sep 09 10:23:49 PM UTC 24
Finished Sep 09 10:23:51 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033758051 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4033758051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.194677462
Short name T1073
Test name
Test status
Simulation time 93986697 ps
CPU time 1.14 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194677462 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.194677462
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.723330862
Short name T1069
Test name
Test status
Simulation time 62567895 ps
CPU time 0.83 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723330862 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.723330862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.234442968
Short name T1070
Test name
Test status
Simulation time 59194733 ps
CPU time 0.85 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234442968 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.234442968
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.3787730820
Short name T1072
Test name
Test status
Simulation time 10632038 ps
CPU time 0.92 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787730820 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3787730820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.380333680
Short name T1074
Test name
Test status
Simulation time 34731962 ps
CPU time 0.95 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380333680 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.380333680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2400894612
Short name T1075
Test name
Test status
Simulation time 26537997 ps
CPU time 1.02 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400894612 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2400894612
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3125847517
Short name T1071
Test name
Test status
Simulation time 9759889 ps
CPU time 0.79 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125847517 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3125847517
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.4246443253
Short name T1077
Test name
Test status
Simulation time 59193251 ps
CPU time 1.08 seconds
Started Sep 09 10:23:51 PM UTC 24
Finished Sep 09 10:23:54 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246443253 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4246443253
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2121689578
Short name T1078
Test name
Test status
Simulation time 39143548 ps
CPU time 1.04 seconds
Started Sep 09 10:23:52 PM UTC 24
Finished Sep 09 10:23:54 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121689578 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2121689578
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.1933325415
Short name T973
Test name
Test status
Simulation time 382449174 ps
CPU time 14.74 seconds
Started Sep 09 10:23:05 PM UTC 24
Finished Sep 09 10:23:21 PM UTC 24
Peak memory 216044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933325415 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1933325415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.707933762
Short name T961
Test name
Test status
Simulation time 449730784 ps
CPU time 10.05 seconds
Started Sep 09 10:23:04 PM UTC 24
Finished Sep 09 10:23:15 PM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707933762 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.707933762
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.123056897
Short name T945
Test name
Test status
Simulation time 36318273 ps
CPU time 2.29 seconds
Started Sep 09 10:23:03 PM UTC 24
Finished Sep 09 10:23:07 PM UTC 24
Peak memory 216128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123056897 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.123056897
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2233741187
Short name T948
Test name
Test status
Simulation time 120733024 ps
CPU time 1.61 seconds
Started Sep 09 10:23:06 PM UTC 24
Finished Sep 09 10:23:09 PM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2233741187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w
ith_rand_reset.2233741187
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.2269299376
Short name T943
Test name
Test status
Simulation time 32521764 ps
CPU time 1.23 seconds
Started Sep 09 10:23:03 PM UTC 24
Finished Sep 09 10:23:06 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269299376 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2269299376
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.4235127086
Short name T940
Test name
Test status
Simulation time 14987299 ps
CPU time 1.21 seconds
Started Sep 09 10:23:02 PM UTC 24
Finished Sep 09 10:23:04 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235127086 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4235127086
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1815469183
Short name T952
Test name
Test status
Simulation time 431256177 ps
CPU time 5.13 seconds
Started Sep 09 10:23:05 PM UTC 24
Finished Sep 09 10:23:12 PM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815469183 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.1815469183
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3552862190
Short name T947
Test name
Test status
Simulation time 880216415 ps
CPU time 6.78 seconds
Started Sep 09 10:23:01 PM UTC 24
Finished Sep 09 10:23:09 PM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552862190 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.3552862190
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.412002127
Short name T942
Test name
Test status
Simulation time 71665905 ps
CPU time 3.52 seconds
Started Sep 09 10:23:01 PM UTC 24
Finished Sep 09 10:23:05 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412002127 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.412002127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.3792439772
Short name T944
Test name
Test status
Simulation time 141489704 ps
CPU time 4.34 seconds
Started Sep 09 10:23:01 PM UTC 24
Finished Sep 09 10:23:06 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792439772 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.3792439772
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.289664871
Short name T1081
Test name
Test status
Simulation time 47226005 ps
CPU time 1.06 seconds
Started Sep 09 10:23:52 PM UTC 24
Finished Sep 09 10:23:54 PM UTC 24
Peak memory 213556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289664871 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.289664871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.96966800
Short name T1076
Test name
Test status
Simulation time 10190762 ps
CPU time 0.77 seconds
Started Sep 09 10:23:52 PM UTC 24
Finished Sep 09 10:23:53 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96966800 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.96966800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3256148334
Short name T1079
Test name
Test status
Simulation time 25601689 ps
CPU time 0.93 seconds
Started Sep 09 10:23:52 PM UTC 24
Finished Sep 09 10:23:54 PM UTC 24
Peak memory 213576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256148334 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3256148334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1342328922
Short name T1080
Test name
Test status
Simulation time 9489985 ps
CPU time 0.99 seconds
Started Sep 09 10:23:52 PM UTC 24
Finished Sep 09 10:23:54 PM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342328922 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1342328922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.2795995491
Short name T1084
Test name
Test status
Simulation time 35591479 ps
CPU time 0.92 seconds
Started Sep 09 10:23:54 PM UTC 24
Finished Sep 09 10:23:56 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795995491 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2795995491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.1981900806
Short name T1085
Test name
Test status
Simulation time 30461513 ps
CPU time 0.93 seconds
Started Sep 09 10:23:54 PM UTC 24
Finished Sep 09 10:23:56 PM UTC 24
Peak memory 213088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981900806 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1981900806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.2885060996
Short name T1086
Test name
Test status
Simulation time 34988144 ps
CPU time 0.96 seconds
Started Sep 09 10:23:54 PM UTC 24
Finished Sep 09 10:23:56 PM UTC 24
Peak memory 213092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885060996 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2885060996
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.2278315666
Short name T1087
Test name
Test status
Simulation time 47156647 ps
CPU time 1.11 seconds
Started Sep 09 10:23:54 PM UTC 24
Finished Sep 09 10:23:56 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278315666 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2278315666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1765434295
Short name T1083
Test name
Test status
Simulation time 15044008 ps
CPU time 0.73 seconds
Started Sep 09 10:23:54 PM UTC 24
Finished Sep 09 10:23:55 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765434295 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1765434295
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.981214546
Short name T1088
Test name
Test status
Simulation time 13288008 ps
CPU time 1.11 seconds
Started Sep 09 10:23:54 PM UTC 24
Finished Sep 09 10:23:56 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981214546 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.981214546
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1485498438
Short name T957
Test name
Test status
Simulation time 55225027 ps
CPU time 2.44 seconds
Started Sep 09 10:23:10 PM UTC 24
Finished Sep 09 10:23:14 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1485498438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w
ith_rand_reset.1485498438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1618041385
Short name T953
Test name
Test status
Simulation time 33441987 ps
CPU time 2.05 seconds
Started Sep 09 10:23:09 PM UTC 24
Finished Sep 09 10:23:12 PM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618041385 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1618041385
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.3907584402
Short name T950
Test name
Test status
Simulation time 45929655 ps
CPU time 1.1 seconds
Started Sep 09 10:23:09 PM UTC 24
Finished Sep 09 10:23:11 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907584402 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3907584402
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2417364974
Short name T960
Test name
Test status
Simulation time 309163594 ps
CPU time 4.06 seconds
Started Sep 09 10:23:10 PM UTC 24
Finished Sep 09 10:23:15 PM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417364974 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.2417364974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3203341506
Short name T951
Test name
Test status
Simulation time 101784411 ps
CPU time 3.64 seconds
Started Sep 09 10:23:06 PM UTC 24
Finished Sep 09 10:23:11 PM UTC 24
Peak memory 226400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203341506 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.3203341506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2192707452
Short name T956
Test name
Test status
Simulation time 321640494 ps
CPU time 4.69 seconds
Started Sep 09 10:23:08 PM UTC 24
Finished Sep 09 10:23:14 PM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192707452 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.2192707452
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.3969940434
Short name T949
Test name
Test status
Simulation time 47541108 ps
CPU time 1.44 seconds
Started Sep 09 10:23:08 PM UTC 24
Finished Sep 09 10:23:10 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969940434 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3969940434
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2310407249
Short name T963
Test name
Test status
Simulation time 30146618 ps
CPU time 1.56 seconds
Started Sep 09 10:23:14 PM UTC 24
Finished Sep 09 10:23:17 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2310407249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w
ith_rand_reset.2310407249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3414384786
Short name T959
Test name
Test status
Simulation time 20862374 ps
CPU time 1.4 seconds
Started Sep 09 10:23:13 PM UTC 24
Finished Sep 09 10:23:15 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414384786 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3414384786
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.728320527
Short name T958
Test name
Test status
Simulation time 37369886 ps
CPU time 1.12 seconds
Started Sep 09 10:23:13 PM UTC 24
Finished Sep 09 10:23:15 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728320527 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.728320527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2194046254
Short name T962
Test name
Test status
Simulation time 52138569 ps
CPU time 2.45 seconds
Started Sep 09 10:23:13 PM UTC 24
Finished Sep 09 10:23:16 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194046254 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.2194046254
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2805746619
Short name T80
Test name
Test status
Simulation time 183694133 ps
CPU time 3.27 seconds
Started Sep 09 10:23:10 PM UTC 24
Finished Sep 09 10:23:15 PM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805746619 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.2805746619
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1765900475
Short name T997
Test name
Test status
Simulation time 1069389381 ps
CPU time 16.86 seconds
Started Sep 09 10:23:10 PM UTC 24
Finished Sep 09 10:23:28 PM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765900475 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.1765900475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.3089139118
Short name T936
Test name
Test status
Simulation time 614008583 ps
CPU time 3.12 seconds
Started Sep 09 10:23:12 PM UTC 24
Finished Sep 09 10:23:16 PM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089139118 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3089139118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.2321971426
Short name T160
Test name
Test status
Simulation time 64122416 ps
CPU time 3.39 seconds
Started Sep 09 10:23:12 PM UTC 24
Finished Sep 09 10:23:16 PM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321971426 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.2321971426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4199059692
Short name T969
Test name
Test status
Simulation time 161361509 ps
CPU time 2.08 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:20 PM UTC 24
Peak memory 226168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4199059692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w
ith_rand_reset.4199059692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2955066817
Short name T966
Test name
Test status
Simulation time 72622198 ps
CPU time 1.98 seconds
Started Sep 09 10:23:16 PM UTC 24
Finished Sep 09 10:23:19 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955066817 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2955066817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.1381363806
Short name T965
Test name
Test status
Simulation time 29314754 ps
CPU time 1.1 seconds
Started Sep 09 10:23:15 PM UTC 24
Finished Sep 09 10:23:18 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381363806 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1381363806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1343395687
Short name T970
Test name
Test status
Simulation time 164524905 ps
CPU time 2.21 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:20 PM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343395687 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.1343395687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2699661257
Short name T964
Test name
Test status
Simulation time 345011494 ps
CPU time 2.21 seconds
Started Sep 09 10:23:14 PM UTC 24
Finished Sep 09 10:23:17 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699661257 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.2699661257
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2725654528
Short name T971
Test name
Test status
Simulation time 290432426 ps
CPU time 5.59 seconds
Started Sep 09 10:23:14 PM UTC 24
Finished Sep 09 10:23:21 PM UTC 24
Peak memory 226608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725654528 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.2725654528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.450034538
Short name T967
Test name
Test status
Simulation time 42276668 ps
CPU time 3.48 seconds
Started Sep 09 10:23:14 PM UTC 24
Finished Sep 09 10:23:19 PM UTC 24
Peak memory 232696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450034538 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.450034538
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4108659176
Short name T972
Test name
Test status
Simulation time 93104454 ps
CPU time 1.55 seconds
Started Sep 09 10:23:19 PM UTC 24
Finished Sep 09 10:23:21 PM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4108659176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w
ith_rand_reset.4108659176
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.2487178031
Short name T974
Test name
Test status
Simulation time 47064588 ps
CPU time 1.78 seconds
Started Sep 09 10:23:19 PM UTC 24
Finished Sep 09 10:23:21 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487178031 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2487178031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.619507087
Short name T968
Test name
Test status
Simulation time 66115460 ps
CPU time 1.09 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:19 PM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619507087 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.619507087
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1582080638
Short name T975
Test name
Test status
Simulation time 220964220 ps
CPU time 2.34 seconds
Started Sep 09 10:23:19 PM UTC 24
Finished Sep 09 10:23:22 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582080638 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.1582080638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4083067546
Short name T976
Test name
Test status
Simulation time 73626471 ps
CPU time 4.04 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:22 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083067546 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.4083067546
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3345353675
Short name T981
Test name
Test status
Simulation time 471499503 ps
CPU time 5.92 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:24 PM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345353675 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.3345353675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.2513287797
Short name T982
Test name
Test status
Simulation time 408932203 ps
CPU time 6.01 seconds
Started Sep 09 10:23:17 PM UTC 24
Finished Sep 09 10:23:24 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513287797 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2513287797
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2403715465
Short name T985
Test name
Test status
Simulation time 86736361 ps
CPU time 2.39 seconds
Started Sep 09 10:23:23 PM UTC 24
Finished Sep 09 10:23:26 PM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2403715465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w
ith_rand_reset.2403715465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.2788831275
Short name T980
Test name
Test status
Simulation time 60723693 ps
CPU time 1.3 seconds
Started Sep 09 10:23:21 PM UTC 24
Finished Sep 09 10:23:23 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788831275 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2788831275
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.2271211177
Short name T979
Test name
Test status
Simulation time 142577468 ps
CPU time 1.02 seconds
Started Sep 09 10:23:21 PM UTC 24
Finished Sep 09 10:23:23 PM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271211177 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2271211177
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1105281814
Short name T984
Test name
Test status
Simulation time 203918525 ps
CPU time 2.29 seconds
Started Sep 09 10:23:23 PM UTC 24
Finished Sep 09 10:23:26 PM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105281814 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.1105281814
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3031674105
Short name T977
Test name
Test status
Simulation time 325883544 ps
CPU time 3.21 seconds
Started Sep 09 10:23:19 PM UTC 24
Finished Sep 09 10:23:23 PM UTC 24
Peak memory 226712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031674105 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3031674105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1080571838
Short name T987
Test name
Test status
Simulation time 329663627 ps
CPU time 5.38 seconds
Started Sep 09 10:23:20 PM UTC 24
Finished Sep 09 10:23:26 PM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080571838 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.1080571838
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.3779094945
Short name T978
Test name
Test status
Simulation time 439335955 ps
CPU time 2.1 seconds
Started Sep 09 10:23:20 PM UTC 24
Finished Sep 09 10:23:23 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779094945 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3779094945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.3785923936
Short name T106
Test name
Test status
Simulation time 1219144387 ps
CPU time 6.33 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:47 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785923936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3785923936
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.2265272068
Short name T2
Test name
Test status
Simulation time 173402468 ps
CPU time 2.21 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:43 PM UTC 24
Peak memory 231492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265272068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2265272068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.3309402717
Short name T1
Test name
Test status
Simulation time 85345136 ps
CPU time 3.26 seconds
Started Sep 09 09:04:39 PM UTC 24
Finished Sep 09 09:04:43 PM UTC 24
Peak memory 214192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309402717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3309402717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.878173493
Short name T17
Test name
Test status
Simulation time 111211669 ps
CPU time 4.73 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:45 PM UTC 24
Peak memory 216184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878173493 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.878173493
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.620142290
Short name T4
Test name
Test status
Simulation time 32392710 ps
CPU time 3.21 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:04:44 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620142290 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.620142290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.934900814
Short name T90
Test name
Test status
Simulation time 3466869565 ps
CPU time 35.6 seconds
Started Sep 09 09:04:40 PM UTC 24
Finished Sep 09 09:05:17 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934900814 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.934900814
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.448681341
Short name T19
Test name
Test status
Simulation time 125520958 ps
CPU time 3.72 seconds
Started Sep 09 09:04:41 PM UTC 24
Finished Sep 09 09:04:46 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448681341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.448681341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.2102329774
Short name T411
Test name
Test status
Simulation time 1600467372 ps
CPU time 60.07 seconds
Started Sep 09 09:04:39 PM UTC 24
Finished Sep 09 09:05:40 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102329774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2102329774
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/0.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.1636358794
Short name T57
Test name
Test status
Simulation time 63957577 ps
CPU time 1.16 seconds
Started Sep 09 09:04:52 PM UTC 24
Finished Sep 09 09:04:54 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636358794 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1636358794
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.485507420
Short name T128
Test name
Test status
Simulation time 161642905 ps
CPU time 2.74 seconds
Started Sep 09 09:04:46 PM UTC 24
Finished Sep 09 09:04:50 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485507420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.485507420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.3378432214
Short name T6
Test name
Test status
Simulation time 171336396 ps
CPU time 4.59 seconds
Started Sep 09 09:04:46 PM UTC 24
Finished Sep 09 09:04:52 PM UTC 24
Peak memory 232340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378432214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3378432214
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.2608390761
Short name T203
Test name
Test status
Simulation time 203500198 ps
CPU time 6.39 seconds
Started Sep 09 09:04:45 PM UTC 24
Finished Sep 09 09:04:52 PM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608390761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2608390761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.2773296410
Short name T156
Test name
Test status
Simulation time 931138255 ps
CPU time 4.55 seconds
Started Sep 09 09:04:45 PM UTC 24
Finished Sep 09 09:04:50 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773296410 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2773296410
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.3110870032
Short name T209
Test name
Test status
Simulation time 253751444 ps
CPU time 2.6 seconds
Started Sep 09 09:04:48 PM UTC 24
Finished Sep 09 09:04:52 PM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110870032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3110870032
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3267958123
Short name T199
Test name
Test status
Simulation time 678814535 ps
CPU time 7.04 seconds
Started Sep 09 09:04:45 PM UTC 24
Finished Sep 09 09:04:53 PM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267958123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3267958123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.335741946
Short name T633
Test name
Test status
Simulation time 8107396195 ps
CPU time 194.52 seconds
Started Sep 09 09:04:50 PM UTC 24
Finished Sep 09 09:08:08 PM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335741946 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.335741946
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.3940830426
Short name T27
Test name
Test status
Simulation time 149683107 ps
CPU time 6.34 seconds
Started Sep 09 09:04:47 PM UTC 24
Finished Sep 09 09:04:54 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940830426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3940830426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.3151195627
Short name T59
Test name
Test status
Simulation time 41090980 ps
CPU time 2.18 seconds
Started Sep 09 09:04:50 PM UTC 24
Finished Sep 09 09:04:54 PM UTC 24
Peak memory 219968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151195627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3151195627
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.1639298021
Short name T469
Test name
Test status
Simulation time 16217586 ps
CPU time 1.1 seconds
Started Sep 09 09:06:06 PM UTC 24
Finished Sep 09 09:06:08 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639298021 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1639298021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.3212917489
Short name T254
Test name
Test status
Simulation time 151927229 ps
CPU time 4.01 seconds
Started Sep 09 09:06:02 PM UTC 24
Finished Sep 09 09:06:07 PM UTC 24
Peak memory 232624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212917489 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3212917489
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.3377095618
Short name T30
Test name
Test status
Simulation time 91953924 ps
CPU time 3.26 seconds
Started Sep 09 09:06:03 PM UTC 24
Finished Sep 09 09:06:07 PM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377095618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3377095618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.3090291188
Short name T145
Test name
Test status
Simulation time 362043900 ps
CPU time 3.61 seconds
Started Sep 09 09:06:02 PM UTC 24
Finished Sep 09 09:06:06 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090291188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3090291188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.4087032707
Short name T52
Test name
Test status
Simulation time 90787510 ps
CPU time 3.25 seconds
Started Sep 09 09:06:03 PM UTC 24
Finished Sep 09 09:06:07 PM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087032707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4087032707
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.4004968068
Short name T54
Test name
Test status
Simulation time 9465135088 ps
CPU time 12.25 seconds
Started Sep 09 09:06:03 PM UTC 24
Finished Sep 09 09:06:16 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004968068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4004968068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.3675500536
Short name T417
Test name
Test status
Simulation time 112492833 ps
CPU time 4.29 seconds
Started Sep 09 09:06:03 PM UTC 24
Finished Sep 09 09:06:08 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675500536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3675500536
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_random.2599426839
Short name T387
Test name
Test status
Simulation time 2854710650 ps
CPU time 62.89 seconds
Started Sep 09 09:06:02 PM UTC 24
Finished Sep 09 09:07:06 PM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599426839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2599426839
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.1361701726
Short name T194
Test name
Test status
Simulation time 473384881 ps
CPU time 4.81 seconds
Started Sep 09 09:06:00 PM UTC 24
Finished Sep 09 09:06:06 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361701726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1361701726
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.2820367641
Short name T468
Test name
Test status
Simulation time 62220011 ps
CPU time 4.5 seconds
Started Sep 09 09:06:01 PM UTC 24
Finished Sep 09 09:06:07 PM UTC 24
Peak memory 218328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820367641 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2820367641
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.2638477525
Short name T193
Test name
Test status
Simulation time 276585736 ps
CPU time 3.78 seconds
Started Sep 09 09:06:00 PM UTC 24
Finished Sep 09 09:06:05 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638477525 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2638477525
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.627122242
Short name T195
Test name
Test status
Simulation time 95767852 ps
CPU time 3.71 seconds
Started Sep 09 09:06:01 PM UTC 24
Finished Sep 09 09:06:06 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627122242 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.627122242
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.173759661
Short name T255
Test name
Test status
Simulation time 253642823 ps
CPU time 3.58 seconds
Started Sep 09 09:06:04 PM UTC 24
Finished Sep 09 09:06:09 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173759661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.173759661
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1211201063
Short name T192
Test name
Test status
Simulation time 999211404 ps
CPU time 3.89 seconds
Started Sep 09 09:06:00 PM UTC 24
Finished Sep 09 09:06:05 PM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211201063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1211201063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.3702391984
Short name T539
Test name
Test status
Simulation time 35384400621 ps
CPU time 71.09 seconds
Started Sep 09 09:06:03 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702391984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3702391984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.3796185284
Short name T399
Test name
Test status
Simulation time 134938602 ps
CPU time 3.93 seconds
Started Sep 09 09:06:05 PM UTC 24
Finished Sep 09 09:06:10 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796185284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3796185284
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.1198684555
Short name T473
Test name
Test status
Simulation time 15527700 ps
CPU time 1.13 seconds
Started Sep 09 09:06:14 PM UTC 24
Finished Sep 09 09:06:16 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198684555 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1198684555
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.2978804950
Short name T404
Test name
Test status
Simulation time 41899102 ps
CPU time 4.29 seconds
Started Sep 09 09:06:08 PM UTC 24
Finished Sep 09 09:06:13 PM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978804950 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2978804950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.720446514
Short name T29
Test name
Test status
Simulation time 146359646 ps
CPU time 2.56 seconds
Started Sep 09 09:06:09 PM UTC 24
Finished Sep 09 09:06:13 PM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720446514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.720446514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.2996351563
Short name T361
Test name
Test status
Simulation time 371071421 ps
CPU time 5.44 seconds
Started Sep 09 09:06:08 PM UTC 24
Finished Sep 09 09:06:14 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996351563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2996351563
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.3245656283
Short name T46
Test name
Test status
Simulation time 29501611 ps
CPU time 2.01 seconds
Started Sep 09 09:06:09 PM UTC 24
Finished Sep 09 09:06:12 PM UTC 24
Peak memory 223584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245656283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3245656283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.1186345786
Short name T225
Test name
Test status
Simulation time 113656183 ps
CPU time 3.88 seconds
Started Sep 09 09:06:09 PM UTC 24
Finished Sep 09 09:06:14 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186345786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1186345786
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_random.2766009909
Short name T440
Test name
Test status
Simulation time 2061939120 ps
CPU time 28.93 seconds
Started Sep 09 09:06:08 PM UTC 24
Finished Sep 09 09:06:38 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766009909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2766009909
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.3141823179
Short name T471
Test name
Test status
Simulation time 120612137 ps
CPU time 4.05 seconds
Started Sep 09 09:06:07 PM UTC 24
Finished Sep 09 09:06:13 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141823179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3141823179
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.471891578
Short name T472
Test name
Test status
Simulation time 300104964 ps
CPU time 4.38 seconds
Started Sep 09 09:06:08 PM UTC 24
Finished Sep 09 09:06:13 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471891578 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.471891578
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.485653814
Short name T381
Test name
Test status
Simulation time 1183924813 ps
CPU time 11.35 seconds
Started Sep 09 09:06:08 PM UTC 24
Finished Sep 09 09:06:20 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485653814 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.485653814
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.4217647562
Short name T492
Test name
Test status
Simulation time 1260132002 ps
CPU time 30.48 seconds
Started Sep 09 09:06:08 PM UTC 24
Finished Sep 09 09:06:40 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217647562 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4217647562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.2443084557
Short name T349
Test name
Test status
Simulation time 249541564 ps
CPU time 3.46 seconds
Started Sep 09 09:06:09 PM UTC 24
Finished Sep 09 09:06:14 PM UTC 24
Peak memory 230640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443084557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2443084557
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.2712872236
Short name T470
Test name
Test status
Simulation time 670987807 ps
CPU time 3.77 seconds
Started Sep 09 09:06:07 PM UTC 24
Finished Sep 09 09:06:12 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712872236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2712872236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.3396294938
Short name T206
Test name
Test status
Simulation time 440948786 ps
CPU time 12.89 seconds
Started Sep 09 09:06:11 PM UTC 24
Finished Sep 09 09:06:26 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396294938 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3396294938
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.2416826518
Short name T218
Test name
Test status
Simulation time 2158581985 ps
CPU time 8.1 seconds
Started Sep 09 09:06:10 PM UTC 24
Finished Sep 09 09:06:20 PM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416826518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2416826518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.2855939875
Short name T477
Test name
Test status
Simulation time 43405163 ps
CPU time 1.12 seconds
Started Sep 09 09:06:22 PM UTC 24
Finished Sep 09 09:06:24 PM UTC 24
Peak memory 214128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855939875 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2855939875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.3559164384
Short name T384
Test name
Test status
Simulation time 58839794 ps
CPU time 5.09 seconds
Started Sep 09 09:06:15 PM UTC 24
Finished Sep 09 09:06:21 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559164384 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3559164384
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.2490219804
Short name T33
Test name
Test status
Simulation time 34924747 ps
CPU time 3.22 seconds
Started Sep 09 09:06:19 PM UTC 24
Finished Sep 09 09:06:23 PM UTC 24
Peak memory 228880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490219804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2490219804
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.1421366353
Short name T362
Test name
Test status
Simulation time 172152645 ps
CPU time 5.5 seconds
Started Sep 09 09:06:15 PM UTC 24
Finished Sep 09 09:06:22 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421366353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1421366353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.409858566
Short name T394
Test name
Test status
Simulation time 238844481 ps
CPU time 2.59 seconds
Started Sep 09 09:06:16 PM UTC 24
Finished Sep 09 09:06:20 PM UTC 24
Peak memory 226280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409858566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.409858566
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.1752149234
Short name T217
Test name
Test status
Simulation time 123605659 ps
CPU time 7.57 seconds
Started Sep 09 09:06:15 PM UTC 24
Finished Sep 09 09:06:24 PM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752149234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1752149234
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_random.3459462351
Short name T475
Test name
Test status
Simulation time 168744891 ps
CPU time 5.76 seconds
Started Sep 09 09:06:15 PM UTC 24
Finished Sep 09 09:06:22 PM UTC 24
Peak memory 216172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459462351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3459462351
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.801567558
Short name T270
Test name
Test status
Simulation time 381535537 ps
CPU time 4.26 seconds
Started Sep 09 09:06:14 PM UTC 24
Finished Sep 09 09:06:19 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801567558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.801567558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.3040340613
Short name T476
Test name
Test status
Simulation time 343765370 ps
CPU time 9.18 seconds
Started Sep 09 09:06:14 PM UTC 24
Finished Sep 09 09:06:24 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040340613 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3040340613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.2370851997
Short name T527
Test name
Test status
Simulation time 22661001120 ps
CPU time 54.96 seconds
Started Sep 09 09:06:14 PM UTC 24
Finished Sep 09 09:07:11 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370851997 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2370851997
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.445251879
Short name T474
Test name
Test status
Simulation time 606412647 ps
CPU time 6.64 seconds
Started Sep 09 09:06:14 PM UTC 24
Finished Sep 09 09:06:22 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445251879 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.445251879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.1990298293
Short name T439
Test name
Test status
Simulation time 126749463 ps
CPU time 4.27 seconds
Started Sep 09 09:06:20 PM UTC 24
Finished Sep 09 09:06:25 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990298293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1990298293
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.991261614
Short name T421
Test name
Test status
Simulation time 746935478 ps
CPU time 17.89 seconds
Started Sep 09 09:06:14 PM UTC 24
Finished Sep 09 09:06:33 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991261614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.991261614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.3189501313
Short name T266
Test name
Test status
Simulation time 975869280 ps
CPU time 31.93 seconds
Started Sep 09 09:06:21 PM UTC 24
Finished Sep 09 09:06:54 PM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189501313 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3189501313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.3437134935
Short name T87
Test name
Test status
Simulation time 656994105 ps
CPU time 22.55 seconds
Started Sep 09 09:06:21 PM UTC 24
Finished Sep 09 09:06:45 PM UTC 24
Peak memory 231120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3437134935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg
r_stress_all_with_rand_reset.3437134935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.1266162427
Short name T286
Test name
Test status
Simulation time 737230155 ps
CPU time 18.42 seconds
Started Sep 09 09:06:15 PM UTC 24
Finished Sep 09 09:06:35 PM UTC 24
Peak memory 219964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266162427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1266162427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.3933189361
Short name T178
Test name
Test status
Simulation time 72373074 ps
CPU time 3.44 seconds
Started Sep 09 09:06:21 PM UTC 24
Finished Sep 09 09:06:25 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933189361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3933189361
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.271435752
Short name T482
Test name
Test status
Simulation time 12996255 ps
CPU time 1.17 seconds
Started Sep 09 09:06:27 PM UTC 24
Finished Sep 09 09:06:30 PM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271435752 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.271435752
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.2582635652
Short name T10
Test name
Test status
Simulation time 84662995 ps
CPU time 2.82 seconds
Started Sep 09 09:06:26 PM UTC 24
Finished Sep 09 09:06:30 PM UTC 24
Peak memory 232488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582635652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2582635652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.2242731739
Short name T146
Test name
Test status
Simulation time 49848689 ps
CPU time 2.09 seconds
Started Sep 09 09:06:25 PM UTC 24
Finished Sep 09 09:06:28 PM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242731739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2242731739
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.204859220
Short name T53
Test name
Test status
Simulation time 377689267 ps
CPU time 5.28 seconds
Started Sep 09 09:06:26 PM UTC 24
Finished Sep 09 09:06:32 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204859220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.204859220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.3953415940
Short name T280
Test name
Test status
Simulation time 1348378596 ps
CPU time 4.55 seconds
Started Sep 09 09:06:26 PM UTC 24
Finished Sep 09 09:06:32 PM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953415940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3953415940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.4257221125
Short name T223
Test name
Test status
Simulation time 36908899 ps
CPU time 2.34 seconds
Started Sep 09 09:06:25 PM UTC 24
Finished Sep 09 09:06:28 PM UTC 24
Peak memory 226196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257221125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4257221125
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_random.3291025348
Short name T356
Test name
Test status
Simulation time 564336029 ps
CPU time 4.91 seconds
Started Sep 09 09:06:24 PM UTC 24
Finished Sep 09 09:06:30 PM UTC 24
Peak memory 216044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291025348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3291025348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.3629170161
Short name T343
Test name
Test status
Simulation time 30613992 ps
CPU time 2.7 seconds
Started Sep 09 09:06:22 PM UTC 24
Finished Sep 09 09:06:26 PM UTC 24
Peak memory 217972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629170161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3629170161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.3083343580
Short name T479
Test name
Test status
Simulation time 111661580 ps
CPU time 2.96 seconds
Started Sep 09 09:06:22 PM UTC 24
Finished Sep 09 09:06:26 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083343580 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3083343580
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.3794077571
Short name T480
Test name
Test status
Simulation time 66497635 ps
CPU time 3.27 seconds
Started Sep 09 09:06:22 PM UTC 24
Finished Sep 09 09:06:27 PM UTC 24
Peak memory 217832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794077571 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3794077571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.296456904
Short name T481
Test name
Test status
Simulation time 108855768 ps
CPU time 2.97 seconds
Started Sep 09 09:06:24 PM UTC 24
Finished Sep 09 09:06:28 PM UTC 24
Peak memory 218116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296456904 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.296456904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.1923580590
Short name T335
Test name
Test status
Simulation time 192368106 ps
CPU time 2.89 seconds
Started Sep 09 09:06:26 PM UTC 24
Finished Sep 09 09:06:30 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923580590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1923580590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.4122096231
Short name T478
Test name
Test status
Simulation time 73397301 ps
CPU time 2.94 seconds
Started Sep 09 09:06:22 PM UTC 24
Finished Sep 09 09:06:26 PM UTC 24
Peak memory 215788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122096231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4122096231
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.3791667700
Short name T385
Test name
Test status
Simulation time 261265113 ps
CPU time 9.03 seconds
Started Sep 09 09:06:27 PM UTC 24
Finished Sep 09 09:06:37 PM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791667700 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3791667700
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.987665712
Short name T357
Test name
Test status
Simulation time 510231432 ps
CPU time 6.7 seconds
Started Sep 09 09:06:25 PM UTC 24
Finished Sep 09 09:06:33 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987665712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.987665712
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.2154551455
Short name T486
Test name
Test status
Simulation time 329154079 ps
CPU time 5.46 seconds
Started Sep 09 09:06:27 PM UTC 24
Finished Sep 09 09:06:34 PM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154551455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2154551455
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.1336899947
Short name T488
Test name
Test status
Simulation time 18816360 ps
CPU time 1.05 seconds
Started Sep 09 09:06:34 PM UTC 24
Finished Sep 09 09:06:36 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336899947 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1336899947
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2073527847
Short name T246
Test name
Test status
Simulation time 131502357 ps
CPU time 7.42 seconds
Started Sep 09 09:06:30 PM UTC 24
Finished Sep 09 09:06:39 PM UTC 24
Peak memory 226192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073527847 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2073527847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.2743469329
Short name T485
Test name
Test status
Simulation time 46708906 ps
CPU time 2.49 seconds
Started Sep 09 09:06:30 PM UTC 24
Finished Sep 09 09:06:34 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743469329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2743469329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.2385633022
Short name T418
Test name
Test status
Simulation time 1197634819 ps
CPU time 35.34 seconds
Started Sep 09 09:06:31 PM UTC 24
Finished Sep 09 09:07:08 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385633022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2385633022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.3557107299
Short name T433
Test name
Test status
Simulation time 209608246 ps
CPU time 2.94 seconds
Started Sep 09 09:06:31 PM UTC 24
Finished Sep 09 09:06:35 PM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557107299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3557107299
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_random.690316663
Short name T386
Test name
Test status
Simulation time 203511201 ps
CPU time 7.34 seconds
Started Sep 09 09:06:30 PM UTC 24
Finished Sep 09 09:06:39 PM UTC 24
Peak memory 220088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690316663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.690316663
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.1951758044
Short name T297
Test name
Test status
Simulation time 385786064 ps
CPU time 3.1 seconds
Started Sep 09 09:06:29 PM UTC 24
Finished Sep 09 09:06:33 PM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951758044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1951758044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.1368853168
Short name T484
Test name
Test status
Simulation time 76100211 ps
CPU time 3.21 seconds
Started Sep 09 09:06:29 PM UTC 24
Finished Sep 09 09:06:33 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368853168 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1368853168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.4256395748
Short name T487
Test name
Test status
Simulation time 141698217 ps
CPU time 4.27 seconds
Started Sep 09 09:06:29 PM UTC 24
Finished Sep 09 09:06:34 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256395748 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4256395748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.4039384398
Short name T489
Test name
Test status
Simulation time 217805252 ps
CPU time 7.13 seconds
Started Sep 09 09:06:29 PM UTC 24
Finished Sep 09 09:06:37 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039384398 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4039384398
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.551425037
Short name T491
Test name
Test status
Simulation time 1021707336 ps
CPU time 4.6 seconds
Started Sep 09 09:06:34 PM UTC 24
Finished Sep 09 09:06:39 PM UTC 24
Peak memory 224428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551425037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.551425037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.1404602763
Short name T483
Test name
Test status
Simulation time 20776111 ps
CPU time 2.07 seconds
Started Sep 09 09:06:28 PM UTC 24
Finished Sep 09 09:06:31 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404602763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1404602763
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.799668352
Short name T299
Test name
Test status
Simulation time 43188147 ps
CPU time 2.7 seconds
Started Sep 09 09:06:31 PM UTC 24
Finished Sep 09 09:06:35 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799668352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.799668352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.3229436408
Short name T493
Test name
Test status
Simulation time 242518991 ps
CPU time 7.35 seconds
Started Sep 09 09:06:34 PM UTC 24
Finished Sep 09 09:06:42 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229436408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3229436408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2274521873
Short name T494
Test name
Test status
Simulation time 12757216 ps
CPU time 1.28 seconds
Started Sep 09 09:06:41 PM UTC 24
Finished Sep 09 09:06:43 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274521873 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2274521873
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.2871012730
Short name T143
Test name
Test status
Simulation time 1884454784 ps
CPU time 8.58 seconds
Started Sep 09 09:06:40 PM UTC 24
Finished Sep 09 09:06:49 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871012730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2871012730
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.2098105681
Short name T353
Test name
Test status
Simulation time 655756304 ps
CPU time 6.59 seconds
Started Sep 09 09:06:37 PM UTC 24
Finished Sep 09 09:06:45 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098105681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2098105681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.388655179
Short name T320
Test name
Test status
Simulation time 969847682 ps
CPU time 3.55 seconds
Started Sep 09 09:06:39 PM UTC 24
Finished Sep 09 09:06:43 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388655179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.388655179
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.251220745
Short name T134
Test name
Test status
Simulation time 101330495 ps
CPU time 2.2 seconds
Started Sep 09 09:06:38 PM UTC 24
Finished Sep 09 09:06:42 PM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251220745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.251220745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_random.3098308399
Short name T265
Test name
Test status
Simulation time 331286831 ps
CPU time 5.98 seconds
Started Sep 09 09:06:36 PM UTC 24
Finished Sep 09 09:06:43 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098308399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3098308399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.3472514413
Short name T388
Test name
Test status
Simulation time 505894431 ps
CPU time 4.45 seconds
Started Sep 09 09:06:35 PM UTC 24
Finished Sep 09 09:06:40 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472514413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3472514413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.3860557944
Short name T495
Test name
Test status
Simulation time 919414059 ps
CPU time 6.77 seconds
Started Sep 09 09:06:36 PM UTC 24
Finished Sep 09 09:06:44 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860557944 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3860557944
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.253047321
Short name T522
Test name
Test status
Simulation time 4370889984 ps
CPU time 29.15 seconds
Started Sep 09 09:06:35 PM UTC 24
Finished Sep 09 09:07:05 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253047321 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.253047321
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.3959234474
Short name T351
Test name
Test status
Simulation time 382142135 ps
CPU time 5.19 seconds
Started Sep 09 09:06:36 PM UTC 24
Finished Sep 09 09:06:42 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959234474 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3959234474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2157392643
Short name T497
Test name
Test status
Simulation time 93847804 ps
CPU time 4.2 seconds
Started Sep 09 09:06:40 PM UTC 24
Finished Sep 09 09:06:45 PM UTC 24
Peak memory 220108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157392643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2157392643
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.681477709
Short name T490
Test name
Test status
Simulation time 135039219 ps
CPU time 3 seconds
Started Sep 09 09:06:35 PM UTC 24
Finished Sep 09 09:06:39 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681477709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.681477709
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.3496440766
Short name T98
Test name
Test status
Simulation time 500229287 ps
CPU time 17.52 seconds
Started Sep 09 09:06:40 PM UTC 24
Finished Sep 09 09:06:59 PM UTC 24
Peak memory 232416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3496440766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg
r_stress_all_with_rand_reset.3496440766
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.2570620094
Short name T415
Test name
Test status
Simulation time 542990637 ps
CPU time 5.85 seconds
Started Sep 09 09:06:38 PM UTC 24
Finished Sep 09 09:06:45 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570620094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2570620094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3952511912
Short name T400
Test name
Test status
Simulation time 101444617 ps
CPU time 4.18 seconds
Started Sep 09 09:06:40 PM UTC 24
Finished Sep 09 09:06:45 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952511912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3952511912
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1637928919
Short name T501
Test name
Test status
Simulation time 13789505 ps
CPU time 1.12 seconds
Started Sep 09 09:06:48 PM UTC 24
Finished Sep 09 09:06:50 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637928919 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1637928919
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.2152284403
Short name T403
Test name
Test status
Simulation time 218734169 ps
CPU time 7.29 seconds
Started Sep 09 09:06:45 PM UTC 24
Finished Sep 09 09:06:53 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152284403 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2152284403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.1870064471
Short name T391
Test name
Test status
Simulation time 5977483146 ps
CPU time 11.4 seconds
Started Sep 09 09:06:45 PM UTC 24
Finished Sep 09 09:06:57 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870064471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1870064471
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.952774057
Short name T307
Test name
Test status
Simulation time 270215956 ps
CPU time 5.16 seconds
Started Sep 09 09:06:46 PM UTC 24
Finished Sep 09 09:06:52 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952774057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.952774057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.2553229945
Short name T504
Test name
Test status
Simulation time 306733300 ps
CPU time 4.68 seconds
Started Sep 09 09:06:46 PM UTC 24
Finished Sep 09 09:06:52 PM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553229945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2553229945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.3542918394
Short name T137
Test name
Test status
Simulation time 127056655 ps
CPU time 4.18 seconds
Started Sep 09 09:06:45 PM UTC 24
Finished Sep 09 09:06:50 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542918394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3542918394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_random.1898938098
Short name T506
Test name
Test status
Simulation time 121211968 ps
CPU time 6.64 seconds
Started Sep 09 09:06:44 PM UTC 24
Finished Sep 09 09:06:52 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898938098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1898938098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.394012709
Short name T498
Test name
Test status
Simulation time 762134804 ps
CPU time 2.74 seconds
Started Sep 09 09:06:42 PM UTC 24
Finished Sep 09 09:06:46 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394012709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.394012709
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.753393238
Short name T500
Test name
Test status
Simulation time 379723736 ps
CPU time 4.97 seconds
Started Sep 09 09:06:43 PM UTC 24
Finished Sep 09 09:06:49 PM UTC 24
Peak memory 218200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753393238 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.753393238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.546897730
Short name T523
Test name
Test status
Simulation time 554707272 ps
CPU time 21.92 seconds
Started Sep 09 09:06:43 PM UTC 24
Finished Sep 09 09:07:07 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546897730 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.546897730
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3652694697
Short name T499
Test name
Test status
Simulation time 51789804 ps
CPU time 3.13 seconds
Started Sep 09 09:06:43 PM UTC 24
Finished Sep 09 09:06:48 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652694697 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3652694697
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.96571135
Short name T442
Test name
Test status
Simulation time 527043625 ps
CPU time 4.66 seconds
Started Sep 09 09:06:46 PM UTC 24
Finished Sep 09 09:06:52 PM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96571135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.96571135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.3956613518
Short name T496
Test name
Test status
Simulation time 189543097 ps
CPU time 2.58 seconds
Started Sep 09 09:06:41 PM UTC 24
Finished Sep 09 09:06:45 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956613518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3956613518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.236307258
Short name T502
Test name
Test status
Simulation time 57010079 ps
CPU time 4.71 seconds
Started Sep 09 09:06:45 PM UTC 24
Finished Sep 09 09:06:50 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236307258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.236307258
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.2537981715
Short name T503
Test name
Test status
Simulation time 106372712 ps
CPU time 3.99 seconds
Started Sep 09 09:06:46 PM UTC 24
Finished Sep 09 09:06:51 PM UTC 24
Peak memory 219992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537981715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2537981715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.3374937014
Short name T513
Test name
Test status
Simulation time 43341245 ps
CPU time 1.15 seconds
Started Sep 09 09:06:56 PM UTC 24
Finished Sep 09 09:06:58 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374937014 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3374937014
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.901356404
Short name T247
Test name
Test status
Simulation time 233820276 ps
CPU time 3.63 seconds
Started Sep 09 09:06:53 PM UTC 24
Finished Sep 09 09:06:58 PM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901356404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.901356404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.3443413664
Short name T147
Test name
Test status
Simulation time 153498884 ps
CPU time 2.78 seconds
Started Sep 09 09:06:52 PM UTC 24
Finished Sep 09 09:06:56 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443413664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3443413664
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.2971567138
Short name T43
Test name
Test status
Simulation time 25818735 ps
CPU time 2.43 seconds
Started Sep 09 09:06:53 PM UTC 24
Finished Sep 09 09:06:57 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971567138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2971567138
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.3525231639
Short name T511
Test name
Test status
Simulation time 62928327 ps
CPU time 2.29 seconds
Started Sep 09 09:06:53 PM UTC 24
Finished Sep 09 09:06:56 PM UTC 24
Peak memory 224156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525231639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3525231639
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.2370059466
Short name T138
Test name
Test status
Simulation time 34675535 ps
CPU time 2.44 seconds
Started Sep 09 09:06:53 PM UTC 24
Finished Sep 09 09:06:56 PM UTC 24
Peak memory 218256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370059466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2370059466
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_random.3327861831
Short name T510
Test name
Test status
Simulation time 86629857 ps
CPU time 2.6 seconds
Started Sep 09 09:06:52 PM UTC 24
Finished Sep 09 09:06:55 PM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327861831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3327861831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.1335145366
Short name T516
Test name
Test status
Simulation time 245932988 ps
CPU time 8.23 seconds
Started Sep 09 09:06:50 PM UTC 24
Finished Sep 09 09:07:00 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335145366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1335145366
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.1458220028
Short name T509
Test name
Test status
Simulation time 612692155 ps
CPU time 3.54 seconds
Started Sep 09 09:06:51 PM UTC 24
Finished Sep 09 09:06:55 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458220028 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1458220028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.247447973
Short name T507
Test name
Test status
Simulation time 336467018 ps
CPU time 2.55 seconds
Started Sep 09 09:06:50 PM UTC 24
Finished Sep 09 09:06:54 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247447973 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.247447973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.2156096294
Short name T520
Test name
Test status
Simulation time 710539047 ps
CPU time 11.4 seconds
Started Sep 09 09:06:52 PM UTC 24
Finished Sep 09 09:07:04 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156096294 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2156096294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.2570757921
Short name T314
Test name
Test status
Simulation time 200979039 ps
CPU time 3.91 seconds
Started Sep 09 09:06:54 PM UTC 24
Finished Sep 09 09:06:59 PM UTC 24
Peak memory 224260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570757921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2570757921
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.3435464660
Short name T508
Test name
Test status
Simulation time 466987759 ps
CPU time 3.41 seconds
Started Sep 09 09:06:50 PM UTC 24
Finished Sep 09 09:06:55 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435464660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3435464660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.2330859392
Short name T515
Test name
Test status
Simulation time 761779074 ps
CPU time 4.93 seconds
Started Sep 09 09:06:53 PM UTC 24
Finished Sep 09 09:06:59 PM UTC 24
Peak memory 230164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330859392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2330859392
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.1080753060
Short name T514
Test name
Test status
Simulation time 68703382 ps
CPU time 3 seconds
Started Sep 09 09:06:54 PM UTC 24
Finished Sep 09 09:06:58 PM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080753060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1080753060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.3538970998
Short name T518
Test name
Test status
Simulation time 36010576 ps
CPU time 1.05 seconds
Started Sep 09 09:07:02 PM UTC 24
Finished Sep 09 09:07:04 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538970998 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3538970998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.609068764
Short name T312
Test name
Test status
Simulation time 45059987 ps
CPU time 4.58 seconds
Started Sep 09 09:06:58 PM UTC 24
Finished Sep 09 09:07:04 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609068764 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.609068764
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.1892469158
Short name T148
Test name
Test status
Simulation time 1326161549 ps
CPU time 3.38 seconds
Started Sep 09 09:06:58 PM UTC 24
Finished Sep 09 09:07:03 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892469158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1892469158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_random.1789455789
Short name T517
Test name
Test status
Simulation time 72522371 ps
CPU time 4.22 seconds
Started Sep 09 09:06:58 PM UTC 24
Finished Sep 09 09:07:03 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789455789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1789455789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.557030747
Short name T412
Test name
Test status
Simulation time 30649532 ps
CPU time 3.06 seconds
Started Sep 09 09:06:57 PM UTC 24
Finished Sep 09 09:07:01 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557030747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.557030747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.1101187955
Short name T524
Test name
Test status
Simulation time 182474198 ps
CPU time 7.72 seconds
Started Sep 09 09:06:58 PM UTC 24
Finished Sep 09 09:07:07 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101187955 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1101187955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.895097056
Short name T413
Test name
Test status
Simulation time 60913449 ps
CPU time 3.93 seconds
Started Sep 09 09:06:57 PM UTC 24
Finished Sep 09 09:07:02 PM UTC 24
Peak memory 218324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895097056 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.895097056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.3054421825
Short name T519
Test name
Test status
Simulation time 106460152 ps
CPU time 5.09 seconds
Started Sep 09 09:06:58 PM UTC 24
Finished Sep 09 09:07:04 PM UTC 24
Peak memory 218312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054421825 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3054421825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.2566491082
Short name T358
Test name
Test status
Simulation time 227702937 ps
CPU time 4.6 seconds
Started Sep 09 09:07:01 PM UTC 24
Finished Sep 09 09:07:06 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566491082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2566491082
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.309012496
Short name T410
Test name
Test status
Simulation time 910309902 ps
CPU time 7.79 seconds
Started Sep 09 09:06:56 PM UTC 24
Finished Sep 09 09:07:04 PM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309012496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.309012496
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.2855315603
Short name T149
Test name
Test status
Simulation time 206883648 ps
CPU time 10.05 seconds
Started Sep 09 09:07:01 PM UTC 24
Finished Sep 09 09:07:12 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855315603 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2855315603
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.4199124680
Short name T150
Test name
Test status
Simulation time 493263850 ps
CPU time 18.65 seconds
Started Sep 09 09:07:02 PM UTC 24
Finished Sep 09 09:07:22 PM UTC 24
Peak memory 232300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4199124680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg
r_stress_all_with_rand_reset.4199124680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.1935117338
Short name T249
Test name
Test status
Simulation time 495151437 ps
CPU time 4.92 seconds
Started Sep 09 09:06:59 PM UTC 24
Finished Sep 09 09:07:05 PM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935117338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1935117338
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.1163569596
Short name T521
Test name
Test status
Simulation time 51979204 ps
CPU time 3.32 seconds
Started Sep 09 09:07:01 PM UTC 24
Finished Sep 09 09:07:05 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163569596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1163569596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.3534133748
Short name T525
Test name
Test status
Simulation time 13622282 ps
CPU time 1.33 seconds
Started Sep 09 09:07:08 PM UTC 24
Finished Sep 09 09:07:10 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534133748 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3534133748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.3533744290
Short name T313
Test name
Test status
Simulation time 106846698 ps
CPU time 3.84 seconds
Started Sep 09 09:07:04 PM UTC 24
Finished Sep 09 09:07:09 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533744290 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3533744290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.2855402885
Short name T526
Test name
Test status
Simulation time 294513806 ps
CPU time 3.67 seconds
Started Sep 09 09:07:06 PM UTC 24
Finished Sep 09 09:07:10 PM UTC 24
Peak memory 218556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855402885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2855402885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.3153123516
Short name T319
Test name
Test status
Simulation time 207243034 ps
CPU time 5.09 seconds
Started Sep 09 09:07:04 PM UTC 24
Finished Sep 09 09:07:11 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153123516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3153123516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.698841459
Short name T276
Test name
Test status
Simulation time 31803003 ps
CPU time 2.26 seconds
Started Sep 09 09:07:06 PM UTC 24
Finished Sep 09 09:07:09 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698841459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.698841459
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.435338706
Short name T308
Test name
Test status
Simulation time 556229049 ps
CPU time 4.92 seconds
Started Sep 09 09:07:06 PM UTC 24
Finished Sep 09 09:07:12 PM UTC 24
Peak memory 232212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435338706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.435338706
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_random.2807438631
Short name T420
Test name
Test status
Simulation time 130628103 ps
CPU time 3.67 seconds
Started Sep 09 09:07:04 PM UTC 24
Finished Sep 09 09:07:09 PM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807438631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2807438631
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3078888023
Short name T262
Test name
Test status
Simulation time 487997289 ps
CPU time 4.15 seconds
Started Sep 09 09:07:03 PM UTC 24
Finished Sep 09 09:07:08 PM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078888023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3078888023
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2921064950
Short name T530
Test name
Test status
Simulation time 316689986 ps
CPU time 8.49 seconds
Started Sep 09 09:07:03 PM UTC 24
Finished Sep 09 09:07:13 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921064950 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2921064950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.1043199391
Short name T505
Test name
Test status
Simulation time 67284938 ps
CPU time 3.24 seconds
Started Sep 09 09:07:03 PM UTC 24
Finished Sep 09 09:07:07 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043199391 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1043199391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.2170746467
Short name T369
Test name
Test status
Simulation time 136945613 ps
CPU time 3.6 seconds
Started Sep 09 09:07:03 PM UTC 24
Finished Sep 09 09:07:08 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170746467 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2170746467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.3652905285
Short name T529
Test name
Test status
Simulation time 135895005 ps
CPU time 3.96 seconds
Started Sep 09 09:07:07 PM UTC 24
Finished Sep 09 09:07:12 PM UTC 24
Peak memory 230332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652905285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3652905285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.3145465770
Short name T535
Test name
Test status
Simulation time 4313589814 ps
CPU time 11.38 seconds
Started Sep 09 09:07:02 PM UTC 24
Finished Sep 09 09:07:14 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145465770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3145465770
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.234494925
Short name T185
Test name
Test status
Simulation time 168589904 ps
CPU time 7.13 seconds
Started Sep 09 09:07:07 PM UTC 24
Finished Sep 09 09:07:15 PM UTC 24
Peak memory 232496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=234494925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr
_stress_all_with_rand_reset.234494925
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.3689083589
Short name T534
Test name
Test status
Simulation time 244446720 ps
CPU time 7.18 seconds
Started Sep 09 09:07:06 PM UTC 24
Finished Sep 09 09:07:14 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689083589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3689083589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.1454783125
Short name T528
Test name
Test status
Simulation time 68303689 ps
CPU time 2.79 seconds
Started Sep 09 09:07:07 PM UTC 24
Finished Sep 09 09:07:11 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454783125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1454783125
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1511534784
Short name T58
Test name
Test status
Simulation time 19513111 ps
CPU time 1.49 seconds
Started Sep 09 09:05:00 PM UTC 24
Finished Sep 09 09:05:03 PM UTC 24
Peak memory 213676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511534784 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1511534784
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.4244324738
Short name T37
Test name
Test status
Simulation time 206292240 ps
CPU time 3.7 seconds
Started Sep 09 09:04:56 PM UTC 24
Finished Sep 09 09:05:00 PM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244324738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4244324738
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.1570324205
Short name T101
Test name
Test status
Simulation time 1355987922 ps
CPU time 10.15 seconds
Started Sep 09 09:04:54 PM UTC 24
Finished Sep 09 09:05:05 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570324205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1570324205
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.2157113118
Short name T60
Test name
Test status
Simulation time 144464450 ps
CPU time 3 seconds
Started Sep 09 09:04:56 PM UTC 24
Finished Sep 09 09:05:00 PM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157113118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2157113118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_random.1360411962
Short name T65
Test name
Test status
Simulation time 83425145 ps
CPU time 4.36 seconds
Started Sep 09 09:04:53 PM UTC 24
Finished Sep 09 09:04:58 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360411962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1360411962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.1013679740
Short name T205
Test name
Test status
Simulation time 184005172 ps
CPU time 3.52 seconds
Started Sep 09 09:04:52 PM UTC 24
Finished Sep 09 09:04:56 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013679740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1013679740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.1967390960
Short name T213
Test name
Test status
Simulation time 83019402 ps
CPU time 2.39 seconds
Started Sep 09 09:04:53 PM UTC 24
Finished Sep 09 09:04:56 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967390960 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1967390960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.2286048536
Short name T68
Test name
Test status
Simulation time 3806039279 ps
CPU time 23.13 seconds
Started Sep 09 09:04:53 PM UTC 24
Finished Sep 09 09:05:17 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286048536 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2286048536
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.123441986
Short name T67
Test name
Test status
Simulation time 208323491 ps
CPU time 5.19 seconds
Started Sep 09 09:04:57 PM UTC 24
Finished Sep 09 09:05:03 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123441986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.123441986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.2877579592
Short name T152
Test name
Test status
Simulation time 905585259 ps
CPU time 17.31 seconds
Started Sep 09 09:04:52 PM UTC 24
Finished Sep 09 09:05:10 PM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877579592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2877579592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.2504948291
Short name T303
Test name
Test status
Simulation time 6702153335 ps
CPU time 197.11 seconds
Started Sep 09 09:04:59 PM UTC 24
Finished Sep 09 09:08:19 PM UTC 24
Peak memory 228620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504948291 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2504948291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.3004217854
Short name T102
Test name
Test status
Simulation time 345990455 ps
CPU time 10.78 seconds
Started Sep 09 09:04:54 PM UTC 24
Finished Sep 09 09:05:06 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004217854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3004217854
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.2737646760
Short name T39
Test name
Test status
Simulation time 414143788 ps
CPU time 6.36 seconds
Started Sep 09 09:04:57 PM UTC 24
Finished Sep 09 09:05:04 PM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737646760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2737646760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.1911318747
Short name T538
Test name
Test status
Simulation time 84749561 ps
CPU time 1.25 seconds
Started Sep 09 09:07:13 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911318747 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1911318747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.213501583
Short name T359
Test name
Test status
Simulation time 245593349 ps
CPU time 5.76 seconds
Started Sep 09 09:07:10 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 226340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213501583 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.213501583
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.383369912
Short name T275
Test name
Test status
Simulation time 121122586 ps
CPU time 2.27 seconds
Started Sep 09 09:07:11 PM UTC 24
Finished Sep 09 09:07:14 PM UTC 24
Peak memory 224304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383369912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.383369912
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.3501856122
Short name T540
Test name
Test status
Simulation time 677835380 ps
CPU time 5.38 seconds
Started Sep 09 09:07:10 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501856122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3501856122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_random.1275912485
Short name T336
Test name
Test status
Simulation time 129736595 ps
CPU time 5.04 seconds
Started Sep 09 09:07:10 PM UTC 24
Finished Sep 09 09:07:16 PM UTC 24
Peak memory 230328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275912485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1275912485
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.106374824
Short name T536
Test name
Test status
Simulation time 148694443 ps
CPU time 5.15 seconds
Started Sep 09 09:07:08 PM UTC 24
Finished Sep 09 09:07:15 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106374824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.106374824
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.3074099577
Short name T554
Test name
Test status
Simulation time 628809503 ps
CPU time 16.24 seconds
Started Sep 09 09:07:08 PM UTC 24
Finished Sep 09 09:07:26 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074099577 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3074099577
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.1143520934
Short name T532
Test name
Test status
Simulation time 277511787 ps
CPU time 4.07 seconds
Started Sep 09 09:07:08 PM UTC 24
Finished Sep 09 09:07:13 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143520934 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1143520934
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.2650409475
Short name T531
Test name
Test status
Simulation time 42974722 ps
CPU time 3.33 seconds
Started Sep 09 09:07:08 PM UTC 24
Finished Sep 09 09:07:13 PM UTC 24
Peak memory 218244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650409475 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2650409475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.3668901383
Short name T537
Test name
Test status
Simulation time 40091327 ps
CPU time 2.03 seconds
Started Sep 09 09:07:12 PM UTC 24
Finished Sep 09 09:07:15 PM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668901383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3668901383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.2657217877
Short name T533
Test name
Test status
Simulation time 124249513 ps
CPU time 4.54 seconds
Started Sep 09 09:07:08 PM UTC 24
Finished Sep 09 09:07:14 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657217877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2657217877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.2092084779
Short name T263
Test name
Test status
Simulation time 2055841725 ps
CPU time 48.89 seconds
Started Sep 09 09:07:12 PM UTC 24
Finished Sep 09 09:08:03 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092084779 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2092084779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.2445822535
Short name T151
Test name
Test status
Simulation time 487657667 ps
CPU time 24.84 seconds
Started Sep 09 09:07:12 PM UTC 24
Finished Sep 09 09:07:38 PM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2445822535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg
r_stress_all_with_rand_reset.2445822535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.3758389052
Short name T542
Test name
Test status
Simulation time 303493483 ps
CPU time 6.4 seconds
Started Sep 09 09:07:11 PM UTC 24
Finished Sep 09 09:07:18 PM UTC 24
Peak memory 219928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758389052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3758389052
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.1397669430
Short name T546
Test name
Test status
Simulation time 36090882 ps
CPU time 0.95 seconds
Started Sep 09 09:07:18 PM UTC 24
Finished Sep 09 09:07:20 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397669430 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1397669430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.3598772365
Short name T423
Test name
Test status
Simulation time 388187820 ps
CPU time 7.26 seconds
Started Sep 09 09:07:15 PM UTC 24
Finished Sep 09 09:07:23 PM UTC 24
Peak memory 226100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598772365 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3598772365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.48356540
Short name T183
Test name
Test status
Simulation time 193959333 ps
CPU time 6.64 seconds
Started Sep 09 09:07:16 PM UTC 24
Finished Sep 09 09:07:24 PM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48356540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.48356540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.2854270560
Short name T541
Test name
Test status
Simulation time 29262201 ps
CPU time 1.7 seconds
Started Sep 09 09:07:15 PM UTC 24
Finished Sep 09 09:07:18 PM UTC 24
Peak memory 217612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854270560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2854270560
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.1881530115
Short name T341
Test name
Test status
Simulation time 103326147 ps
CPU time 2.39 seconds
Started Sep 09 09:07:16 PM UTC 24
Finished Sep 09 09:07:20 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881530115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1881530115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.1454005849
Short name T547
Test name
Test status
Simulation time 158349255 ps
CPU time 3.28 seconds
Started Sep 09 09:07:16 PM UTC 24
Finished Sep 09 09:07:21 PM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454005849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1454005849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.210648565
Short name T549
Test name
Test status
Simulation time 116276965 ps
CPU time 3.93 seconds
Started Sep 09 09:07:16 PM UTC 24
Finished Sep 09 09:07:21 PM UTC 24
Peak memory 226564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210648565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.210648565
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_random.2690038348
Short name T360
Test name
Test status
Simulation time 198634530 ps
CPU time 5 seconds
Started Sep 09 09:07:15 PM UTC 24
Finished Sep 09 09:07:21 PM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690038348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2690038348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.142555621
Short name T544
Test name
Test status
Simulation time 301888443 ps
CPU time 4.02 seconds
Started Sep 09 09:07:13 PM UTC 24
Finished Sep 09 09:07:18 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142555621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.142555621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.2807494236
Short name T370
Test name
Test status
Simulation time 33554018 ps
CPU time 2.31 seconds
Started Sep 09 09:07:14 PM UTC 24
Finished Sep 09 09:07:17 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807494236 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2807494236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.4162495499
Short name T552
Test name
Test status
Simulation time 242195335 ps
CPU time 7.95 seconds
Started Sep 09 09:07:13 PM UTC 24
Finished Sep 09 09:07:23 PM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162495499 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4162495499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.1363515944
Short name T545
Test name
Test status
Simulation time 273948716 ps
CPU time 3.06 seconds
Started Sep 09 09:07:15 PM UTC 24
Finished Sep 09 09:07:19 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363515944 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1363515944
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.642967234
Short name T565
Test name
Test status
Simulation time 1476463216 ps
CPU time 13.21 seconds
Started Sep 09 09:07:17 PM UTC 24
Finished Sep 09 09:07:32 PM UTC 24
Peak memory 218028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642967234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.642967234
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.3505037370
Short name T543
Test name
Test status
Simulation time 181151587 ps
CPU time 3.9 seconds
Started Sep 09 09:07:13 PM UTC 24
Finished Sep 09 09:07:18 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505037370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3505037370
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.2574090630
Short name T318
Test name
Test status
Simulation time 6786115932 ps
CPU time 66.34 seconds
Started Sep 09 09:07:17 PM UTC 24
Finished Sep 09 09:08:26 PM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574090630 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2574090630
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.1722311513
Short name T419
Test name
Test status
Simulation time 246491859 ps
CPU time 8.74 seconds
Started Sep 09 09:07:16 PM UTC 24
Finished Sep 09 09:07:26 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722311513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1722311513
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.1261099493
Short name T550
Test name
Test status
Simulation time 109579525 ps
CPU time 2.99 seconds
Started Sep 09 09:07:17 PM UTC 24
Finished Sep 09 09:07:21 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261099493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1261099493
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.428915071
Short name T555
Test name
Test status
Simulation time 34206328 ps
CPU time 1.21 seconds
Started Sep 09 09:07:24 PM UTC 24
Finished Sep 09 09:07:26 PM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428915071 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.428915071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.3302590245
Short name T229
Test name
Test status
Simulation time 4377748146 ps
CPU time 21.65 seconds
Started Sep 09 09:07:22 PM UTC 24
Finished Sep 09 09:07:46 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302590245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3302590245
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.3881158893
Short name T371
Test name
Test status
Simulation time 27466043 ps
CPU time 2.29 seconds
Started Sep 09 09:07:20 PM UTC 24
Finished Sep 09 09:07:24 PM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881158893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3881158893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.1332715494
Short name T393
Test name
Test status
Simulation time 119408293 ps
CPU time 3.18 seconds
Started Sep 09 09:07:22 PM UTC 24
Finished Sep 09 09:07:27 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332715494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1332715494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.3285030116
Short name T405
Test name
Test status
Simulation time 120649797 ps
CPU time 2.66 seconds
Started Sep 09 09:07:22 PM UTC 24
Finished Sep 09 09:07:27 PM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285030116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3285030116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.2166413425
Short name T416
Test name
Test status
Simulation time 186143590 ps
CPU time 3.18 seconds
Started Sep 09 09:07:21 PM UTC 24
Finished Sep 09 09:07:26 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166413425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2166413425
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_random.3968715479
Short name T558
Test name
Test status
Simulation time 313870821 ps
CPU time 6.7 seconds
Started Sep 09 09:07:19 PM UTC 24
Finished Sep 09 09:07:27 PM UTC 24
Peak memory 228460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968715479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3968715479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.62761776
Short name T298
Test name
Test status
Simulation time 802633990 ps
CPU time 5.65 seconds
Started Sep 09 09:07:18 PM UTC 24
Finished Sep 09 09:07:24 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62761776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.62761776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.1751864844
Short name T600
Test name
Test status
Simulation time 1433757735 ps
CPU time 32.8 seconds
Started Sep 09 09:07:19 PM UTC 24
Finished Sep 09 09:07:53 PM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751864844 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1751864844
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.3845696569
Short name T551
Test name
Test status
Simulation time 82009527 ps
CPU time 1.89 seconds
Started Sep 09 09:07:19 PM UTC 24
Finished Sep 09 09:07:22 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845696569 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3845696569
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3767074680
Short name T553
Test name
Test status
Simulation time 111753743 ps
CPU time 3.54 seconds
Started Sep 09 09:07:19 PM UTC 24
Finished Sep 09 09:07:24 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767074680 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3767074680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.328821586
Short name T557
Test name
Test status
Simulation time 56353376 ps
CPU time 2.73 seconds
Started Sep 09 09:07:23 PM UTC 24
Finished Sep 09 09:07:27 PM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328821586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.328821586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.2099556440
Short name T548
Test name
Test status
Simulation time 47133383 ps
CPU time 2.41 seconds
Started Sep 09 09:07:18 PM UTC 24
Finished Sep 09 09:07:21 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099556440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2099556440
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.1228264582
Short name T347
Test name
Test status
Simulation time 1400785243 ps
CPU time 18.15 seconds
Started Sep 09 09:07:23 PM UTC 24
Finished Sep 09 09:07:43 PM UTC 24
Peak memory 232228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228264582 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1228264582
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1776370926
Short name T422
Test name
Test status
Simulation time 116038897 ps
CPU time 5.54 seconds
Started Sep 09 09:07:22 PM UTC 24
Finished Sep 09 09:07:29 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776370926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1776370926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.3968064298
Short name T556
Test name
Test status
Simulation time 56933788 ps
CPU time 2.2 seconds
Started Sep 09 09:07:23 PM UTC 24
Finished Sep 09 09:07:26 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968064298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3968064298
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.115038372
Short name T568
Test name
Test status
Simulation time 9905080 ps
CPU time 1.3 seconds
Started Sep 09 09:07:30 PM UTC 24
Finished Sep 09 09:07:33 PM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115038372 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.115038372
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.1521960831
Short name T287
Test name
Test status
Simulation time 48642854 ps
CPU time 4.72 seconds
Started Sep 09 09:07:25 PM UTC 24
Finished Sep 09 09:07:31 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521960831 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1521960831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.3526006406
Short name T561
Test name
Test status
Simulation time 181983001 ps
CPU time 5.91 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:07:35 PM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526006406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3526006406
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.27494066
Short name T560
Test name
Test status
Simulation time 124714573 ps
CPU time 2.6 seconds
Started Sep 09 09:07:25 PM UTC 24
Finished Sep 09 09:07:29 PM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27494066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.27494066
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.2024405586
Short name T441
Test name
Test status
Simulation time 78340614 ps
CPU time 1.94 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:07:31 PM UTC 24
Peak memory 223584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024405586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2024405586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.3514633780
Short name T342
Test name
Test status
Simulation time 59283812 ps
CPU time 4.33 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:07:33 PM UTC 24
Peak memory 232120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514633780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3514633780
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.2774059969
Short name T562
Test name
Test status
Simulation time 106973481 ps
CPU time 3.49 seconds
Started Sep 09 09:07:26 PM UTC 24
Finished Sep 09 09:07:31 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774059969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2774059969
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_random.3288200510
Short name T564
Test name
Test status
Simulation time 60300532 ps
CPU time 5.05 seconds
Started Sep 09 09:07:25 PM UTC 24
Finished Sep 09 09:07:32 PM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288200510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3288200510
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.1068345073
Short name T377
Test name
Test status
Simulation time 138008931 ps
CPU time 4.92 seconds
Started Sep 09 09:07:24 PM UTC 24
Finished Sep 09 09:07:30 PM UTC 24
Peak memory 218056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068345073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1068345073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.1445807075
Short name T345
Test name
Test status
Simulation time 872397664 ps
CPU time 7.19 seconds
Started Sep 09 09:07:24 PM UTC 24
Finished Sep 09 09:07:32 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445807075 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1445807075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.2547471777
Short name T559
Test name
Test status
Simulation time 113973233 ps
CPU time 3.64 seconds
Started Sep 09 09:07:24 PM UTC 24
Finished Sep 09 09:07:29 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547471777 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2547471777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.3867692967
Short name T587
Test name
Test status
Simulation time 6751459536 ps
CPU time 19.57 seconds
Started Sep 09 09:07:25 PM UTC 24
Finished Sep 09 09:07:46 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867692967 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3867692967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.741830827
Short name T563
Test name
Test status
Simulation time 39060843 ps
CPU time 2.5 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:07:31 PM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741830827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.741830827
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2550654389
Short name T567
Test name
Test status
Simulation time 943183209 ps
CPU time 7.43 seconds
Started Sep 09 09:07:24 PM UTC 24
Finished Sep 09 09:07:33 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550654389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2550654389
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.1747550836
Short name T860
Test name
Test status
Simulation time 8802639495 ps
CPU time 116.93 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:09:27 PM UTC 24
Peak memory 230312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747550836 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1747550836
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.3431747701
Short name T167
Test name
Test status
Simulation time 132516600 ps
CPU time 8.21 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:07:37 PM UTC 24
Peak memory 230768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3431747701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg
r_stress_all_with_rand_reset.3431747701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.1814781464
Short name T566
Test name
Test status
Simulation time 166261472 ps
CPU time 4.38 seconds
Started Sep 09 09:07:26 PM UTC 24
Finished Sep 09 09:07:32 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814781464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1814781464
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.1388131542
Short name T575
Test name
Test status
Simulation time 864351554 ps
CPU time 9.33 seconds
Started Sep 09 09:07:28 PM UTC 24
Finished Sep 09 09:07:38 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388131542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1388131542
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.1256653646
Short name T573
Test name
Test status
Simulation time 18977754 ps
CPU time 1.29 seconds
Started Sep 09 09:07:35 PM UTC 24
Finished Sep 09 09:07:38 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256653646 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1256653646
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.2230731246
Short name T288
Test name
Test status
Simulation time 120998817 ps
CPU time 6.54 seconds
Started Sep 09 09:07:34 PM UTC 24
Finished Sep 09 09:07:41 PM UTC 24
Peak memory 231820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230731246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2230731246
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.1481363132
Short name T338
Test name
Test status
Simulation time 184205119 ps
CPU time 3.39 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:37 PM UTC 24
Peak memory 223728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481363132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1481363132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.1310645176
Short name T576
Test name
Test status
Simulation time 757049317 ps
CPU time 4.6 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:38 PM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310645176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1310645176
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.1785409990
Short name T572
Test name
Test status
Simulation time 165727260 ps
CPU time 3.03 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:37 PM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785409990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1785409990
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.1904586961
Short name T216
Test name
Test status
Simulation time 27481438 ps
CPU time 2.36 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:36 PM UTC 24
Peak memory 217900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904586961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1904586961
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_random.2644671314
Short name T579
Test name
Test status
Simulation time 249603692 ps
CPU time 5.59 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:39 PM UTC 24
Peak memory 224092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644671314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2644671314
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.1816714062
Short name T597
Test name
Test status
Simulation time 641699327 ps
CPU time 19.79 seconds
Started Sep 09 09:07:30 PM UTC 24
Finished Sep 09 09:07:51 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816714062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1816714062
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.2634483606
Short name T570
Test name
Test status
Simulation time 225377837 ps
CPU time 4.46 seconds
Started Sep 09 09:07:31 PM UTC 24
Finished Sep 09 09:07:37 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634483606 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2634483606
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.344921329
Short name T578
Test name
Test status
Simulation time 516178729 ps
CPU time 6.36 seconds
Started Sep 09 09:07:31 PM UTC 24
Finished Sep 09 09:07:39 PM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344921329 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.344921329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.2212676723
Short name T577
Test name
Test status
Simulation time 118656271 ps
CPU time 5.92 seconds
Started Sep 09 09:07:31 PM UTC 24
Finished Sep 09 09:07:39 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212676723 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2212676723
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.1898492160
Short name T574
Test name
Test status
Simulation time 56276073 ps
CPU time 2.97 seconds
Started Sep 09 09:07:34 PM UTC 24
Finished Sep 09 09:07:38 PM UTC 24
Peak memory 228580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898492160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1898492160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.275605592
Short name T569
Test name
Test status
Simulation time 427844857 ps
CPU time 6.29 seconds
Started Sep 09 09:07:30 PM UTC 24
Finished Sep 09 09:07:38 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275605592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.275605592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.1449279439
Short name T339
Test name
Test status
Simulation time 6880958936 ps
CPU time 46.23 seconds
Started Sep 09 09:07:34 PM UTC 24
Finished Sep 09 09:08:22 PM UTC 24
Peak memory 228192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449279439 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1449279439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.3187078363
Short name T186
Test name
Test status
Simulation time 3149304828 ps
CPU time 26.99 seconds
Started Sep 09 09:07:34 PM UTC 24
Finished Sep 09 09:08:02 PM UTC 24
Peak memory 232412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3187078363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymg
r_stress_all_with_rand_reset.3187078363
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.3603666443
Short name T571
Test name
Test status
Simulation time 42532219 ps
CPU time 3.13 seconds
Started Sep 09 09:07:33 PM UTC 24
Finished Sep 09 09:07:37 PM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603666443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3603666443
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1790530542
Short name T585
Test name
Test status
Simulation time 13307732 ps
CPU time 1.27 seconds
Started Sep 09 09:07:43 PM UTC 24
Finished Sep 09 09:07:45 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790530542 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1790530542
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.1168311959
Short name T426
Test name
Test status
Simulation time 142576981 ps
CPU time 8.57 seconds
Started Sep 09 09:07:39 PM UTC 24
Finished Sep 09 09:07:49 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168311959 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1168311959
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.21192536
Short name T588
Test name
Test status
Simulation time 217999563 ps
CPU time 6.81 seconds
Started Sep 09 09:07:40 PM UTC 24
Finished Sep 09 09:07:48 PM UTC 24
Peak memory 218176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21192536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.21192536
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.2516979403
Short name T583
Test name
Test status
Simulation time 435532622 ps
CPU time 3.88 seconds
Started Sep 09 09:07:39 PM UTC 24
Finished Sep 09 09:07:44 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516979403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2516979403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.2351404096
Short name T584
Test name
Test status
Simulation time 265800003 ps
CPU time 3.46 seconds
Started Sep 09 09:07:40 PM UTC 24
Finished Sep 09 09:07:45 PM UTC 24
Peak memory 224300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351404096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2351404096
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.3833864542
Short name T586
Test name
Test status
Simulation time 607242918 ps
CPU time 4.65 seconds
Started Sep 09 09:07:39 PM UTC 24
Finished Sep 09 09:07:45 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833864542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3833864542
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_random.2260800984
Short name T408
Test name
Test status
Simulation time 294477796 ps
CPU time 5.05 seconds
Started Sep 09 09:07:39 PM UTC 24
Finished Sep 09 09:07:45 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260800984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2260800984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.1578679415
Short name T580
Test name
Test status
Simulation time 81444310 ps
CPU time 1.79 seconds
Started Sep 09 09:07:38 PM UTC 24
Finished Sep 09 09:07:42 PM UTC 24
Peak memory 215628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578679415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1578679415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.1675443105
Short name T581
Test name
Test status
Simulation time 149181385 ps
CPU time 3.15 seconds
Started Sep 09 09:07:39 PM UTC 24
Finished Sep 09 09:07:43 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675443105 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1675443105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.3969113653
Short name T620
Test name
Test status
Simulation time 849509562 ps
CPU time 22.61 seconds
Started Sep 09 09:07:38 PM UTC 24
Finished Sep 09 09:08:03 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969113653 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3969113653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.206855719
Short name T590
Test name
Test status
Simulation time 468429388 ps
CPU time 8.71 seconds
Started Sep 09 09:07:39 PM UTC 24
Finished Sep 09 09:07:49 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206855719 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.206855719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.2855768563
Short name T598
Test name
Test status
Simulation time 397857304 ps
CPU time 10.06 seconds
Started Sep 09 09:07:40 PM UTC 24
Finished Sep 09 09:07:52 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855768563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2855768563
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.4095901845
Short name T582
Test name
Test status
Simulation time 223811440 ps
CPU time 5.47 seconds
Started Sep 09 09:07:37 PM UTC 24
Finished Sep 09 09:07:44 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095901845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4095901845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.2443236198
Short name T346
Test name
Test status
Simulation time 511818918 ps
CPU time 4.84 seconds
Started Sep 09 09:07:40 PM UTC 24
Finished Sep 09 09:07:46 PM UTC 24
Peak memory 219932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443236198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2443236198
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.2004111550
Short name T407
Test name
Test status
Simulation time 672083256 ps
CPU time 2.7 seconds
Started Sep 09 09:07:40 PM UTC 24
Finished Sep 09 09:07:44 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004111550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2004111550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.1180208708
Short name T595
Test name
Test status
Simulation time 18187721 ps
CPU time 1.01 seconds
Started Sep 09 09:07:49 PM UTC 24
Finished Sep 09 09:07:51 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180208708 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1180208708
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.168047285
Short name T235
Test name
Test status
Simulation time 672511079 ps
CPU time 4.39 seconds
Started Sep 09 09:07:48 PM UTC 24
Finished Sep 09 09:07:53 PM UTC 24
Peak memory 218556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168047285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.168047285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.2847726535
Short name T594
Test name
Test status
Simulation time 51225214 ps
CPU time 2.39 seconds
Started Sep 09 09:07:46 PM UTC 24
Finished Sep 09 09:07:50 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847726535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2847726535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.2554764989
Short name T49
Test name
Test status
Simulation time 947728022 ps
CPU time 8.37 seconds
Started Sep 09 09:07:47 PM UTC 24
Finished Sep 09 09:07:57 PM UTC 24
Peak memory 231864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554764989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2554764989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.3506898976
Short name T261
Test name
Test status
Simulation time 122072181 ps
CPU time 3.14 seconds
Started Sep 09 09:07:46 PM UTC 24
Finished Sep 09 09:07:50 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506898976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3506898976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_random.3973668161
Short name T599
Test name
Test status
Simulation time 221746707 ps
CPU time 5.7 seconds
Started Sep 09 09:07:46 PM UTC 24
Finished Sep 09 09:07:53 PM UTC 24
Peak memory 224208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973668161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3973668161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.3799254223
Short name T354
Test name
Test status
Simulation time 24291722 ps
CPU time 2.23 seconds
Started Sep 09 09:07:44 PM UTC 24
Finished Sep 09 09:07:47 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799254223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3799254223
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.2557711353
Short name T593
Test name
Test status
Simulation time 42817797 ps
CPU time 3.17 seconds
Started Sep 09 09:07:45 PM UTC 24
Finished Sep 09 09:07:49 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557711353 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2557711353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.3002506723
Short name T592
Test name
Test status
Simulation time 37239309 ps
CPU time 3.22 seconds
Started Sep 09 09:07:45 PM UTC 24
Finished Sep 09 09:07:49 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002506723 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3002506723
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.2417229780
Short name T591
Test name
Test status
Simulation time 34137061 ps
CPU time 2.93 seconds
Started Sep 09 09:07:45 PM UTC 24
Finished Sep 09 09:07:49 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417229780 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2417229780
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.3588052658
Short name T603
Test name
Test status
Simulation time 1336300220 ps
CPU time 5.63 seconds
Started Sep 09 09:07:48 PM UTC 24
Finished Sep 09 09:07:54 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588052658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3588052658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.1799141181
Short name T589
Test name
Test status
Simulation time 251590187 ps
CPU time 3.94 seconds
Started Sep 09 09:07:44 PM UTC 24
Finished Sep 09 09:07:49 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799141181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1799141181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.515466893
Short name T242
Test name
Test status
Simulation time 549110550 ps
CPU time 19.93 seconds
Started Sep 09 09:07:48 PM UTC 24
Finished Sep 09 09:08:09 PM UTC 24
Peak memory 231024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515466893 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.515466893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.2738088058
Short name T372
Test name
Test status
Simulation time 1062994878 ps
CPU time 19 seconds
Started Sep 09 09:07:46 PM UTC 24
Finished Sep 09 09:08:06 PM UTC 24
Peak memory 217972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738088058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2738088058
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.2834413526
Short name T596
Test name
Test status
Simulation time 143753796 ps
CPU time 2.26 seconds
Started Sep 09 09:07:48 PM UTC 24
Finished Sep 09 09:07:51 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834413526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2834413526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.2889600986
Short name T608
Test name
Test status
Simulation time 33407777 ps
CPU time 1.33 seconds
Started Sep 09 09:07:54 PM UTC 24
Finished Sep 09 09:07:56 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889600986 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2889600986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.3891948174
Short name T425
Test name
Test status
Simulation time 6988793665 ps
CPU time 45.17 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891948174 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3891948174
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.3308121235
Short name T613
Test name
Test status
Simulation time 442191866 ps
CPU time 7 seconds
Started Sep 09 09:07:52 PM UTC 24
Finished Sep 09 09:08:00 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308121235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3308121235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.660849890
Short name T409
Test name
Test status
Simulation time 91429149 ps
CPU time 2.75 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:07:54 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660849890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.660849890
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.4099750354
Short name T607
Test name
Test status
Simulation time 208489058 ps
CPU time 3.54 seconds
Started Sep 09 09:07:51 PM UTC 24
Finished Sep 09 09:07:56 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099750354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4099750354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.628442816
Short name T363
Test name
Test status
Simulation time 53672343 ps
CPU time 4.53 seconds
Started Sep 09 09:07:52 PM UTC 24
Finished Sep 09 09:07:57 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628442816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.628442816
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.1521377508
Short name T606
Test name
Test status
Simulation time 2065561262 ps
CPU time 4.31 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:07:56 PM UTC 24
Peak memory 224152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521377508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1521377508
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_random.2515896021
Short name T605
Test name
Test status
Simulation time 303607260 ps
CPU time 4.18 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:07:55 PM UTC 24
Peak memory 218060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515896021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2515896021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.3571254995
Short name T658
Test name
Test status
Simulation time 2586352535 ps
CPU time 29.17 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:08:20 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571254995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3571254995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2137895898
Short name T604
Test name
Test status
Simulation time 208128699 ps
CPU time 3.84 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:07:55 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137895898 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2137895898
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.564044811
Short name T614
Test name
Test status
Simulation time 334943066 ps
CPU time 8.7 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:08:00 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564044811 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.564044811
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.2676121701
Short name T602
Test name
Test status
Simulation time 60562333 ps
CPU time 3.02 seconds
Started Sep 09 09:07:50 PM UTC 24
Finished Sep 09 09:07:54 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676121701 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2676121701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.2200293041
Short name T601
Test name
Test status
Simulation time 198984984 ps
CPU time 4.3 seconds
Started Sep 09 09:07:49 PM UTC 24
Finished Sep 09 09:07:54 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200293041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2200293041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.1812074370
Short name T785
Test name
Test status
Simulation time 10432709373 ps
CPU time 68.22 seconds
Started Sep 09 09:07:54 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812074370 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1812074370
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all_with_rand_reset.3829517629
Short name T187
Test name
Test status
Simulation time 1255875489 ps
CPU time 13.26 seconds
Started Sep 09 09:07:54 PM UTC 24
Finished Sep 09 09:08:08 PM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3829517629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymg
r_stress_all_with_rand_reset.3829517629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.389259054
Short name T610
Test name
Test status
Simulation time 776930865 ps
CPU time 5.89 seconds
Started Sep 09 09:07:51 PM UTC 24
Finished Sep 09 09:07:58 PM UTC 24
Peak memory 230504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389259054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.389259054
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.4259204061
Short name T609
Test name
Test status
Simulation time 35064012 ps
CPU time 2.62 seconds
Started Sep 09 09:07:53 PM UTC 24
Finished Sep 09 09:07:56 PM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259204061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.4259204061
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.1546448669
Short name T611
Test name
Test status
Simulation time 30635066 ps
CPU time 1.44 seconds
Started Sep 09 09:08:00 PM UTC 24
Finished Sep 09 09:08:03 PM UTC 24
Peak memory 213720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546448669 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1546448669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.3267780591
Short name T623
Test name
Test status
Simulation time 652693982 ps
CPU time 7.51 seconds
Started Sep 09 09:07:56 PM UTC 24
Finished Sep 09 09:08:04 PM UTC 24
Peak memory 230264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267780591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3267780591
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.4104914601
Short name T272
Test name
Test status
Simulation time 74381173 ps
CPU time 2.62 seconds
Started Sep 09 09:07:57 PM UTC 24
Finished Sep 09 09:08:00 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104914601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4104914601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.118430162
Short name T273
Test name
Test status
Simulation time 80480236 ps
CPU time 3.63 seconds
Started Sep 09 09:07:57 PM UTC 24
Finished Sep 09 09:08:02 PM UTC 24
Peak memory 224240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118430162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.118430162
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.606967291
Short name T625
Test name
Test status
Simulation time 731535612 ps
CPU time 6.68 seconds
Started Sep 09 09:07:57 PM UTC 24
Finished Sep 09 09:08:04 PM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606967291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.606967291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_random.3829712551
Short name T619
Test name
Test status
Simulation time 381962295 ps
CPU time 4.75 seconds
Started Sep 09 09:07:55 PM UTC 24
Finished Sep 09 09:08:01 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829712551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3829712551
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.893844441
Short name T344
Test name
Test status
Simulation time 254303984 ps
CPU time 3.94 seconds
Started Sep 09 09:07:54 PM UTC 24
Finished Sep 09 09:07:59 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893844441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.893844441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.3630117742
Short name T612
Test name
Test status
Simulation time 30910290 ps
CPU time 2.77 seconds
Started Sep 09 09:07:55 PM UTC 24
Finished Sep 09 09:07:59 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630117742 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3630117742
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.598482657
Short name T615
Test name
Test status
Simulation time 39645359 ps
CPU time 3.36 seconds
Started Sep 09 09:07:55 PM UTC 24
Finished Sep 09 09:08:00 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598482657 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.598482657
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.1295563736
Short name T617
Test name
Test status
Simulation time 61207562 ps
CPU time 4.2 seconds
Started Sep 09 09:07:55 PM UTC 24
Finished Sep 09 09:08:01 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295563736 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1295563736
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.2214273194
Short name T618
Test name
Test status
Simulation time 57576079 ps
CPU time 2.19 seconds
Started Sep 09 09:07:58 PM UTC 24
Finished Sep 09 09:08:01 PM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214273194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2214273194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.3129615577
Short name T616
Test name
Test status
Simulation time 243072761 ps
CPU time 4.65 seconds
Started Sep 09 09:07:54 PM UTC 24
Finished Sep 09 09:08:00 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129615577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3129615577
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.2297384619
Short name T268
Test name
Test status
Simulation time 3895948687 ps
CPU time 30.6 seconds
Started Sep 09 09:07:59 PM UTC 24
Finished Sep 09 09:08:31 PM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297384619 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2297384619
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.1281901428
Short name T647
Test name
Test status
Simulation time 234262585 ps
CPU time 13.96 seconds
Started Sep 09 09:07:59 PM UTC 24
Finished Sep 09 09:08:14 PM UTC 24
Peak memory 230596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1281901428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg
r_stress_all_with_rand_reset.1281901428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.1246677531
Short name T621
Test name
Test status
Simulation time 129039991 ps
CPU time 6.13 seconds
Started Sep 09 09:07:57 PM UTC 24
Finished Sep 09 09:08:04 PM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246677531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1246677531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.4241996101
Short name T660
Test name
Test status
Simulation time 3903436703 ps
CPU time 22.1 seconds
Started Sep 09 09:07:58 PM UTC 24
Finished Sep 09 09:08:21 PM UTC 24
Peak memory 220204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241996101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4241996101
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.3483347304
Short name T631
Test name
Test status
Simulation time 41222674 ps
CPU time 1.08 seconds
Started Sep 09 09:08:06 PM UTC 24
Finished Sep 09 09:08:08 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483347304 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3483347304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.2849317237
Short name T437
Test name
Test status
Simulation time 154499648 ps
CPU time 3.33 seconds
Started Sep 09 09:08:02 PM UTC 24
Finished Sep 09 09:08:06 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849317237 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2849317237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2537515863
Short name T629
Test name
Test status
Simulation time 117848767 ps
CPU time 3.76 seconds
Started Sep 09 09:08:02 PM UTC 24
Finished Sep 09 09:08:06 PM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537515863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2537515863
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.1749064008
Short name T240
Test name
Test status
Simulation time 87241930 ps
CPU time 3.73 seconds
Started Sep 09 09:08:03 PM UTC 24
Finished Sep 09 09:08:08 PM UTC 24
Peak memory 215880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749064008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1749064008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_random.3413371140
Short name T628
Test name
Test status
Simulation time 142910759 ps
CPU time 3.1 seconds
Started Sep 09 09:08:02 PM UTC 24
Finished Sep 09 09:08:06 PM UTC 24
Peak memory 224428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413371140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3413371140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.2502661484
Short name T630
Test name
Test status
Simulation time 537110547 ps
CPU time 5.86 seconds
Started Sep 09 09:08:00 PM UTC 24
Finished Sep 09 09:08:07 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502661484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2502661484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.2472674503
Short name T626
Test name
Test status
Simulation time 53396310 ps
CPU time 3.51 seconds
Started Sep 09 09:08:00 PM UTC 24
Finished Sep 09 09:08:05 PM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472674503 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2472674503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.231606705
Short name T622
Test name
Test status
Simulation time 49739950 ps
CPU time 2.72 seconds
Started Sep 09 09:08:00 PM UTC 24
Finished Sep 09 09:08:04 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231606705 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.231606705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.1600333729
Short name T627
Test name
Test status
Simulation time 295442197 ps
CPU time 3.66 seconds
Started Sep 09 09:08:00 PM UTC 24
Finished Sep 09 09:08:05 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600333729 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1600333729
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3795526587
Short name T632
Test name
Test status
Simulation time 104826158 ps
CPU time 2.54 seconds
Started Sep 09 09:08:04 PM UTC 24
Finished Sep 09 09:08:08 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795526587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3795526587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.1938717392
Short name T624
Test name
Test status
Simulation time 588101522 ps
CPU time 2.94 seconds
Started Sep 09 09:08:00 PM UTC 24
Finished Sep 09 09:08:04 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938717392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1938717392
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.3950535449
Short name T379
Test name
Test status
Simulation time 1766055197 ps
CPU time 32.17 seconds
Started Sep 09 09:08:04 PM UTC 24
Finished Sep 09 09:08:38 PM UTC 24
Peak memory 232296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950535449 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3950535449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.1935429779
Short name T188
Test name
Test status
Simulation time 536695737 ps
CPU time 12.63 seconds
Started Sep 09 09:08:05 PM UTC 24
Finished Sep 09 09:08:19 PM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1935429779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg
r_stress_all_with_rand_reset.1935429779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.3659704427
Short name T638
Test name
Test status
Simulation time 285244646 ps
CPU time 7.96 seconds
Started Sep 09 09:08:03 PM UTC 24
Finished Sep 09 09:08:12 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659704427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3659704427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.2184335724
Short name T640
Test name
Test status
Simulation time 444108405 ps
CPU time 7.53 seconds
Started Sep 09 09:08:04 PM UTC 24
Finished Sep 09 09:08:13 PM UTC 24
Peak memory 219984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184335724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2184335724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.1657467881
Short name T452
Test name
Test status
Simulation time 108817561 ps
CPU time 0.89 seconds
Started Sep 09 09:05:11 PM UTC 24
Finished Sep 09 09:05:13 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657467881 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1657467881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.3505149472
Short name T107
Test name
Test status
Simulation time 92017278 ps
CPU time 4.55 seconds
Started Sep 09 09:05:05 PM UTC 24
Finished Sep 09 09:05:10 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505149472 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3505149472
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.2339226204
Short name T28
Test name
Test status
Simulation time 227519916 ps
CPU time 4.9 seconds
Started Sep 09 09:05:07 PM UTC 24
Finished Sep 09 09:05:13 PM UTC 24
Peak memory 232816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339226204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2339226204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.1445861374
Short name T105
Test name
Test status
Simulation time 35459307 ps
CPU time 2.86 seconds
Started Sep 09 09:05:06 PM UTC 24
Finished Sep 09 09:05:10 PM UTC 24
Peak memory 218056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445861374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1445861374
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.3276594666
Short name T45
Test name
Test status
Simulation time 277689438 ps
CPU time 3.4 seconds
Started Sep 09 09:05:07 PM UTC 24
Finished Sep 09 09:05:11 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276594666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3276594666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.2727973788
Short name T204
Test name
Test status
Simulation time 352710930 ps
CPU time 4.94 seconds
Started Sep 09 09:05:07 PM UTC 24
Finished Sep 09 09:05:13 PM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727973788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2727973788
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.2096142128
Short name T130
Test name
Test status
Simulation time 246794537 ps
CPU time 4.25 seconds
Started Sep 09 09:05:06 PM UTC 24
Finished Sep 09 09:05:11 PM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096142128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2096142128
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_random.4019264645
Short name T153
Test name
Test status
Simulation time 283214488 ps
CPU time 5.77 seconds
Started Sep 09 09:05:03 PM UTC 24
Finished Sep 09 09:05:10 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019264645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4019264645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.2564302256
Short name T41
Test name
Test status
Simulation time 751528453 ps
CPU time 5.46 seconds
Started Sep 09 09:05:10 PM UTC 24
Finished Sep 09 09:05:17 PM UTC 24
Peak memory 256308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564302256 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2564302256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.1202502208
Short name T103
Test name
Test status
Simulation time 139420580 ps
CPU time 3.86 seconds
Started Sep 09 09:05:01 PM UTC 24
Finished Sep 09 09:05:06 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202502208 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1202502208
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.1168559851
Short name T104
Test name
Test status
Simulation time 782164968 ps
CPU time 6.65 seconds
Started Sep 09 09:05:01 PM UTC 24
Finished Sep 09 09:05:09 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168559851 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1168559851
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.1281632314
Short name T258
Test name
Test status
Simulation time 1152241275 ps
CPU time 31.36 seconds
Started Sep 09 09:05:03 PM UTC 24
Finished Sep 09 09:05:36 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281632314 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1281632314
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.4242795892
Short name T154
Test name
Test status
Simulation time 121268346 ps
CPU time 2.68 seconds
Started Sep 09 09:05:09 PM UTC 24
Finished Sep 09 09:05:13 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242795892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4242795892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.1269212862
Short name T100
Test name
Test status
Simulation time 50873063 ps
CPU time 3.79 seconds
Started Sep 09 09:05:00 PM UTC 24
Finished Sep 09 09:05:05 PM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269212862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1269212862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.2392951139
Short name T155
Test name
Test status
Simulation time 105400519 ps
CPU time 5.03 seconds
Started Sep 09 09:05:07 PM UTC 24
Finished Sep 09 09:05:13 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392951139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2392951139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.1246924852
Short name T71
Test name
Test status
Simulation time 62952386 ps
CPU time 2.32 seconds
Started Sep 09 09:05:10 PM UTC 24
Finished Sep 09 09:05:14 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246924852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1246924852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.1206774642
Short name T637
Test name
Test status
Simulation time 12766155 ps
CPU time 1.2 seconds
Started Sep 09 09:08:10 PM UTC 24
Finished Sep 09 09:08:12 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206774642 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1206774642
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.2695533750
Short name T636
Test name
Test status
Simulation time 43989092 ps
CPU time 2.24 seconds
Started Sep 09 09:08:08 PM UTC 24
Finished Sep 09 09:08:12 PM UTC 24
Peak memory 230804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695533750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2695533750
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.3855041564
Short name T302
Test name
Test status
Simulation time 208873385 ps
CPU time 5.68 seconds
Started Sep 09 09:08:07 PM UTC 24
Finished Sep 09 09:08:14 PM UTC 24
Peak memory 219932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855041564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3855041564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.4178888420
Short name T55
Test name
Test status
Simulation time 153935105 ps
CPU time 5.24 seconds
Started Sep 09 09:08:08 PM UTC 24
Finished Sep 09 09:08:15 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178888420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4178888420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.1355532438
Short name T396
Test name
Test status
Simulation time 111935062 ps
CPU time 5.98 seconds
Started Sep 09 09:08:08 PM UTC 24
Finished Sep 09 09:08:15 PM UTC 24
Peak memory 231904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355532438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1355532438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.2153576524
Short name T645
Test name
Test status
Simulation time 227598540 ps
CPU time 4.86 seconds
Started Sep 09 09:08:08 PM UTC 24
Finished Sep 09 09:08:14 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153576524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2153576524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_random.3387912084
Short name T639
Test name
Test status
Simulation time 398060489 ps
CPU time 4.34 seconds
Started Sep 09 09:08:07 PM UTC 24
Finished Sep 09 09:08:12 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387912084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3387912084
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.686866726
Short name T634
Test name
Test status
Simulation time 121100392 ps
CPU time 2.73 seconds
Started Sep 09 09:08:06 PM UTC 24
Finished Sep 09 09:08:09 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686866726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.686866726
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.796141141
Short name T644
Test name
Test status
Simulation time 391424798 ps
CPU time 6.06 seconds
Started Sep 09 09:08:07 PM UTC 24
Finished Sep 09 09:08:14 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796141141 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.796141141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.2341999217
Short name T675
Test name
Test status
Simulation time 801386406 ps
CPU time 18.17 seconds
Started Sep 09 09:08:06 PM UTC 24
Finished Sep 09 09:08:25 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341999217 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2341999217
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.1749689904
Short name T635
Test name
Test status
Simulation time 136861604 ps
CPU time 2.75 seconds
Started Sep 09 09:08:07 PM UTC 24
Finished Sep 09 09:08:11 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749689904 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1749689904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3642485491
Short name T641
Test name
Test status
Simulation time 98074421 ps
CPU time 3.58 seconds
Started Sep 09 09:08:08 PM UTC 24
Finished Sep 09 09:08:13 PM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642485491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3642485491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.482128915
Short name T643
Test name
Test status
Simulation time 211415636 ps
CPU time 6.79 seconds
Started Sep 09 09:08:06 PM UTC 24
Finished Sep 09 09:08:13 PM UTC 24
Peak memory 215732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482128915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.482128915
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.2322407448
Short name T670
Test name
Test status
Simulation time 939299588 ps
CPU time 12.98 seconds
Started Sep 09 09:08:10 PM UTC 24
Finished Sep 09 09:08:24 PM UTC 24
Peak memory 230828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322407448 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2322407448
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.3782339908
Short name T671
Test name
Test status
Simulation time 588954487 ps
CPU time 13.73 seconds
Started Sep 09 09:08:10 PM UTC 24
Finished Sep 09 09:08:25 PM UTC 24
Peak memory 230540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3782339908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg
r_stress_all_with_rand_reset.3782339908
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.614709368
Short name T646
Test name
Test status
Simulation time 85074025 ps
CPU time 4.92 seconds
Started Sep 09 09:08:08 PM UTC 24
Finished Sep 09 09:08:14 PM UTC 24
Peak memory 217972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614709368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.614709368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.1799491420
Short name T642
Test name
Test status
Simulation time 64019013 ps
CPU time 2.74 seconds
Started Sep 09 09:08:10 PM UTC 24
Finished Sep 09 09:08:13 PM UTC 24
Peak memory 218004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799491420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1799491420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.967656105
Short name T652
Test name
Test status
Simulation time 18992766 ps
CPU time 1.03 seconds
Started Sep 09 09:08:16 PM UTC 24
Finished Sep 09 09:08:18 PM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967656105 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.967656105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.2501443519
Short name T449
Test name
Test status
Simulation time 126659104 ps
CPU time 3.59 seconds
Started Sep 09 09:08:13 PM UTC 24
Finished Sep 09 09:08:18 PM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501443519 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2501443519
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.173153173
Short name T662
Test name
Test status
Simulation time 859586200 ps
CPU time 6.23 seconds
Started Sep 09 09:08:15 PM UTC 24
Finished Sep 09 09:08:22 PM UTC 24
Peak memory 230324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173153173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.173153173
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.390587158
Short name T650
Test name
Test status
Simulation time 194158439 ps
CPU time 2.87 seconds
Started Sep 09 09:08:13 PM UTC 24
Finished Sep 09 09:08:17 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390587158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.390587158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.1354621864
Short name T654
Test name
Test status
Simulation time 35085196 ps
CPU time 3.35 seconds
Started Sep 09 09:08:14 PM UTC 24
Finished Sep 09 09:08:19 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354621864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1354621864
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.2764074290
Short name T656
Test name
Test status
Simulation time 91192884 ps
CPU time 3.62 seconds
Started Sep 09 09:08:15 PM UTC 24
Finished Sep 09 09:08:19 PM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764074290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2764074290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.665721209
Short name T231
Test name
Test status
Simulation time 287943705 ps
CPU time 5.59 seconds
Started Sep 09 09:08:14 PM UTC 24
Finished Sep 09 09:08:21 PM UTC 24
Peak memory 232588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665721209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.665721209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_random.3560231644
Short name T267
Test name
Test status
Simulation time 806081489 ps
CPU time 7.83 seconds
Started Sep 09 09:08:13 PM UTC 24
Finished Sep 09 09:08:22 PM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560231644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3560231644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.3991553277
Short name T649
Test name
Test status
Simulation time 263368101 ps
CPU time 4.11 seconds
Started Sep 09 09:08:12 PM UTC 24
Finished Sep 09 09:08:17 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991553277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3991553277
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.1959390057
Short name T764
Test name
Test status
Simulation time 1452736373 ps
CPU time 43.05 seconds
Started Sep 09 09:08:12 PM UTC 24
Finished Sep 09 09:08:56 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959390057 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1959390057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.4239174310
Short name T651
Test name
Test status
Simulation time 164542852 ps
CPU time 4.68 seconds
Started Sep 09 09:08:12 PM UTC 24
Finished Sep 09 09:08:18 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239174310 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4239174310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.1512650122
Short name T655
Test name
Test status
Simulation time 1222864278 ps
CPU time 4.72 seconds
Started Sep 09 09:08:13 PM UTC 24
Finished Sep 09 09:08:19 PM UTC 24
Peak memory 217832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512650122 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1512650122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.2920134495
Short name T653
Test name
Test status
Simulation time 137777827 ps
CPU time 2.73 seconds
Started Sep 09 09:08:15 PM UTC 24
Finished Sep 09 09:08:18 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920134495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2920134495
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.3976728695
Short name T648
Test name
Test status
Simulation time 491876710 ps
CPU time 4.26 seconds
Started Sep 09 09:08:11 PM UTC 24
Finished Sep 09 09:08:16 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976728695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3976728695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.3752391575
Short name T337
Test name
Test status
Simulation time 1062924576 ps
CPU time 35.04 seconds
Started Sep 09 09:08:16 PM UTC 24
Finished Sep 09 09:08:52 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752391575 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3752391575
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.1505836675
Short name T659
Test name
Test status
Simulation time 124084991 ps
CPU time 5.12 seconds
Started Sep 09 09:08:14 PM UTC 24
Finished Sep 09 09:08:21 PM UTC 24
Peak memory 224288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505836675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1505836675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2968057405
Short name T661
Test name
Test status
Simulation time 535282965 ps
CPU time 4.64 seconds
Started Sep 09 09:08:16 PM UTC 24
Finished Sep 09 09:08:22 PM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968057405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2968057405
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.3899418923
Short name T668
Test name
Test status
Simulation time 31574007 ps
CPU time 1.1 seconds
Started Sep 09 09:08:21 PM UTC 24
Finished Sep 09 09:08:23 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899418923 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3899418923
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.3257198439
Short name T424
Test name
Test status
Simulation time 108931714 ps
CPU time 5.68 seconds
Started Sep 09 09:08:18 PM UTC 24
Finished Sep 09 09:08:25 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257198439 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3257198439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.2238282818
Short name T11
Test name
Test status
Simulation time 222441016 ps
CPU time 2.34 seconds
Started Sep 09 09:08:20 PM UTC 24
Finished Sep 09 09:08:23 PM UTC 24
Peak memory 232824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238282818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2238282818
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.1185698807
Short name T665
Test name
Test status
Simulation time 125368959 ps
CPU time 3.32 seconds
Started Sep 09 09:08:18 PM UTC 24
Finished Sep 09 09:08:23 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185698807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1185698807
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1511529724
Short name T672
Test name
Test status
Simulation time 476658500 ps
CPU time 3.82 seconds
Started Sep 09 09:08:20 PM UTC 24
Finished Sep 09 09:08:25 PM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511529724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1511529724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.3361324643
Short name T674
Test name
Test status
Simulation time 403169477 ps
CPU time 4.03 seconds
Started Sep 09 09:08:20 PM UTC 24
Finished Sep 09 09:08:25 PM UTC 24
Peak memory 232300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361324643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3361324643
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3836097515
Short name T673
Test name
Test status
Simulation time 111478836 ps
CPU time 5.16 seconds
Started Sep 09 09:08:19 PM UTC 24
Finished Sep 09 09:08:25 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836097515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3836097515
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_random.1101212190
Short name T731
Test name
Test status
Simulation time 4065382541 ps
CPU time 27.23 seconds
Started Sep 09 09:08:18 PM UTC 24
Finished Sep 09 09:08:47 PM UTC 24
Peak memory 218156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101212190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1101212190
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.1654460503
Short name T666
Test name
Test status
Simulation time 117374067 ps
CPU time 5.86 seconds
Started Sep 09 09:08:16 PM UTC 24
Finished Sep 09 09:08:23 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654460503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1654460503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.2162570918
Short name T664
Test name
Test status
Simulation time 76421456 ps
CPU time 3.87 seconds
Started Sep 09 09:08:17 PM UTC 24
Finished Sep 09 09:08:22 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162570918 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2162570918
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.3398337561
Short name T663
Test name
Test status
Simulation time 76457807 ps
CPU time 3.66 seconds
Started Sep 09 09:08:17 PM UTC 24
Finished Sep 09 09:08:22 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398337561 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3398337561
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.2522348615
Short name T669
Test name
Test status
Simulation time 94797406 ps
CPU time 3.89 seconds
Started Sep 09 09:08:18 PM UTC 24
Finished Sep 09 09:08:23 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522348615 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2522348615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.4248397032
Short name T685
Test name
Test status
Simulation time 1007658889 ps
CPU time 8.62 seconds
Started Sep 09 09:08:20 PM UTC 24
Finished Sep 09 09:08:30 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248397032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4248397032
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.2721106779
Short name T657
Test name
Test status
Simulation time 51479234 ps
CPU time 2.71 seconds
Started Sep 09 09:08:16 PM UTC 24
Finished Sep 09 09:08:20 PM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721106779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2721106779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1459906300
Short name T682
Test name
Test status
Simulation time 4286959843 ps
CPU time 7.92 seconds
Started Sep 09 09:08:20 PM UTC 24
Finished Sep 09 09:08:29 PM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459906300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1459906300
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2543328230
Short name T667
Test name
Test status
Simulation time 171945918 ps
CPU time 2.23 seconds
Started Sep 09 09:08:20 PM UTC 24
Finished Sep 09 09:08:23 PM UTC 24
Peak memory 218368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543328230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2543328230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.4190210567
Short name T677
Test name
Test status
Simulation time 34740334 ps
CPU time 0.96 seconds
Started Sep 09 09:08:25 PM UTC 24
Finished Sep 09 09:08:27 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190210567 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4190210567
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.2597689233
Short name T694
Test name
Test status
Simulation time 807801531 ps
CPU time 8.82 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:34 PM UTC 24
Peak memory 232344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597689233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2597689233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.3179879868
Short name T348
Test name
Test status
Simulation time 37278137 ps
CPU time 2.7 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:28 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179879868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3179879868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.2583466565
Short name T243
Test name
Test status
Simulation time 249200366 ps
CPU time 4.3 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:29 PM UTC 24
Peak memory 230280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583466565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2583466565
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_random.2994765589
Short name T680
Test name
Test status
Simulation time 269321636 ps
CPU time 4.96 seconds
Started Sep 09 09:08:23 PM UTC 24
Finished Sep 09 09:08:29 PM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994765589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2994765589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.196617633
Short name T679
Test name
Test status
Simulation time 84994814 ps
CPU time 4.41 seconds
Started Sep 09 09:08:22 PM UTC 24
Finished Sep 09 09:08:28 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196617633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.196617633
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.2315373470
Short name T678
Test name
Test status
Simulation time 137765614 ps
CPU time 3.74 seconds
Started Sep 09 09:08:23 PM UTC 24
Finished Sep 09 09:08:27 PM UTC 24
Peak memory 218312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315373470 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2315373470
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.1309892959
Short name T753
Test name
Test status
Simulation time 2531634805 ps
CPU time 29.23 seconds
Started Sep 09 09:08:22 PM UTC 24
Finished Sep 09 09:08:53 PM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309892959 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1309892959
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.3830341606
Short name T683
Test name
Test status
Simulation time 155493439 ps
CPU time 5.37 seconds
Started Sep 09 09:08:23 PM UTC 24
Finished Sep 09 09:08:29 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830341606 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3830341606
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.2367009875
Short name T684
Test name
Test status
Simulation time 287590317 ps
CPU time 4.2 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:29 PM UTC 24
Peak memory 228268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367009875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2367009875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.2152003185
Short name T676
Test name
Test status
Simulation time 106130919 ps
CPU time 2.61 seconds
Started Sep 09 09:08:22 PM UTC 24
Finished Sep 09 09:08:26 PM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152003185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2152003185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.4267819950
Short name T706
Test name
Test status
Simulation time 1712651031 ps
CPU time 10.65 seconds
Started Sep 09 09:08:25 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267819950 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4267819950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.2297668240
Short name T698
Test name
Test status
Simulation time 1049832494 ps
CPU time 9.52 seconds
Started Sep 09 09:08:25 PM UTC 24
Finished Sep 09 09:08:36 PM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2297668240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymg
r_stress_all_with_rand_reset.2297668240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.1339077201
Short name T693
Test name
Test status
Simulation time 296135792 ps
CPU time 8.22 seconds
Started Sep 09 09:08:24 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339077201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1339077201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.2389852140
Short name T681
Test name
Test status
Simulation time 98266158 ps
CPU time 2.47 seconds
Started Sep 09 09:08:25 PM UTC 24
Finished Sep 09 09:08:29 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389852140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2389852140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.4270604952
Short name T692
Test name
Test status
Simulation time 16347491 ps
CPU time 1.02 seconds
Started Sep 09 09:08:31 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270604952 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4270604952
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.2426179206
Short name T445
Test name
Test status
Simulation time 48719917 ps
CPU time 4.35 seconds
Started Sep 09 09:08:28 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426179206 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2426179206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.2640468981
Short name T373
Test name
Test status
Simulation time 76183222 ps
CPU time 3.15 seconds
Started Sep 09 09:08:29 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 228460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640468981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2640468981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.2366464080
Short name T689
Test name
Test status
Simulation time 173053532 ps
CPU time 3.28 seconds
Started Sep 09 09:08:28 PM UTC 24
Finished Sep 09 09:08:32 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366464080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2366464080
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.1767446875
Short name T364
Test name
Test status
Simulation time 77134390 ps
CPU time 1.8 seconds
Started Sep 09 09:08:29 PM UTC 24
Finished Sep 09 09:08:32 PM UTC 24
Peak memory 223524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767446875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1767446875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.1779961140
Short name T135
Test name
Test status
Simulation time 66679204 ps
CPU time 3.05 seconds
Started Sep 09 09:08:28 PM UTC 24
Finished Sep 09 09:08:32 PM UTC 24
Peak memory 216028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779961140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1779961140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_random.1924632914
Short name T688
Test name
Test status
Simulation time 193074558 ps
CPU time 3.17 seconds
Started Sep 09 09:08:28 PM UTC 24
Finished Sep 09 09:08:32 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924632914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1924632914
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.1405249766
Short name T687
Test name
Test status
Simulation time 83074248 ps
CPU time 3.73 seconds
Started Sep 09 09:08:27 PM UTC 24
Finished Sep 09 09:08:31 PM UTC 24
Peak memory 215824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405249766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1405249766
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.2836433475
Short name T799
Test name
Test status
Simulation time 3272184942 ps
CPU time 40.28 seconds
Started Sep 09 09:08:27 PM UTC 24
Finished Sep 09 09:09:08 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836433475 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2836433475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.412922011
Short name T686
Test name
Test status
Simulation time 61593352 ps
CPU time 3.18 seconds
Started Sep 09 09:08:27 PM UTC 24
Finished Sep 09 09:08:31 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412922011 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.412922011
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.2550757762
Short name T690
Test name
Test status
Simulation time 66924904 ps
CPU time 4.74 seconds
Started Sep 09 09:08:27 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550757762 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2550757762
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.3569440454
Short name T695
Test name
Test status
Simulation time 112121152 ps
CPU time 2.3 seconds
Started Sep 09 09:08:30 PM UTC 24
Finished Sep 09 09:08:34 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569440454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3569440454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.622827852
Short name T691
Test name
Test status
Simulation time 3565884131 ps
CPU time 4.99 seconds
Started Sep 09 09:08:26 PM UTC 24
Finished Sep 09 09:08:33 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622827852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.622827852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1522632113
Short name T376
Test name
Test status
Simulation time 2863115512 ps
CPU time 22.94 seconds
Started Sep 09 09:08:31 PM UTC 24
Finished Sep 09 09:08:55 PM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522632113 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1522632113
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.3756002091
Short name T710
Test name
Test status
Simulation time 976868003 ps
CPU time 7.72 seconds
Started Sep 09 09:08:29 PM UTC 24
Finished Sep 09 09:08:38 PM UTC 24
Peak memory 228240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756002091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3756002091
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.1006703302
Short name T196
Test name
Test status
Simulation time 653645459 ps
CPU time 2.93 seconds
Started Sep 09 09:08:30 PM UTC 24
Finished Sep 09 09:08:34 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006703302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1006703302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2033674269
Short name T704
Test name
Test status
Simulation time 12660732 ps
CPU time 1.14 seconds
Started Sep 09 09:08:35 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033674269 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2033674269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.999446674
Short name T431
Test name
Test status
Simulation time 178929095 ps
CPU time 8.25 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:42 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999446674 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.999446674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.1398543352
Short name T31
Test name
Test status
Simulation time 47032277 ps
CPU time 2.69 seconds
Started Sep 09 09:08:35 PM UTC 24
Finished Sep 09 09:08:38 PM UTC 24
Peak memory 219944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398543352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1398543352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.2293922757
Short name T702
Test name
Test status
Simulation time 176555965 ps
CPU time 2.61 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293922757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2293922757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3659242407
Short name T322
Test name
Test status
Simulation time 38572821 ps
CPU time 3.04 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 224012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659242407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3659242407
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.3639337
Short name T703
Test name
Test status
Simulation time 238661658 ps
CPU time 2.45 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3639337
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.337709874
Short name T230
Test name
Test status
Simulation time 219126401 ps
CPU time 2.3 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337709874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.337709874
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_random.4168237020
Short name T709
Test name
Test status
Simulation time 166305620 ps
CPU time 3.44 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:38 PM UTC 24
Peak memory 216176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168237020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4168237020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.80230251
Short name T700
Test name
Test status
Simulation time 341606066 ps
CPU time 3.18 seconds
Started Sep 09 09:08:32 PM UTC 24
Finished Sep 09 09:08:36 PM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80230251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.80230251
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.4137620065
Short name T699
Test name
Test status
Simulation time 419476562 ps
CPU time 2.94 seconds
Started Sep 09 09:08:32 PM UTC 24
Finished Sep 09 09:08:36 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137620065 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4137620065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.1585221571
Short name T701
Test name
Test status
Simulation time 74147337 ps
CPU time 3.42 seconds
Started Sep 09 09:08:32 PM UTC 24
Finished Sep 09 09:08:36 PM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585221571 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1585221571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.1345224606
Short name T705
Test name
Test status
Simulation time 174745172 ps
CPU time 3.97 seconds
Started Sep 09 09:08:32 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345224606 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1345224606
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.2471436647
Short name T711
Test name
Test status
Simulation time 49217996 ps
CPU time 2.66 seconds
Started Sep 09 09:08:35 PM UTC 24
Finished Sep 09 09:08:38 PM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471436647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2471436647
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.2877107359
Short name T708
Test name
Test status
Simulation time 649767445 ps
CPU time 5.5 seconds
Started Sep 09 09:08:31 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877107359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2877107359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.2451652589
Short name T227
Test name
Test status
Simulation time 3574596125 ps
CPU time 69.73 seconds
Started Sep 09 09:08:35 PM UTC 24
Finished Sep 09 09:09:46 PM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451652589 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2451652589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.2604134622
Short name T707
Test name
Test status
Simulation time 37170133 ps
CPU time 2.72 seconds
Started Sep 09 09:08:33 PM UTC 24
Finished Sep 09 09:08:37 PM UTC 24
Peak memory 216180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604134622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2604134622
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.2631732444
Short name T712
Test name
Test status
Simulation time 148588067 ps
CPU time 2.59 seconds
Started Sep 09 09:08:35 PM UTC 24
Finished Sep 09 09:08:38 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631732444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2631732444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.3794319688
Short name T719
Test name
Test status
Simulation time 69060406 ps
CPU time 1.2 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794319688 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3794319688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3613951823
Short name T429
Test name
Test status
Simulation time 42989763 ps
CPU time 3.26 seconds
Started Sep 09 09:08:37 PM UTC 24
Finished Sep 09 09:08:42 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613951823 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3613951823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.2433694071
Short name T184
Test name
Test status
Simulation time 63589122 ps
CPU time 2.14 seconds
Started Sep 09 09:08:38 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433694071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2433694071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.2657328196
Short name T722
Test name
Test status
Simulation time 221319801 ps
CPU time 4.16 seconds
Started Sep 09 09:08:37 PM UTC 24
Finished Sep 09 09:08:43 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657328196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2657328196
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.3874620454
Short name T324
Test name
Test status
Simulation time 407672881 ps
CPU time 5.18 seconds
Started Sep 09 09:08:38 PM UTC 24
Finished Sep 09 09:08:44 PM UTC 24
Peak memory 231124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874620454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3874620454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.3378347117
Short name T717
Test name
Test status
Simulation time 46761764 ps
CPU time 2.71 seconds
Started Sep 09 09:08:38 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 230904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378347117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3378347117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.3320054939
Short name T716
Test name
Test status
Simulation time 340981428 ps
CPU time 2.78 seconds
Started Sep 09 09:08:38 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 216156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320054939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3320054939
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_random.1041574586
Short name T715
Test name
Test status
Simulation time 97373693 ps
CPU time 2.39 seconds
Started Sep 09 09:08:37 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 216172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041574586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1041574586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.2197736812
Short name T723
Test name
Test status
Simulation time 168776320 ps
CPU time 5.89 seconds
Started Sep 09 09:08:36 PM UTC 24
Finished Sep 09 09:08:43 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197736812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2197736812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.1807017191
Short name T718
Test name
Test status
Simulation time 63577387 ps
CPU time 3.11 seconds
Started Sep 09 09:08:37 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807017191 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1807017191
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.1904157690
Short name T713
Test name
Test status
Simulation time 43164833 ps
CPU time 2.72 seconds
Started Sep 09 09:08:36 PM UTC 24
Finished Sep 09 09:08:40 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904157690 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1904157690
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.4028787301
Short name T727
Test name
Test status
Simulation time 204647766 ps
CPU time 6.84 seconds
Started Sep 09 09:08:37 PM UTC 24
Finished Sep 09 09:08:45 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028787301 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4028787301
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.1641190655
Short name T774
Test name
Test status
Simulation time 923911235 ps
CPU time 19.56 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:09:00 PM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641190655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1641190655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.2594077845
Short name T714
Test name
Test status
Simulation time 102845264 ps
CPU time 3.52 seconds
Started Sep 09 09:08:36 PM UTC 24
Finished Sep 09 09:08:41 PM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594077845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2594077845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.1526745325
Short name T733
Test name
Test status
Simulation time 1007503759 ps
CPU time 7.51 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:48 PM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526745325 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1526745325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.2426295012
Short name T776
Test name
Test status
Simulation time 640612745 ps
CPU time 20.33 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:09:01 PM UTC 24
Peak memory 232324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2426295012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg
r_stress_all_with_rand_reset.2426295012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.2614396755
Short name T720
Test name
Test status
Simulation time 136682516 ps
CPU time 3.27 seconds
Started Sep 09 09:08:38 PM UTC 24
Finished Sep 09 09:08:42 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614396755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2614396755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.775193792
Short name T180
Test name
Test status
Simulation time 193339900 ps
CPU time 3.22 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:43 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775193792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.775193792
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.1042371403
Short name T728
Test name
Test status
Simulation time 98321212 ps
CPU time 1.03 seconds
Started Sep 09 09:08:44 PM UTC 24
Finished Sep 09 09:08:46 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042371403 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1042371403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.2305279876
Short name T451
Test name
Test status
Simulation time 71494151 ps
CPU time 3.18 seconds
Started Sep 09 09:08:42 PM UTC 24
Finished Sep 09 09:08:46 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305279876 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2305279876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.1184386834
Short name T697
Test name
Test status
Simulation time 193037782 ps
CPU time 2.7 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:08:47 PM UTC 24
Peak memory 228460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184386834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1184386834
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.963613813
Short name T729
Test name
Test status
Simulation time 133597991 ps
CPU time 4.07 seconds
Started Sep 09 09:08:42 PM UTC 24
Finished Sep 09 09:08:47 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963613813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.963613813
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.220286010
Short name T327
Test name
Test status
Simulation time 1208709481 ps
CPU time 6.46 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:08:50 PM UTC 24
Peak memory 230320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220286010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.220286010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.581377516
Short name T735
Test name
Test status
Simulation time 551809984 ps
CPU time 4.04 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:08:48 PM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581377516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.581377516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.152023547
Short name T726
Test name
Test status
Simulation time 29656962 ps
CPU time 2.17 seconds
Started Sep 09 09:08:42 PM UTC 24
Finished Sep 09 09:08:45 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152023547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.152023547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_random.3023301389
Short name T730
Test name
Test status
Simulation time 560288069 ps
CPU time 5.17 seconds
Started Sep 09 09:08:40 PM UTC 24
Finished Sep 09 09:08:47 PM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023301389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3023301389
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.3940933677
Short name T382
Test name
Test status
Simulation time 32390718 ps
CPU time 2.7 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:43 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940933677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3940933677
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.2334950524
Short name T724
Test name
Test status
Simulation time 177927415 ps
CPU time 2.9 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:43 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334950524 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2334950524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.2260360229
Short name T750
Test name
Test status
Simulation time 430693756 ps
CPU time 11 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260360229 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2260360229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.2306576179
Short name T725
Test name
Test status
Simulation time 149222919 ps
CPU time 3.34 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:44 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306576179 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2306576179
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.4250158789
Short name T732
Test name
Test status
Simulation time 67369572 ps
CPU time 3.06 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:08:47 PM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250158789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4250158789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.4127818196
Short name T721
Test name
Test status
Simulation time 24355243 ps
CPU time 1.78 seconds
Started Sep 09 09:08:39 PM UTC 24
Finished Sep 09 09:08:42 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127818196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4127818196
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.3165785331
Short name T808
Test name
Test status
Simulation time 1110425315 ps
CPU time 26.56 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:09:11 PM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165785331 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3165785331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.4201995518
Short name T740
Test name
Test status
Simulation time 199853201 ps
CPU time 4.73 seconds
Started Sep 09 09:08:44 PM UTC 24
Finished Sep 09 09:08:50 PM UTC 24
Peak memory 228580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4201995518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg
r_stress_all_with_rand_reset.4201995518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.1910424139
Short name T741
Test name
Test status
Simulation time 239936618 ps
CPU time 6.24 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:08:50 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910424139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1910424139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.354203592
Short name T744
Test name
Test status
Simulation time 156996119 ps
CPU time 6.36 seconds
Started Sep 09 09:08:43 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354203592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.354203592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.1512329103
Short name T747
Test name
Test status
Simulation time 53335419 ps
CPU time 1.25 seconds
Started Sep 09 09:08:48 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512329103 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1512329103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.2250934273
Short name T752
Test name
Test status
Simulation time 166132731 ps
CPU time 4.42 seconds
Started Sep 09 09:08:47 PM UTC 24
Finished Sep 09 09:08:53 PM UTC 24
Peak memory 228208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250934273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2250934273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.2609360362
Short name T739
Test name
Test status
Simulation time 103633988 ps
CPU time 2.28 seconds
Started Sep 09 09:08:46 PM UTC 24
Finished Sep 09 09:08:49 PM UTC 24
Peak memory 220088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609360362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2609360362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.838940699
Short name T398
Test name
Test status
Simulation time 118805353 ps
CPU time 5.82 seconds
Started Sep 09 09:08:47 PM UTC 24
Finished Sep 09 09:08:54 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838940699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.838940699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.2887870588
Short name T306
Test name
Test status
Simulation time 188427206 ps
CPU time 8.53 seconds
Started Sep 09 09:08:47 PM UTC 24
Finished Sep 09 09:08:57 PM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887870588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2887870588
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.3056144223
Short name T748
Test name
Test status
Simulation time 64493645 ps
CPU time 3.9 seconds
Started Sep 09 09:08:46 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056144223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3056144223
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_random.340336594
Short name T742
Test name
Test status
Simulation time 591966805 ps
CPU time 4.44 seconds
Started Sep 09 09:08:45 PM UTC 24
Finished Sep 09 09:08:50 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340336594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.340336594
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.1316242333
Short name T737
Test name
Test status
Simulation time 40814856 ps
CPU time 2.67 seconds
Started Sep 09 09:08:44 PM UTC 24
Finished Sep 09 09:08:48 PM UTC 24
Peak memory 215816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316242333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1316242333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.2974812709
Short name T746
Test name
Test status
Simulation time 256341454 ps
CPU time 5.09 seconds
Started Sep 09 09:08:45 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974812709 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2974812709
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.1768512519
Short name T736
Test name
Test status
Simulation time 137919904 ps
CPU time 2.47 seconds
Started Sep 09 09:08:44 PM UTC 24
Finished Sep 09 09:08:48 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768512519 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1768512519
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.1096102794
Short name T738
Test name
Test status
Simulation time 87247788 ps
CPU time 2.62 seconds
Started Sep 09 09:08:45 PM UTC 24
Finished Sep 09 09:08:48 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096102794 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1096102794
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.231110207
Short name T745
Test name
Test status
Simulation time 82593989 ps
CPU time 2.45 seconds
Started Sep 09 09:08:47 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231110207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.231110207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.1821806216
Short name T734
Test name
Test status
Simulation time 86332980 ps
CPU time 2.46 seconds
Started Sep 09 09:08:44 PM UTC 24
Finished Sep 09 09:08:48 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821806216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1821806216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.240099794
Short name T749
Test name
Test status
Simulation time 81162817 ps
CPU time 2.67 seconds
Started Sep 09 09:08:47 PM UTC 24
Finished Sep 09 09:08:51 PM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240099794 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.240099794
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.2376251704
Short name T756
Test name
Test status
Simulation time 140745574 ps
CPU time 6.37 seconds
Started Sep 09 09:08:46 PM UTC 24
Finished Sep 09 09:08:53 PM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376251704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2376251704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.908520690
Short name T743
Test name
Test status
Simulation time 129105694 ps
CPU time 1.88 seconds
Started Sep 09 09:08:47 PM UTC 24
Finished Sep 09 09:08:50 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908520690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.908520690
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.4181747986
Short name T757
Test name
Test status
Simulation time 134649533 ps
CPU time 1.13 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:08:54 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181747986 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4181747986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1903270477
Short name T759
Test name
Test status
Simulation time 517302402 ps
CPU time 3.07 seconds
Started Sep 09 09:08:50 PM UTC 24
Finished Sep 09 09:08:54 PM UTC 24
Peak memory 215608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903270477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1903270477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.4206139850
Short name T775
Test name
Test status
Simulation time 282157916 ps
CPU time 7.91 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:09:00 PM UTC 24
Peak memory 230888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206139850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4206139850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.2428210903
Short name T762
Test name
Test status
Simulation time 302545533 ps
CPU time 3.82 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:08:56 PM UTC 24
Peak memory 230444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428210903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2428210903
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.3765415025
Short name T284
Test name
Test status
Simulation time 69526018 ps
CPU time 3.01 seconds
Started Sep 09 09:08:50 PM UTC 24
Finished Sep 09 09:08:54 PM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765415025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3765415025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_random.2206414897
Short name T380
Test name
Test status
Simulation time 279097855 ps
CPU time 8.21 seconds
Started Sep 09 09:08:50 PM UTC 24
Finished Sep 09 09:08:59 PM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206414897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2206414897
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3915195880
Short name T760
Test name
Test status
Simulation time 243522526 ps
CPU time 5.38 seconds
Started Sep 09 09:08:48 PM UTC 24
Finished Sep 09 09:08:55 PM UTC 24
Peak memory 218060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915195880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3915195880
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.655867777
Short name T758
Test name
Test status
Simulation time 964227028 ps
CPU time 3.89 seconds
Started Sep 09 09:08:49 PM UTC 24
Finished Sep 09 09:08:54 PM UTC 24
Peak memory 218272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655867777 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.655867777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.2104233953
Short name T815
Test name
Test status
Simulation time 712804161 ps
CPU time 22.82 seconds
Started Sep 09 09:08:49 PM UTC 24
Finished Sep 09 09:09:13 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104233953 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2104233953
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.626047214
Short name T755
Test name
Test status
Simulation time 153216722 ps
CPU time 3.03 seconds
Started Sep 09 09:08:49 PM UTC 24
Finished Sep 09 09:08:53 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626047214 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.626047214
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.1588289341
Short name T761
Test name
Test status
Simulation time 130061188 ps
CPU time 2.88 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:08:55 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588289341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1588289341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.102373625
Short name T754
Test name
Test status
Simulation time 361125731 ps
CPU time 3.59 seconds
Started Sep 09 09:08:48 PM UTC 24
Finished Sep 09 09:08:53 PM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102373625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.102373625
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.494361659
Short name T763
Test name
Test status
Simulation time 214782378 ps
CPU time 3.72 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:08:56 PM UTC 24
Peak memory 217820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494361659 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.494361659
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.2601859033
Short name T801
Test name
Test status
Simulation time 811338581 ps
CPU time 16 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:09:09 PM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2601859033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymg
r_stress_all_with_rand_reset.2601859033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.3624283562
Short name T332
Test name
Test status
Simulation time 234396355 ps
CPU time 8.06 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:09:00 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624283562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3624283562
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.533183154
Short name T172
Test name
Test status
Simulation time 304667323 ps
CPU time 4.15 seconds
Started Sep 09 09:08:51 PM UTC 24
Finished Sep 09 09:08:56 PM UTC 24
Peak memory 220304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533183154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.533183154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.806287591
Short name T96
Test name
Test status
Simulation time 61318632 ps
CPU time 1.14 seconds
Started Sep 09 09:05:19 PM UTC 24
Finished Sep 09 09:05:21 PM UTC 24
Peak memory 213596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806287591 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.806287591
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.2291805645
Short name T7
Test name
Test status
Simulation time 799981093 ps
CPU time 7.52 seconds
Started Sep 09 09:05:16 PM UTC 24
Finished Sep 09 09:05:25 PM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291805645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2291805645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.3432945444
Short name T91
Test name
Test status
Simulation time 84045845 ps
CPU time 3.04 seconds
Started Sep 09 09:05:14 PM UTC 24
Finished Sep 09 09:05:18 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432945444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3432945444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.1814967754
Short name T93
Test name
Test status
Simulation time 435515405 ps
CPU time 3.52 seconds
Started Sep 09 09:05:15 PM UTC 24
Finished Sep 09 09:05:20 PM UTC 24
Peak memory 224328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814967754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1814967754
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.2368372124
Short name T62
Test name
Test status
Simulation time 259215014 ps
CPU time 3.98 seconds
Started Sep 09 09:05:16 PM UTC 24
Finished Sep 09 09:05:21 PM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368372124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2368372124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2737007377
Short name T92
Test name
Test status
Simulation time 121888100 ps
CPU time 3.05 seconds
Started Sep 09 09:05:14 PM UTC 24
Finished Sep 09 09:05:18 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737007377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2737007377
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_random.3666297974
Short name T94
Test name
Test status
Simulation time 60611282 ps
CPU time 5.15 seconds
Started Sep 09 09:05:14 PM UTC 24
Finished Sep 09 09:05:20 PM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666297974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3666297974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.986112676
Short name T42
Test name
Test status
Simulation time 1401652334 ps
CPU time 15.17 seconds
Started Sep 09 09:05:18 PM UTC 24
Finished Sep 09 09:05:34 PM UTC 24
Peak memory 262312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986112676 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.986112676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.1079808547
Short name T290
Test name
Test status
Simulation time 79368937 ps
CPU time 3.09 seconds
Started Sep 09 09:05:12 PM UTC 24
Finished Sep 09 09:05:16 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079808547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1079808547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.1972296958
Short name T66
Test name
Test status
Simulation time 104455678 ps
CPU time 3.28 seconds
Started Sep 09 09:05:13 PM UTC 24
Finished Sep 09 09:05:17 PM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972296958 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1972296958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.74032680
Short name T212
Test name
Test status
Simulation time 54398658 ps
CPU time 2.65 seconds
Started Sep 09 09:05:12 PM UTC 24
Finished Sep 09 09:05:15 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74032680 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.74032680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.1525910774
Short name T215
Test name
Test status
Simulation time 169601545 ps
CPU time 7.15 seconds
Started Sep 09 09:05:14 PM UTC 24
Finished Sep 09 09:05:22 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525910774 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1525910774
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.1668224984
Short name T95
Test name
Test status
Simulation time 83900755 ps
CPU time 2.29 seconds
Started Sep 09 09:05:17 PM UTC 24
Finished Sep 09 09:05:21 PM UTC 24
Peak memory 216200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668224984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1668224984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.586679716
Short name T455
Test name
Test status
Simulation time 8779961576 ps
CPU time 19.07 seconds
Started Sep 09 09:05:11 PM UTC 24
Finished Sep 09 09:05:32 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586679716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.586679716
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.3917210883
Short name T200
Test name
Test status
Simulation time 132071640 ps
CPU time 7.71 seconds
Started Sep 09 09:05:15 PM UTC 24
Finished Sep 09 09:05:24 PM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917210883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3917210883
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.2047837141
Short name T40
Test name
Test status
Simulation time 253557576 ps
CPU time 3.37 seconds
Started Sep 09 09:05:17 PM UTC 24
Finished Sep 09 09:05:22 PM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047837141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2047837141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.3938169189
Short name T770
Test name
Test status
Simulation time 39925940 ps
CPU time 1.1 seconds
Started Sep 09 09:08:56 PM UTC 24
Finished Sep 09 09:08:59 PM UTC 24
Peak memory 213272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938169189 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3938169189
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.3312716201
Short name T436
Test name
Test status
Simulation time 69770787 ps
CPU time 3.95 seconds
Started Sep 09 09:08:54 PM UTC 24
Finished Sep 09 09:08:59 PM UTC 24
Peak memory 226100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312716201 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3312716201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.718734291
Short name T237
Test name
Test status
Simulation time 93819777 ps
CPU time 3.62 seconds
Started Sep 09 09:08:55 PM UTC 24
Finished Sep 09 09:09:00 PM UTC 24
Peak memory 228484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718734291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.718734291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.3555912386
Short name T767
Test name
Test status
Simulation time 21851464 ps
CPU time 1.86 seconds
Started Sep 09 09:08:54 PM UTC 24
Finished Sep 09 09:08:58 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555912386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3555912386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.744419991
Short name T779
Test name
Test status
Simulation time 620605145 ps
CPU time 5.58 seconds
Started Sep 09 09:08:55 PM UTC 24
Finished Sep 09 09:09:02 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744419991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.744419991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.3714278820
Short name T771
Test name
Test status
Simulation time 32854543 ps
CPU time 2.54 seconds
Started Sep 09 09:08:55 PM UTC 24
Finished Sep 09 09:08:59 PM UTC 24
Peak memory 230728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714278820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3714278820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.2790166367
Short name T773
Test name
Test status
Simulation time 94347130 ps
CPU time 4.22 seconds
Started Sep 09 09:08:54 PM UTC 24
Finished Sep 09 09:09:00 PM UTC 24
Peak memory 230164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790166367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2790166367
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_random.1249703135
Short name T777
Test name
Test status
Simulation time 211544364 ps
CPU time 5.88 seconds
Started Sep 09 09:08:54 PM UTC 24
Finished Sep 09 09:09:01 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249703135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1249703135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.2830898349
Short name T766
Test name
Test status
Simulation time 720419749 ps
CPU time 3.67 seconds
Started Sep 09 09:08:52 PM UTC 24
Finished Sep 09 09:08:57 PM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830898349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2830898349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.3243121298
Short name T823
Test name
Test status
Simulation time 4691914249 ps
CPU time 21.59 seconds
Started Sep 09 09:08:53 PM UTC 24
Finished Sep 09 09:09:16 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243121298 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3243121298
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.1014173653
Short name T765
Test name
Test status
Simulation time 268299346 ps
CPU time 2.96 seconds
Started Sep 09 09:08:53 PM UTC 24
Finished Sep 09 09:08:57 PM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014173653 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1014173653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.96859326
Short name T769
Test name
Test status
Simulation time 61131275 ps
CPU time 2.91 seconds
Started Sep 09 09:08:54 PM UTC 24
Finished Sep 09 09:08:58 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96859326 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.96859326
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.1814184041
Short name T383
Test name
Test status
Simulation time 53260126 ps
CPU time 2.23 seconds
Started Sep 09 09:08:55 PM UTC 24
Finished Sep 09 09:08:59 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814184041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1814184041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.2286162778
Short name T768
Test name
Test status
Simulation time 178353906 ps
CPU time 4.07 seconds
Started Sep 09 09:08:52 PM UTC 24
Finished Sep 09 09:08:58 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286162778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2286162778
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.3465227480
Short name T233
Test name
Test status
Simulation time 746605243 ps
CPU time 27.37 seconds
Started Sep 09 09:08:56 PM UTC 24
Finished Sep 09 09:09:25 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465227480 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3465227480
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2138830429
Short name T828
Test name
Test status
Simulation time 5992375932 ps
CPU time 21.13 seconds
Started Sep 09 09:08:54 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138830429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2138830429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.520521026
Short name T772
Test name
Test status
Simulation time 100343209 ps
CPU time 2.71 seconds
Started Sep 09 09:08:55 PM UTC 24
Finished Sep 09 09:08:59 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520521026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.520521026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.2584068450
Short name T784
Test name
Test status
Simulation time 13371766 ps
CPU time 1.09 seconds
Started Sep 09 09:09:01 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584068450 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2584068450
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.927823451
Short name T292
Test name
Test status
Simulation time 467467890 ps
CPU time 4.8 seconds
Started Sep 09 09:08:58 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927823451 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.927823451
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.2055748599
Short name T224
Test name
Test status
Simulation time 41063643 ps
CPU time 2.28 seconds
Started Sep 09 09:09:00 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055748599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2055748599
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.35712704
Short name T797
Test name
Test status
Simulation time 1331819702 ps
CPU time 7.84 seconds
Started Sep 09 09:08:59 PM UTC 24
Finished Sep 09 09:09:08 PM UTC 24
Peak memory 230524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35712704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.35712704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.785650284
Short name T789
Test name
Test status
Simulation time 256678704 ps
CPU time 3.39 seconds
Started Sep 09 09:09:00 PM UTC 24
Finished Sep 09 09:09:05 PM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785650284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.785650284
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.1225065967
Short name T780
Test name
Test status
Simulation time 155902918 ps
CPU time 2.44 seconds
Started Sep 09 09:08:59 PM UTC 24
Finished Sep 09 09:09:03 PM UTC 24
Peak memory 230184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225065967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1225065967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_random.2072345143
Short name T787
Test name
Test status
Simulation time 159728786 ps
CPU time 5.65 seconds
Started Sep 09 09:08:58 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072345143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2072345143
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.1629993699
Short name T788
Test name
Test status
Simulation time 225918581 ps
CPU time 5.79 seconds
Started Sep 09 09:08:57 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629993699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1629993699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.1407093788
Short name T783
Test name
Test status
Simulation time 630218069 ps
CPU time 4.29 seconds
Started Sep 09 09:08:58 PM UTC 24
Finished Sep 09 09:09:03 PM UTC 24
Peak memory 217944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407093788 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1407093788
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.3261331775
Short name T781
Test name
Test status
Simulation time 111510486 ps
CPU time 3.91 seconds
Started Sep 09 09:08:58 PM UTC 24
Finished Sep 09 09:09:03 PM UTC 24
Peak memory 216176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261331775 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3261331775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.3303391430
Short name T782
Test name
Test status
Simulation time 67131558 ps
CPU time 4.23 seconds
Started Sep 09 09:08:58 PM UTC 24
Finished Sep 09 09:09:03 PM UTC 24
Peak memory 218040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303391430 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3303391430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.1649282675
Short name T751
Test name
Test status
Simulation time 196148994 ps
CPU time 2.75 seconds
Started Sep 09 09:09:00 PM UTC 24
Finished Sep 09 09:09:04 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649282675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1649282675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.2762914457
Short name T791
Test name
Test status
Simulation time 1543208428 ps
CPU time 8.02 seconds
Started Sep 09 09:08:56 PM UTC 24
Finished Sep 09 09:09:06 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762914457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2762914457
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.3391373879
Short name T334
Test name
Test status
Simulation time 1026699663 ps
CPU time 38.67 seconds
Started Sep 09 09:09:00 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391373879 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3391373879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.579661861
Short name T824
Test name
Test status
Simulation time 1905294557 ps
CPU time 15.6 seconds
Started Sep 09 09:08:59 PM UTC 24
Finished Sep 09 09:09:16 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579661861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.579661861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.1996043862
Short name T812
Test name
Test status
Simulation time 648635340 ps
CPU time 10.23 seconds
Started Sep 09 09:09:00 PM UTC 24
Finished Sep 09 09:09:12 PM UTC 24
Peak memory 220036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996043862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1996043862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.2880444990
Short name T794
Test name
Test status
Simulation time 19255024 ps
CPU time 1.09 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:09:07 PM UTC 24
Peak memory 213496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880444990 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2880444990
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.427303035
Short name T795
Test name
Test status
Simulation time 972792192 ps
CPU time 2.78 seconds
Started Sep 09 09:09:03 PM UTC 24
Finished Sep 09 09:09:07 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427303035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.427303035
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.3850852906
Short name T804
Test name
Test status
Simulation time 422195914 ps
CPU time 4.73 seconds
Started Sep 09 09:09:03 PM UTC 24
Finished Sep 09 09:09:09 PM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850852906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3850852906
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.61385395
Short name T806
Test name
Test status
Simulation time 79618328 ps
CPU time 4.02 seconds
Started Sep 09 09:09:04 PM UTC 24
Finished Sep 09 09:09:10 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61385395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.61385395
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.2496507368
Short name T239
Test name
Test status
Simulation time 285619097 ps
CPU time 4.59 seconds
Started Sep 09 09:09:03 PM UTC 24
Finished Sep 09 09:09:09 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496507368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2496507368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_random.2220781955
Short name T802
Test name
Test status
Simulation time 174138815 ps
CPU time 4.46 seconds
Started Sep 09 09:09:03 PM UTC 24
Finished Sep 09 09:09:09 PM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220781955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2220781955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.1173220829
Short name T798
Test name
Test status
Simulation time 835483195 ps
CPU time 5.59 seconds
Started Sep 09 09:09:02 PM UTC 24
Finished Sep 09 09:09:08 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173220829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1173220829
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.1432387866
Short name T800
Test name
Test status
Simulation time 493570956 ps
CPU time 5.67 seconds
Started Sep 09 09:09:02 PM UTC 24
Finished Sep 09 09:09:08 PM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432387866 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1432387866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.1971070733
Short name T793
Test name
Test status
Simulation time 172231633 ps
CPU time 3.97 seconds
Started Sep 09 09:09:02 PM UTC 24
Finished Sep 09 09:09:07 PM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971070733 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1971070733
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.99250998
Short name T792
Test name
Test status
Simulation time 248143106 ps
CPU time 3.26 seconds
Started Sep 09 09:09:02 PM UTC 24
Finished Sep 09 09:09:06 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99250998 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.99250998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.494316827
Short name T796
Test name
Test status
Simulation time 15762249 ps
CPU time 1.76 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:09:07 PM UTC 24
Peak memory 215584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494316827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.494316827
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.1322243069
Short name T790
Test name
Test status
Simulation time 60186195 ps
CPU time 2.91 seconds
Started Sep 09 09:09:02 PM UTC 24
Finished Sep 09 09:09:06 PM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322243069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1322243069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.3582211978
Short name T818
Test name
Test status
Simulation time 455507605 ps
CPU time 8.5 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:09:15 PM UTC 24
Peak memory 232340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3582211978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg
r_stress_all_with_rand_reset.3582211978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.3964235096
Short name T803
Test name
Test status
Simulation time 1517529863 ps
CPU time 4.8 seconds
Started Sep 09 09:09:03 PM UTC 24
Finished Sep 09 09:09:09 PM UTC 24
Peak memory 230244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964235096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3964235096
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.4206155970
Short name T805
Test name
Test status
Simulation time 181533048 ps
CPU time 3.59 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:09:09 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206155970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4206155970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.169614437
Short name T814
Test name
Test status
Simulation time 11299445 ps
CPU time 1.09 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:13 PM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169614437 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.169614437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.207042929
Short name T447
Test name
Test status
Simulation time 1905059527 ps
CPU time 12.15 seconds
Started Sep 09 09:09:06 PM UTC 24
Finished Sep 09 09:09:19 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207042929 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.207042929
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.1268740866
Short name T816
Test name
Test status
Simulation time 131200760 ps
CPU time 3.47 seconds
Started Sep 09 09:09:09 PM UTC 24
Finished Sep 09 09:09:14 PM UTC 24
Peak memory 232976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268740866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1268740866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.223310704
Short name T883
Test name
Test status
Simulation time 849219726 ps
CPU time 26.44 seconds
Started Sep 09 09:09:07 PM UTC 24
Finished Sep 09 09:09:35 PM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223310704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.223310704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.1416706479
Short name T367
Test name
Test status
Simulation time 418533743 ps
CPU time 4.74 seconds
Started Sep 09 09:09:07 PM UTC 24
Finished Sep 09 09:09:13 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416706479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1416706479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1865948849
Short name T820
Test name
Test status
Simulation time 455802872 ps
CPU time 4.63 seconds
Started Sep 09 09:09:09 PM UTC 24
Finished Sep 09 09:09:15 PM UTC 24
Peak memory 230528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865948849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1865948849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.3802412167
Short name T811
Test name
Test status
Simulation time 38894294 ps
CPU time 2.99 seconds
Started Sep 09 09:09:07 PM UTC 24
Finished Sep 09 09:09:11 PM UTC 24
Peak memory 230584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802412167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3802412167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_random.302732650
Short name T807
Test name
Test status
Simulation time 156063700 ps
CPU time 3.35 seconds
Started Sep 09 09:09:06 PM UTC 24
Finished Sep 09 09:09:11 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302732650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.302732650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.2482279304
Short name T880
Test name
Test status
Simulation time 5409111176 ps
CPU time 27.32 seconds
Started Sep 09 09:09:06 PM UTC 24
Finished Sep 09 09:09:35 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482279304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2482279304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.2750455762
Short name T840
Test name
Test status
Simulation time 472197860 ps
CPU time 13.46 seconds
Started Sep 09 09:09:06 PM UTC 24
Finished Sep 09 09:09:21 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750455762 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2750455762
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.1463888270
Short name T809
Test name
Test status
Simulation time 306263390 ps
CPU time 4.12 seconds
Started Sep 09 09:09:06 PM UTC 24
Finished Sep 09 09:09:11 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463888270 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1463888270
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.3504142504
Short name T837
Test name
Test status
Simulation time 468084555 ps
CPU time 12.9 seconds
Started Sep 09 09:09:06 PM UTC 24
Finished Sep 09 09:09:20 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504142504 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3504142504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.2612567179
Short name T813
Test name
Test status
Simulation time 29108956 ps
CPU time 2.67 seconds
Started Sep 09 09:09:09 PM UTC 24
Finished Sep 09 09:09:13 PM UTC 24
Peak memory 218084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612567179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2612567179
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.4147009026
Short name T810
Test name
Test status
Simulation time 297178226 ps
CPU time 5.27 seconds
Started Sep 09 09:09:05 PM UTC 24
Finished Sep 09 09:09:11 PM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147009026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.4147009026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.731980769
Short name T858
Test name
Test status
Simulation time 2547514061 ps
CPU time 16.76 seconds
Started Sep 09 09:09:09 PM UTC 24
Finished Sep 09 09:09:27 PM UTC 24
Peak memory 230312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731980769 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.731980769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.3476000123
Short name T825
Test name
Test status
Simulation time 4954117581 ps
CPU time 7.51 seconds
Started Sep 09 09:09:07 PM UTC 24
Finished Sep 09 09:09:16 PM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476000123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3476000123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.2498899906
Short name T817
Test name
Test status
Simulation time 344763931 ps
CPU time 3.67 seconds
Started Sep 09 09:09:09 PM UTC 24
Finished Sep 09 09:09:14 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498899906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2498899906
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.1603159245
Short name T826
Test name
Test status
Simulation time 14677785 ps
CPU time 1.16 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603159245 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1603159245
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.369156279
Short name T245
Test name
Test status
Simulation time 784439556 ps
CPU time 35.05 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:47 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369156279 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.369156279
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.1493350152
Short name T830
Test name
Test status
Simulation time 79568830 ps
CPU time 2.74 seconds
Started Sep 09 09:09:13 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 218348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493350152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1493350152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.149150246
Short name T819
Test name
Test status
Simulation time 40642155 ps
CPU time 2.66 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:15 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149150246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.149150246
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1950117496
Short name T835
Test name
Test status
Simulation time 664488354 ps
CPU time 6.43 seconds
Started Sep 09 09:09:12 PM UTC 24
Finished Sep 09 09:09:19 PM UTC 24
Peak memory 224036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950117496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1950117496
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.4222760989
Short name T831
Test name
Test status
Simulation time 1177711123 ps
CPU time 3.32 seconds
Started Sep 09 09:09:13 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222760989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4222760989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.1870603895
Short name T822
Test name
Test status
Simulation time 93106715 ps
CPU time 3.27 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:15 PM UTC 24
Peak memory 224152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870603895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1870603895
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_random.298382133
Short name T832
Test name
Test status
Simulation time 251220487 ps
CPU time 5.65 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298382133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.298382133
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.2774776028
Short name T873
Test name
Test status
Simulation time 2839312004 ps
CPU time 19.05 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:31 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774776028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2774776028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.1727617890
Short name T833
Test name
Test status
Simulation time 507356030 ps
CPU time 5.86 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:18 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727617890 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1727617890
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.1930224057
Short name T839
Test name
Test status
Simulation time 446267240 ps
CPU time 8.87 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:21 PM UTC 24
Peak memory 218268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930224057 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1930224057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.3443234610
Short name T827
Test name
Test status
Simulation time 485147363 ps
CPU time 5.16 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443234610 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3443234610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.2854661650
Short name T330
Test name
Test status
Simulation time 80776188 ps
CPU time 3.61 seconds
Started Sep 09 09:09:13 PM UTC 24
Finished Sep 09 09:09:18 PM UTC 24
Peak memory 224092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854661650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2854661650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.2004186380
Short name T821
Test name
Test status
Simulation time 1037475823 ps
CPU time 3.52 seconds
Started Sep 09 09:09:10 PM UTC 24
Finished Sep 09 09:09:15 PM UTC 24
Peak memory 218264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004186380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2004186380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.1935828680
Short name T841
Test name
Test status
Simulation time 151064940 ps
CPU time 5.54 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:09:21 PM UTC 24
Peak memory 219968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935828680 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1935828680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.3503627426
Short name T854
Test name
Test status
Simulation time 509043770 ps
CPU time 13.59 seconds
Started Sep 09 09:09:12 PM UTC 24
Finished Sep 09 09:09:26 PM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503627426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3503627426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.1072495828
Short name T829
Test name
Test status
Simulation time 281822689 ps
CPU time 2.92 seconds
Started Sep 09 09:09:13 PM UTC 24
Finished Sep 09 09:09:17 PM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072495828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1072495828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.1997257766
Short name T838
Test name
Test status
Simulation time 19937999 ps
CPU time 1.1 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:21 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997257766 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1997257766
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.3159233271
Short name T450
Test name
Test status
Simulation time 1261758273 ps
CPU time 59.04 seconds
Started Sep 09 09:09:16 PM UTC 24
Finished Sep 09 09:10:16 PM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159233271 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3159233271
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.3700173901
Short name T786
Test name
Test status
Simulation time 482659468 ps
CPU time 4.37 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:24 PM UTC 24
Peak memory 231964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700173901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3700173901
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.696019003
Short name T844
Test name
Test status
Simulation time 60463414 ps
CPU time 3.56 seconds
Started Sep 09 09:09:17 PM UTC 24
Finished Sep 09 09:09:21 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696019003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.696019003
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.3672729209
Short name T845
Test name
Test status
Simulation time 166917249 ps
CPU time 3.93 seconds
Started Sep 09 09:09:17 PM UTC 24
Finished Sep 09 09:09:22 PM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672729209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3672729209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.1558959527
Short name T852
Test name
Test status
Simulation time 353472162 ps
CPU time 5.38 seconds
Started Sep 09 09:09:17 PM UTC 24
Finished Sep 09 09:09:23 PM UTC 24
Peak memory 232120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558959527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1558959527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.3030172529
Short name T256
Test name
Test status
Simulation time 399879048 ps
CPU time 6.9 seconds
Started Sep 09 09:09:17 PM UTC 24
Finished Sep 09 09:09:25 PM UTC 24
Peak memory 218300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030172529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3030172529
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_random.3475386481
Short name T857
Test name
Test status
Simulation time 317817332 ps
CPU time 10.24 seconds
Started Sep 09 09:09:16 PM UTC 24
Finished Sep 09 09:09:27 PM UTC 24
Peak memory 226120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475386481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3475386481
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.4164430794
Short name T834
Test name
Test status
Simulation time 39888139 ps
CPU time 2.43 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:09:18 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164430794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4164430794
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.2313818100
Short name T917
Test name
Test status
Simulation time 1774715943 ps
CPU time 51.33 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:10:07 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313818100 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2313818100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.2436042036
Short name T836
Test name
Test status
Simulation time 413709049 ps
CPU time 4.56 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:09:20 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436042036 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2436042036
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.3202560841
Short name T842
Test name
Test status
Simulation time 103352642 ps
CPU time 4.46 seconds
Started Sep 09 09:09:15 PM UTC 24
Finished Sep 09 09:09:21 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202560841 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3202560841
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.3085965800
Short name T848
Test name
Test status
Simulation time 914300494 ps
CPU time 2.96 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:22 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085965800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3085965800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.2001418955
Short name T895
Test name
Test status
Simulation time 1446968028 ps
CPU time 22.98 seconds
Started Sep 09 09:09:14 PM UTC 24
Finished Sep 09 09:09:39 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001418955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2001418955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.2287453924
Short name T910
Test name
Test status
Simulation time 1184355489 ps
CPU time 27.29 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:47 PM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287453924 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2287453924
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.254565891
Short name T849
Test name
Test status
Simulation time 565733740 ps
CPU time 4.64 seconds
Started Sep 09 09:09:17 PM UTC 24
Finished Sep 09 09:09:23 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254565891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.254565891
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.3192789474
Short name T850
Test name
Test status
Simulation time 78544095 ps
CPU time 3.52 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:23 PM UTC 24
Peak memory 219976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192789474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3192789474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.3360995353
Short name T853
Test name
Test status
Simulation time 64158430 ps
CPU time 1.36 seconds
Started Sep 09 09:09:24 PM UTC 24
Finished Sep 09 09:09:26 PM UTC 24
Peak memory 213720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360995353 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3360995353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.135388861
Short name T444
Test name
Test status
Simulation time 1004328913 ps
CPU time 11.95 seconds
Started Sep 09 09:09:21 PM UTC 24
Finished Sep 09 09:09:34 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135388861 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.135388861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.4037817911
Short name T862
Test name
Test status
Simulation time 255660411 ps
CPU time 4.8 seconds
Started Sep 09 09:09:22 PM UTC 24
Finished Sep 09 09:09:28 PM UTC 24
Peak memory 224204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037817911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.4037817911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.417802415
Short name T864
Test name
Test status
Simulation time 294139088 ps
CPU time 6.45 seconds
Started Sep 09 09:09:21 PM UTC 24
Finished Sep 09 09:09:28 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417802415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.417802415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.2426379466
Short name T50
Test name
Test status
Simulation time 117800692 ps
CPU time 4.81 seconds
Started Sep 09 09:09:22 PM UTC 24
Finished Sep 09 09:09:28 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426379466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2426379466
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.932502644
Short name T855
Test name
Test status
Simulation time 135110724 ps
CPU time 3.36 seconds
Started Sep 09 09:09:22 PM UTC 24
Finished Sep 09 09:09:27 PM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932502644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.932502644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.2635785075
Short name T136
Test name
Test status
Simulation time 100589725 ps
CPU time 4.26 seconds
Started Sep 09 09:09:21 PM UTC 24
Finished Sep 09 09:09:26 PM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635785075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2635785075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_random.1871049871
Short name T843
Test name
Test status
Simulation time 181197672 ps
CPU time 4.18 seconds
Started Sep 09 09:09:21 PM UTC 24
Finished Sep 09 09:09:26 PM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871049871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1871049871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.1196394599
Short name T908
Test name
Test status
Simulation time 1179299124 ps
CPU time 22.28 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:42 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196394599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1196394599
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.3024073479
Short name T847
Test name
Test status
Simulation time 116958052 ps
CPU time 2.4 seconds
Started Sep 09 09:09:19 PM UTC 24
Finished Sep 09 09:09:22 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024073479 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3024073479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.3475420155
Short name T846
Test name
Test status
Simulation time 32386695 ps
CPU time 2.31 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:22 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475420155 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3475420155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.134919672
Short name T851
Test name
Test status
Simulation time 95275124 ps
CPU time 2.22 seconds
Started Sep 09 09:09:20 PM UTC 24
Finished Sep 09 09:09:23 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134919672 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.134919672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.730523065
Short name T856
Test name
Test status
Simulation time 45444597 ps
CPU time 3.57 seconds
Started Sep 09 09:09:22 PM UTC 24
Finished Sep 09 09:09:27 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730523065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.730523065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.814193370
Short name T890
Test name
Test status
Simulation time 6468850899 ps
CPU time 17.15 seconds
Started Sep 09 09:09:18 PM UTC 24
Finished Sep 09 09:09:37 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814193370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.814193370
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.3170706968
Short name T866
Test name
Test status
Simulation time 110601646 ps
CPU time 6.12 seconds
Started Sep 09 09:09:22 PM UTC 24
Finished Sep 09 09:09:29 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170706968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3170706968
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.2322836246
Short name T911
Test name
Test status
Simulation time 13045878773 ps
CPU time 25.59 seconds
Started Sep 09 09:09:22 PM UTC 24
Finished Sep 09 09:09:49 PM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322836246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2322836246
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.643080495
Short name T872
Test name
Test status
Simulation time 46300197 ps
CPU time 0.86 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:31 PM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643080495 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.643080495
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.3458690292
Short name T438
Test name
Test status
Simulation time 3351911410 ps
CPU time 74.49 seconds
Started Sep 09 09:09:25 PM UTC 24
Finished Sep 09 09:10:41 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458690292 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3458690292
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.1501742996
Short name T879
Test name
Test status
Simulation time 120122460 ps
CPU time 5.54 seconds
Started Sep 09 09:09:27 PM UTC 24
Finished Sep 09 09:09:34 PM UTC 24
Peak memory 232140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501742996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1501742996
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.836765903
Short name T865
Test name
Test status
Simulation time 196095803 ps
CPU time 2.67 seconds
Started Sep 09 09:09:25 PM UTC 24
Finished Sep 09 09:09:29 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836765903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.836765903
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.1606242387
Short name T870
Test name
Test status
Simulation time 96015797 ps
CPU time 3.3 seconds
Started Sep 09 09:09:26 PM UTC 24
Finished Sep 09 09:09:31 PM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606242387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1606242387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.682122583
Short name T871
Test name
Test status
Simulation time 333663932 ps
CPU time 3.3 seconds
Started Sep 09 09:09:26 PM UTC 24
Finished Sep 09 09:09:31 PM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682122583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.682122583
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.1836929195
Short name T868
Test name
Test status
Simulation time 325077151 ps
CPU time 4.18 seconds
Started Sep 09 09:09:25 PM UTC 24
Finished Sep 09 09:09:30 PM UTC 24
Peak memory 228208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836929195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1836929195
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_random.767568346
Short name T878
Test name
Test status
Simulation time 1180211742 ps
CPU time 7.96 seconds
Started Sep 09 09:09:25 PM UTC 24
Finished Sep 09 09:09:34 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767568346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.767568346
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.3821978024
Short name T867
Test name
Test status
Simulation time 378953509 ps
CPU time 4.88 seconds
Started Sep 09 09:09:24 PM UTC 24
Finished Sep 09 09:09:30 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821978024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3821978024
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.2319902596
Short name T863
Test name
Test status
Simulation time 45883648 ps
CPU time 3.42 seconds
Started Sep 09 09:09:24 PM UTC 24
Finished Sep 09 09:09:28 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319902596 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2319902596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.1131066524
Short name T869
Test name
Test status
Simulation time 2952011782 ps
CPU time 5.61 seconds
Started Sep 09 09:09:24 PM UTC 24
Finished Sep 09 09:09:30 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131066524 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1131066524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.2683131976
Short name T861
Test name
Test status
Simulation time 57250556 ps
CPU time 3.09 seconds
Started Sep 09 09:09:24 PM UTC 24
Finished Sep 09 09:09:28 PM UTC 24
Peak memory 218356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683131976 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2683131976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3364246568
Short name T874
Test name
Test status
Simulation time 267420975 ps
CPU time 3.5 seconds
Started Sep 09 09:09:27 PM UTC 24
Finished Sep 09 09:09:32 PM UTC 24
Peak memory 226476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364246568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3364246568
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.909311675
Short name T859
Test name
Test status
Simulation time 128812156 ps
CPU time 2.77 seconds
Started Sep 09 09:09:24 PM UTC 24
Finished Sep 09 09:09:27 PM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909311675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.909311675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.661780523
Short name T912
Test name
Test status
Simulation time 565969628 ps
CPU time 25.49 seconds
Started Sep 09 09:09:28 PM UTC 24
Finished Sep 09 09:09:54 PM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661780523 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.661780523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.1992671859
Short name T238
Test name
Test status
Simulation time 673881211 ps
CPU time 15.67 seconds
Started Sep 09 09:09:28 PM UTC 24
Finished Sep 09 09:09:45 PM UTC 24
Peak memory 232476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1992671859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg
r_stress_all_with_rand_reset.1992671859
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.1929434283
Short name T893
Test name
Test status
Simulation time 995052610 ps
CPU time 10.64 seconds
Started Sep 09 09:09:26 PM UTC 24
Finished Sep 09 09:09:38 PM UTC 24
Peak memory 228268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929434283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1929434283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.2974092936
Short name T900
Test name
Test status
Simulation time 1304052311 ps
CPU time 11.61 seconds
Started Sep 09 09:09:28 PM UTC 24
Finished Sep 09 09:09:40 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974092936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2974092936
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.3752523456
Short name T876
Test name
Test status
Simulation time 33915407 ps
CPU time 0.91 seconds
Started Sep 09 09:09:32 PM UTC 24
Finished Sep 09 09:09:34 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752523456 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3752523456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.1138117512
Short name T374
Test name
Test status
Simulation time 31931841 ps
CPU time 3.46 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:34 PM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138117512 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1138117512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.1091054139
Short name T241
Test name
Test status
Simulation time 302417000 ps
CPU time 4 seconds
Started Sep 09 09:09:32 PM UTC 24
Finished Sep 09 09:09:37 PM UTC 24
Peak memory 230316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091054139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1091054139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.3968167735
Short name T884
Test name
Test status
Simulation time 725044016 ps
CPU time 4.82 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:35 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968167735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3968167735
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.3430482454
Short name T886
Test name
Test status
Simulation time 226427485 ps
CPU time 4.4 seconds
Started Sep 09 09:09:30 PM UTC 24
Finished Sep 09 09:09:36 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430482454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3430482454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.4130512748
Short name T881
Test name
Test status
Simulation time 131460304 ps
CPU time 3.25 seconds
Started Sep 09 09:09:30 PM UTC 24
Finished Sep 09 09:09:35 PM UTC 24
Peak memory 230272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130512748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4130512748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.637617799
Short name T885
Test name
Test status
Simulation time 464847501 ps
CPU time 4.33 seconds
Started Sep 09 09:09:30 PM UTC 24
Finished Sep 09 09:09:36 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637617799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.637617799
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_random.448278801
Short name T888
Test name
Test status
Simulation time 478814237 ps
CPU time 5.63 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:36 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448278801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.448278801
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.1448552371
Short name T918
Test name
Test status
Simulation time 10650664098 ps
CPU time 43.27 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:10:14 PM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448552371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1448552371
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.4083111172
Short name T915
Test name
Test status
Simulation time 2716901937 ps
CPU time 32.78 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:10:03 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083111172 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4083111172
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.579999804
Short name T877
Test name
Test status
Simulation time 79880462 ps
CPU time 3.88 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:34 PM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579999804 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.579999804
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.35696204
Short name T875
Test name
Test status
Simulation time 315307680 ps
CPU time 3.27 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:33 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35696204 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.35696204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.2129364616
Short name T887
Test name
Test status
Simulation time 34877717 ps
CPU time 3.15 seconds
Started Sep 09 09:09:32 PM UTC 24
Finished Sep 09 09:09:36 PM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129364616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2129364616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.3222931853
Short name T894
Test name
Test status
Simulation time 502778557 ps
CPU time 8.65 seconds
Started Sep 09 09:09:29 PM UTC 24
Finished Sep 09 09:09:39 PM UTC 24
Peak memory 218004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222931853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3222931853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1105992350
Short name T914
Test name
Test status
Simulation time 980561019 ps
CPU time 23.75 seconds
Started Sep 09 09:09:32 PM UTC 24
Finished Sep 09 09:09:57 PM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105992350 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1105992350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.3679704114
Short name T903
Test name
Test status
Simulation time 941389433 ps
CPU time 7.75 seconds
Started Sep 09 09:09:32 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 232632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3679704114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg
r_stress_all_with_rand_reset.3679704114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.2868708482
Short name T889
Test name
Test status
Simulation time 85265070 ps
CPU time 4.62 seconds
Started Sep 09 09:09:30 PM UTC 24
Finished Sep 09 09:09:36 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868708482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2868708482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.766171097
Short name T882
Test name
Test status
Simulation time 155682795 ps
CPU time 1.95 seconds
Started Sep 09 09:09:32 PM UTC 24
Finished Sep 09 09:09:35 PM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766171097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.766171097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.247194723
Short name T896
Test name
Test status
Simulation time 50990924 ps
CPU time 1.12 seconds
Started Sep 09 09:09:37 PM UTC 24
Finished Sep 09 09:09:39 PM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247194723 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.247194723
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3000291198
Short name T446
Test name
Test status
Simulation time 91356010 ps
CPU time 4.99 seconds
Started Sep 09 09:09:35 PM UTC 24
Finished Sep 09 09:09:42 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000291198 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3000291198
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.4013247708
Short name T234
Test name
Test status
Simulation time 214656558 ps
CPU time 4.61 seconds
Started Sep 09 09:09:37 PM UTC 24
Finished Sep 09 09:09:43 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013247708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4013247708
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.1465886916
Short name T898
Test name
Test status
Simulation time 267545874 ps
CPU time 3.27 seconds
Started Sep 09 09:09:35 PM UTC 24
Finished Sep 09 09:09:40 PM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465886916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1465886916
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.267014733
Short name T905
Test name
Test status
Simulation time 258778857 ps
CPU time 3.84 seconds
Started Sep 09 09:09:36 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 219968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267014733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.267014733
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.3206117866
Short name T909
Test name
Test status
Simulation time 132185030 ps
CPU time 6.1 seconds
Started Sep 09 09:09:36 PM UTC 24
Finished Sep 09 09:09:43 PM UTC 24
Peak memory 232540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206117866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3206117866
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.3925925820
Short name T897
Test name
Test status
Simulation time 259451845 ps
CPU time 2.91 seconds
Started Sep 09 09:09:35 PM UTC 24
Finished Sep 09 09:09:40 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925925820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3925925820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_random.1428603204
Short name T901
Test name
Test status
Simulation time 379103792 ps
CPU time 4.17 seconds
Started Sep 09 09:09:35 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 218236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428603204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1428603204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.3743519515
Short name T919
Test name
Test status
Simulation time 1459710311 ps
CPU time 45.5 seconds
Started Sep 09 09:09:33 PM UTC 24
Finished Sep 09 09:10:20 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743519515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3743519515
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.3905505847
Short name T904
Test name
Test status
Simulation time 491814326 ps
CPU time 4.29 seconds
Started Sep 09 09:09:35 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905505847 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3905505847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.832253648
Short name T892
Test name
Test status
Simulation time 113955637 ps
CPU time 2.43 seconds
Started Sep 09 09:09:34 PM UTC 24
Finished Sep 09 09:09:38 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832253648 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.832253648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.769311209
Short name T899
Test name
Test status
Simulation time 53144160 ps
CPU time 3.73 seconds
Started Sep 09 09:09:35 PM UTC 24
Finished Sep 09 09:09:40 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769311209 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.769311209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.3096882335
Short name T902
Test name
Test status
Simulation time 31777366 ps
CPU time 2.57 seconds
Started Sep 09 09:09:37 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 224176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096882335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3096882335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.3399043055
Short name T891
Test name
Test status
Simulation time 339848304 ps
CPU time 3.05 seconds
Started Sep 09 09:09:33 PM UTC 24
Finished Sep 09 09:09:37 PM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399043055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3399043055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.4094243559
Short name T916
Test name
Test status
Simulation time 1332593757 ps
CPU time 26.73 seconds
Started Sep 09 09:09:37 PM UTC 24
Finished Sep 09 09:10:05 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094243559 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4094243559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.1724199115
Short name T913
Test name
Test status
Simulation time 290987200 ps
CPU time 17.11 seconds
Started Sep 09 09:09:37 PM UTC 24
Finished Sep 09 09:09:55 PM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1724199115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymg
r_stress_all_with_rand_reset.1724199115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.2525869815
Short name T907
Test name
Test status
Simulation time 416729447 ps
CPU time 5.08 seconds
Started Sep 09 09:09:36 PM UTC 24
Finished Sep 09 09:09:42 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525869815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2525869815
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.3723983064
Short name T906
Test name
Test status
Simulation time 171702498 ps
CPU time 3.27 seconds
Started Sep 09 09:09:37 PM UTC 24
Finished Sep 09 09:09:41 PM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723983064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3723983064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.4290061229
Short name T453
Test name
Test status
Simulation time 33721659 ps
CPU time 1.22 seconds
Started Sep 09 09:05:26 PM UTC 24
Finished Sep 09 09:05:28 PM UTC 24
Peak memory 213608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290061229 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4290061229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.1480598616
Short name T38
Test name
Test status
Simulation time 492259206 ps
CPU time 3.99 seconds
Started Sep 09 09:05:24 PM UTC 24
Finished Sep 09 09:05:30 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480598616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1480598616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.439852211
Short name T129
Test name
Test status
Simulation time 79688054 ps
CPU time 4.19 seconds
Started Sep 09 09:05:22 PM UTC 24
Finished Sep 09 09:05:27 PM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439852211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.439852211
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.3618056787
Short name T25
Test name
Test status
Simulation time 33846881 ps
CPU time 2.66 seconds
Started Sep 09 09:05:23 PM UTC 24
Finished Sep 09 09:05:27 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618056787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3618056787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_random.1840588531
Short name T197
Test name
Test status
Simulation time 154660985 ps
CPU time 4.31 seconds
Started Sep 09 09:05:22 PM UTC 24
Finished Sep 09 09:05:27 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840588531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1840588531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.2401132564
Short name T214
Test name
Test status
Simulation time 50305529 ps
CPU time 3.7 seconds
Started Sep 09 09:05:19 PM UTC 24
Finished Sep 09 09:05:23 PM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401132564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2401132564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.2956267672
Short name T389
Test name
Test status
Simulation time 886379689 ps
CPU time 2.81 seconds
Started Sep 09 09:05:20 PM UTC 24
Finished Sep 09 09:05:24 PM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956267672 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2956267672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.3931070702
Short name T285
Test name
Test status
Simulation time 340659645 ps
CPU time 3.93 seconds
Started Sep 09 09:05:19 PM UTC 24
Finished Sep 09 09:05:24 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931070702 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3931070702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.2775544514
Short name T316
Test name
Test status
Simulation time 68750409 ps
CPU time 2.42 seconds
Started Sep 09 09:05:21 PM UTC 24
Finished Sep 09 09:05:24 PM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775544514 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2775544514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1773205
Short name T208
Test name
Test status
Simulation time 488704733 ps
CPU time 3.39 seconds
Started Sep 09 09:05:19 PM UTC 24
Finished Sep 09 09:05:23 PM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1773205
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.1212891560
Short name T64
Test name
Test status
Simulation time 243363930 ps
CPU time 14.9 seconds
Started Sep 09 09:05:26 PM UTC 24
Finished Sep 09 09:05:42 PM UTC 24
Peak memory 232400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1212891560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr
_stress_all_with_rand_reset.1212891560
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.1227246097
Short name T201
Test name
Test status
Simulation time 154087999 ps
CPU time 4.77 seconds
Started Sep 09 09:05:23 PM UTC 24
Finished Sep 09 09:05:29 PM UTC 24
Peak memory 219928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227246097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1227246097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.538630976
Short name T127
Test name
Test status
Simulation time 81922618 ps
CPU time 2.45 seconds
Started Sep 09 09:05:25 PM UTC 24
Finished Sep 09 09:05:28 PM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538630976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.538630976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.2453616855
Short name T458
Test name
Test status
Simulation time 8927388 ps
CPU time 1.06 seconds
Started Sep 09 09:05:34 PM UTC 24
Finished Sep 09 09:05:36 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453616855 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2453616855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.95484273
Short name T63
Test name
Test status
Simulation time 62907118 ps
CPU time 3.35 seconds
Started Sep 09 09:05:31 PM UTC 24
Finished Sep 09 09:05:35 PM UTC 24
Peak memory 218056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95484273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.95484273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.2202099011
Short name T140
Test name
Test status
Simulation time 685426922 ps
CPU time 4.64 seconds
Started Sep 09 09:05:29 PM UTC 24
Finished Sep 09 09:05:35 PM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202099011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2202099011
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.2292555264
Short name T323
Test name
Test status
Simulation time 93076382 ps
CPU time 3.15 seconds
Started Sep 09 09:05:30 PM UTC 24
Finished Sep 09 09:05:35 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292555264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2292555264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.2946003789
Short name T310
Test name
Test status
Simulation time 150249455 ps
CPU time 4.53 seconds
Started Sep 09 09:05:31 PM UTC 24
Finished Sep 09 09:05:36 PM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946003789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2946003789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.530593716
Short name T8
Test name
Test status
Simulation time 181855231 ps
CPU time 2.7 seconds
Started Sep 09 09:05:29 PM UTC 24
Finished Sep 09 09:05:33 PM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530593716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.530593716
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_random.1985330069
Short name T202
Test name
Test status
Simulation time 325352955 ps
CPU time 2.28 seconds
Started Sep 09 09:05:28 PM UTC 24
Finished Sep 09 09:05:31 PM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985330069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1985330069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.2212343526
Short name T456
Test name
Test status
Simulation time 200359147 ps
CPU time 4.91 seconds
Started Sep 09 09:05:26 PM UTC 24
Finished Sep 09 09:05:32 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212343526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2212343526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.327349535
Short name T465
Test name
Test status
Simulation time 3238812511 ps
CPU time 29.78 seconds
Started Sep 09 09:05:28 PM UTC 24
Finished Sep 09 09:05:59 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327349535 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.327349535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.3102984483
Short name T467
Test name
Test status
Simulation time 1396629748 ps
CPU time 37.31 seconds
Started Sep 09 09:05:28 PM UTC 24
Finished Sep 09 09:06:07 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102984483 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3102984483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.1174839882
Short name T457
Test name
Test status
Simulation time 86854894 ps
CPU time 3.45 seconds
Started Sep 09 09:05:28 PM UTC 24
Finished Sep 09 09:05:33 PM UTC 24
Peak memory 216152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174839882 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1174839882
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.2606167442
Short name T210
Test name
Test status
Simulation time 159569162 ps
CPU time 3.73 seconds
Started Sep 09 09:05:32 PM UTC 24
Finished Sep 09 09:05:36 PM UTC 24
Peak memory 228188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606167442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2606167442
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.4264484998
Short name T414
Test name
Test status
Simulation time 651332727 ps
CPU time 2.7 seconds
Started Sep 09 09:05:26 PM UTC 24
Finished Sep 09 09:05:30 PM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264484998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4264484998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.2968894828
Short name T696
Test name
Test status
Simulation time 37661110108 ps
CPU time 179.42 seconds
Started Sep 09 09:05:33 PM UTC 24
Finished Sep 09 09:08:35 PM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968894828 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2968894828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.3830793875
Short name T69
Test name
Test status
Simulation time 178583206 ps
CPU time 6.56 seconds
Started Sep 09 09:05:33 PM UTC 24
Finished Sep 09 09:05:41 PM UTC 24
Peak memory 230380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3830793875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr
_stress_all_with_rand_reset.3830793875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.2753857979
Short name T269
Test name
Test status
Simulation time 32918172 ps
CPU time 2.9 seconds
Started Sep 09 09:05:29 PM UTC 24
Finished Sep 09 09:05:33 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753857979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2753857979
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.3615825740
Short name T460
Test name
Test status
Simulation time 31167524 ps
CPU time 1.2 seconds
Started Sep 09 09:05:42 PM UTC 24
Finished Sep 09 09:05:45 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615825740 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3615825740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.3558478990
Short name T352
Test name
Test status
Simulation time 152141616 ps
CPU time 3.36 seconds
Started Sep 09 09:05:36 PM UTC 24
Finished Sep 09 09:05:41 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558478990 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3558478990
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.2624379445
Short name T22
Test name
Test status
Simulation time 240281667 ps
CPU time 1.88 seconds
Started Sep 09 09:05:41 PM UTC 24
Finished Sep 09 09:05:44 PM UTC 24
Peak memory 216000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624379445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2624379445
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.1840501886
Short name T144
Test name
Test status
Simulation time 85257238 ps
CPU time 4.09 seconds
Started Sep 09 09:05:38 PM UTC 24
Finished Sep 09 09:05:43 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840501886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1840501886
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.184921343
Short name T47
Test name
Test status
Simulation time 208416230 ps
CPU time 2.83 seconds
Started Sep 09 09:05:38 PM UTC 24
Finished Sep 09 09:05:42 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184921343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.184921343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.2246726520
Short name T304
Test name
Test status
Simulation time 402507185 ps
CPU time 4.41 seconds
Started Sep 09 09:05:38 PM UTC 24
Finished Sep 09 09:05:44 PM UTC 24
Peak memory 230940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246726520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2246726520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.3800531138
Short name T110
Test name
Test status
Simulation time 93582366 ps
CPU time 2.65 seconds
Started Sep 09 09:05:38 PM UTC 24
Finished Sep 09 09:05:42 PM UTC 24
Peak memory 226528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800531138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3800531138
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_random.3819137050
Short name T251
Test name
Test status
Simulation time 867686552 ps
CPU time 9.46 seconds
Started Sep 09 09:05:36 PM UTC 24
Finished Sep 09 09:05:47 PM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819137050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3819137050
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.1488127105
Short name T282
Test name
Test status
Simulation time 170504749 ps
CPU time 7.19 seconds
Started Sep 09 09:05:34 PM UTC 24
Finished Sep 09 09:05:43 PM UTC 24
Peak memory 218244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488127105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1488127105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.659075800
Short name T355
Test name
Test status
Simulation time 126245333 ps
CPU time 6.46 seconds
Started Sep 09 09:05:35 PM UTC 24
Finished Sep 09 09:05:43 PM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659075800 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.659075800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.3667879094
Short name T463
Test name
Test status
Simulation time 3276047109 ps
CPU time 15.3 seconds
Started Sep 09 09:05:35 PM UTC 24
Finished Sep 09 09:05:52 PM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667879094 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3667879094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.388565820
Short name T283
Test name
Test status
Simulation time 65934197 ps
CPU time 4.69 seconds
Started Sep 09 09:05:35 PM UTC 24
Finished Sep 09 09:05:41 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388565820 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.388565820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.4032690830
Short name T435
Test name
Test status
Simulation time 26316118 ps
CPU time 1.65 seconds
Started Sep 09 09:05:41 PM UTC 24
Finished Sep 09 09:05:44 PM UTC 24
Peak memory 215992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032690830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4032690830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.2740483008
Short name T459
Test name
Test status
Simulation time 269736022 ps
CPU time 4.03 seconds
Started Sep 09 09:05:34 PM UTC 24
Finished Sep 09 09:05:39 PM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740483008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2740483008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.3441562115
Short name T133
Test name
Test status
Simulation time 1573525117 ps
CPU time 37.8 seconds
Started Sep 09 09:05:42 PM UTC 24
Finished Sep 09 09:06:22 PM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441562115 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3441562115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2060531277
Short name T317
Test name
Test status
Simulation time 147093799 ps
CPU time 8.36 seconds
Started Sep 09 09:05:38 PM UTC 24
Finished Sep 09 09:05:47 PM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060531277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2060531277
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.1169795370
Short name T402
Test name
Test status
Simulation time 42076934 ps
CPU time 2.36 seconds
Started Sep 09 09:05:41 PM UTC 24
Finished Sep 09 09:05:45 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169795370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1169795370
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3113191869
Short name T462
Test name
Test status
Simulation time 23622686 ps
CPU time 1.15 seconds
Started Sep 09 09:05:49 PM UTC 24
Finished Sep 09 09:05:51 PM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113191869 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3113191869
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.301723348
Short name T301
Test name
Test status
Simulation time 4129445782 ps
CPU time 15 seconds
Started Sep 09 09:05:45 PM UTC 24
Finished Sep 09 09:06:01 PM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301723348 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.301723348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.305085763
Short name T126
Test name
Test status
Simulation time 201091106 ps
CPU time 4.36 seconds
Started Sep 09 09:05:45 PM UTC 24
Finished Sep 09 09:05:50 PM UTC 24
Peak memory 230356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305085763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.305085763
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.3243897967
Short name T191
Test name
Test status
Simulation time 333486238 ps
CPU time 15.01 seconds
Started Sep 09 09:05:46 PM UTC 24
Finished Sep 09 09:06:02 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243897967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3243897967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.2681150926
Short name T278
Test name
Test status
Simulation time 88603784 ps
CPU time 4.34 seconds
Started Sep 09 09:05:46 PM UTC 24
Finished Sep 09 09:05:52 PM UTC 24
Peak memory 232196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681150926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2681150926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.1339777160
Short name T434
Test name
Test status
Simulation time 476834541 ps
CPU time 3.09 seconds
Started Sep 09 09:05:45 PM UTC 24
Finished Sep 09 09:05:49 PM UTC 24
Peak memory 230380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339777160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1339777160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_random.3093721975
Short name T293
Test name
Test status
Simulation time 230165807 ps
CPU time 7.53 seconds
Started Sep 09 09:05:45 PM UTC 24
Finished Sep 09 09:05:53 PM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093721975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3093721975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.2144360896
Short name T309
Test name
Test status
Simulation time 929188560 ps
CPU time 23.55 seconds
Started Sep 09 09:05:43 PM UTC 24
Finished Sep 09 09:06:08 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144360896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2144360896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.2783343691
Short name T350
Test name
Test status
Simulation time 36455635 ps
CPU time 2.93 seconds
Started Sep 09 09:05:44 PM UTC 24
Finished Sep 09 09:05:48 PM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783343691 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2783343691
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.549507572
Short name T326
Test name
Test status
Simulation time 34478679 ps
CPU time 3.06 seconds
Started Sep 09 09:05:43 PM UTC 24
Finished Sep 09 09:05:48 PM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549507572 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.549507572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.300620497
Short name T189
Test name
Test status
Simulation time 455261747 ps
CPU time 15.6 seconds
Started Sep 09 09:05:44 PM UTC 24
Finished Sep 09 09:06:01 PM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300620497 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.300620497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.4203707626
Short name T295
Test name
Test status
Simulation time 27504377 ps
CPU time 2.22 seconds
Started Sep 09 09:05:47 PM UTC 24
Finished Sep 09 09:05:51 PM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203707626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4203707626
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.95584266
Short name T461
Test name
Test status
Simulation time 911462628 ps
CPU time 3.8 seconds
Started Sep 09 09:05:42 PM UTC 24
Finished Sep 09 09:05:47 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95584266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.95584266
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.2968994811
Short name T190
Test name
Test status
Simulation time 1741563083 ps
CPU time 11.19 seconds
Started Sep 09 09:05:48 PM UTC 24
Finished Sep 09 09:06:01 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968994811 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2968994811
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.1942095182
Short name T84
Test name
Test status
Simulation time 1078041110 ps
CPU time 10.64 seconds
Started Sep 09 09:05:49 PM UTC 24
Finished Sep 09 09:06:00 PM UTC 24
Peak memory 232412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1942095182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr
_stress_all_with_rand_reset.1942095182
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.783924825
Short name T328
Test name
Test status
Simulation time 2098996142 ps
CPU time 26.61 seconds
Started Sep 09 09:05:46 PM UTC 24
Finished Sep 09 09:06:14 PM UTC 24
Peak memory 224192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783924825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.783924825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3710274811
Short name T141
Test name
Test status
Simulation time 141388150 ps
CPU time 3.82 seconds
Started Sep 09 09:05:48 PM UTC 24
Finished Sep 09 09:05:53 PM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710274811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3710274811
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.1974094769
Short name T454
Test name
Test status
Simulation time 41879093 ps
CPU time 1.25 seconds
Started Sep 09 09:06:00 PM UTC 24
Finished Sep 09 09:06:02 PM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974094769 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1974094769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.1620861014
Short name T294
Test name
Test status
Simulation time 387938855 ps
CPU time 4.78 seconds
Started Sep 09 09:05:53 PM UTC 24
Finished Sep 09 09:05:59 PM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620861014 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1620861014
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.3978597225
Short name T131
Test name
Test status
Simulation time 244982219 ps
CPU time 3.61 seconds
Started Sep 09 09:05:54 PM UTC 24
Finished Sep 09 09:05:59 PM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978597225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3978597225
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.1720482781
Short name T26
Test name
Test status
Simulation time 563695127 ps
CPU time 6.09 seconds
Started Sep 09 09:05:54 PM UTC 24
Finished Sep 09 09:06:02 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720482781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1720482781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.2339103050
Short name T395
Test name
Test status
Simulation time 63810216 ps
CPU time 3 seconds
Started Sep 09 09:05:55 PM UTC 24
Finished Sep 09 09:06:00 PM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339103050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2339103050
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.3553418925
Short name T432
Test name
Test status
Simulation time 139199629 ps
CPU time 1.58 seconds
Started Sep 09 09:05:54 PM UTC 24
Finished Sep 09 09:05:57 PM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553418925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3553418925
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_random.3246239090
Short name T300
Test name
Test status
Simulation time 53953429 ps
CPU time 5.03 seconds
Started Sep 09 09:05:53 PM UTC 24
Finished Sep 09 09:05:59 PM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246239090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3246239090
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.275496064
Short name T279
Test name
Test status
Simulation time 45338941 ps
CPU time 3.14 seconds
Started Sep 09 09:05:50 PM UTC 24
Finished Sep 09 09:05:54 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275496064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.275496064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.3235495479
Short name T466
Test name
Test status
Simulation time 169699966 ps
CPU time 7.69 seconds
Started Sep 09 09:05:51 PM UTC 24
Finished Sep 09 09:06:00 PM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235495479 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3235495479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.2664066862
Short name T259
Test name
Test status
Simulation time 1160914568 ps
CPU time 13.11 seconds
Started Sep 09 09:05:52 PM UTC 24
Finished Sep 09 09:06:07 PM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664066862 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_08/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2664066862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.3302120467
Short name T248
Test name
Test status
Simulation time 247442726 ps
CPU time 2.39 seconds
Started Sep 09 09:05:58 PM UTC 24
Finished Sep 09 09:06:01 PM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302120467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3302120467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.1370079029
Short name T464
Test name
Test status
Simulation time 209904088 ps
CPU time 5.33 seconds
Started Sep 09 09:05:49 PM UTC 24
Finished Sep 09 09:05:55 PM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370079029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1370079029
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.3784887775
Short name T252
Test name
Test status
Simulation time 197206237 ps
CPU time 7.79 seconds
Started Sep 09 09:05:54 PM UTC 24
Finished Sep 09 09:06:03 PM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784887775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3784887775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.580150927
Short name T97
Test name
Test status
Simulation time 203325455 ps
CPU time 2.2 seconds
Started Sep 09 09:05:59 PM UTC 24
Finished Sep 09 09:06:02 PM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580150927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.580150927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%