Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2573949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

584330

1

T1

153

T2

257

T3

149

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2760278	1			T1	701		T2	1972		T3	1307
values[0x0]	197802	1			T1	39		T2	63		T3	39
values[0x1]	200199	1			T1	47		T2	70		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1771555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1386724

1

T1

347

T2

805

T3

516

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10086	1			T1	1		T4	1		T5	5
valid_sources[0x01]	18075	1			T1	2		T4	4		T5	8
valid_sources[0x02]	10854	1			T1	3		T5	4		T13	32
valid_sources[0x03]	11822	1			T1	5		T4	5		T5	5
valid_sources[0x04]	30017	1			T1	8		T5	6		T13	37
valid_sources[0x05]	13283	1			T1	5		T4	4		T5	2
valid_sources[0x06]	15520	1			T1	1		T4	2		T5	2
valid_sources[0x07]	10324	1			T1	1		T4	3		T5	7
valid_sources[0x08]	11205	1			T1	4		T4	3		T5	8
valid_sources[0x09]	10324	1			T1	1		T4	1		T5	3
valid_sources[0x0a]	10765	1			T1	2		T4	3		T5	1
valid_sources[0x0b]	9860	1			T4	2		T5	1		T13	37
valid_sources[0x0c]	12126	1			T4	1		T5	6		T13	40
valid_sources[0x0d]	10158	1			T1	2		T4	3		T5	7
valid_sources[0x0e]	9479	1			T1	9		T4	1		T5	1
valid_sources[0x0f]	35225	1			T1	1		T4	2		T5	3
valid_sources[0x10]	11910	1			T1	4		T5	3		T13	49
valid_sources[0x11]	10047	1			T1	3		T4	2		T5	7
valid_sources[0x12]	11281	1			T1	3		T4	3		T5	5
valid_sources[0x13]	9785	1			T1	3		T4	2		T5	10
valid_sources[0x14]	18670	1			T1	3		T4	2		T5	3
valid_sources[0x15]	10521	1			T1	6		T4	3		T5	4
valid_sources[0x16]	11384	1			T1	4		T4	1		T5	7
valid_sources[0x17]	10054	1			T1	3		T4	1		T5	3
valid_sources[0x18]	9860	1			T1	2		T4	1		T5	5
valid_sources[0x19]	10032	1			T1	2		T4	5		T5	6
valid_sources[0x1a]	10442	1			T5	7		T13	38		T15	8
valid_sources[0x1b]	13206	1			T1	1		T4	1		T5	3
valid_sources[0x1c]	10136	1			T1	2		T4	1		T5	4
valid_sources[0x1d]	9778	1			T1	2		T5	2		T13	27
valid_sources[0x1e]	17221	1			T1	4		T5	7		T13	45
valid_sources[0x1f]	10137	1			T5	4		T13	36		T14	1
valid_sources[0x20]	10220	1			T1	1		T4	1		T5	6
valid_sources[0x21]	9503	1			T1	2		T4	1		T5	5
valid_sources[0x22]	10047	1			T1	1		T5	11		T13	48
valid_sources[0x23]	9768	1			T1	3		T4	1		T5	4
valid_sources[0x24]	12419	1			T1	3		T5	2		T13	49
valid_sources[0x25]	46762	1			T1	4		T4	2		T5	5
valid_sources[0x26]	10317	1			T1	5		T4	1		T5	4
valid_sources[0x27]	9629	1			T4	2		T5	7		T13	51
valid_sources[0x28]	10998	1			T5	4		T13	45		T14	6
valid_sources[0x29]	12244	1			T1	5		T4	2		T5	3
valid_sources[0x2a]	11171	1			T1	3		T5	1		T13	41
valid_sources[0x2b]	13141	1			T1	2		T4	4		T5	5
valid_sources[0x2c]	11699	1			T1	3		T4	1		T5	3
valid_sources[0x2d]	11091	1			T4	2		T5	8		T13	49
valid_sources[0x2e]	14466	1			T1	5		T4	2		T5	3
valid_sources[0x2f]	11785	1			T1	3		T4	1		T5	7
valid_sources[0x30]	11001	1			T1	8		T4	4		T5	3
valid_sources[0x31]	10729	1			T1	1		T4	1		T5	4
valid_sources[0x32]	9272	1			T1	2		T4	3		T5	4
valid_sources[0x33]	10046	1			T1	6		T5	7		T13	47
valid_sources[0x34]	10707	1			T1	7		T5	10		T13	43
valid_sources[0x35]	10893	1			T5	6		T13	45		T14	4
valid_sources[0x36]	9499	1			T1	1		T4	3		T5	6
valid_sources[0x37]	14577	1			T1	4		T4	3		T5	9
valid_sources[0x38]	17404	1			T1	2		T4	1		T5	6
valid_sources[0x39]	11356	1			T1	5		T4	3		T5	3
valid_sources[0x3a]	11175	1			T1	5		T4	1		T5	6
valid_sources[0x3b]	10439	1			T1	2		T4	1		T5	3
valid_sources[0x3c]	10024	1			T1	3		T5	3		T13	48
valid_sources[0x3d]	12547	1			T1	5		T4	3		T5	7
valid_sources[0x3e]	9879	1			T1	4		T5	5		T13	43
valid_sources[0x3f]	11226	1			T1	1		T3	1394		T4	6
valid_sources[0x40]	10331	1			T1	2		T4	6		T5	4
valid_sources[0x41]	11337	1			T1	2		T4	2		T5	4
valid_sources[0x42]	9369	1			T1	4		T4	2		T5	7
valid_sources[0x43]	22920	1			T1	8		T4	2		T5	6
valid_sources[0x44]	10381	1			T1	4		T4	2		T5	4
valid_sources[0x45]	9236	1			T1	1		T5	3		T13	39
valid_sources[0x46]	14155	1			T1	5		T4	1		T5	8
valid_sources[0x47]	9800	1			T4	4		T5	7		T13	29
valid_sources[0x48]	9492	1			T1	2		T4	1		T5	5
valid_sources[0x49]	10721	1			T1	5		T4	3		T5	4
valid_sources[0x4a]	12738	1			T1	5		T5	7		T13	34
valid_sources[0x4b]	9458	1			T1	2		T4	1		T5	5
valid_sources[0x4c]	16231	1			T4	2		T5	2		T13	29
valid_sources[0x4d]	59415	1			T5	3		T13	36		T14	7
valid_sources[0x4e]	15246	1			T1	4		T4	3		T5	5
valid_sources[0x4f]	13758	1			T1	7		T5	6		T13	38
valid_sources[0x50]	14274	1			T1	3		T4	1		T5	2
valid_sources[0x51]	10264	1			T1	1		T4	3		T5	7
valid_sources[0x52]	20492	1			T1	2		T4	3		T5	8
valid_sources[0x53]	11731	1			T1	4		T4	1		T5	8
valid_sources[0x54]	10499	1			T1	11		T4	1		T5	6
valid_sources[0x55]	10504	1			T1	1		T5	9		T13	30
valid_sources[0x56]	9675	1			T1	8		T4	2		T5	2
valid_sources[0x57]	9919	1			T1	8		T5	2		T13	33
valid_sources[0x58]	10053	1			T1	1		T4	1		T5	6
valid_sources[0x59]	11055	1			T4	1		T5	4		T13	40
valid_sources[0x5a]	16516	1			T1	6		T5	5		T13	41
valid_sources[0x5b]	10695	1			T1	4		T4	4		T5	2
valid_sources[0x5c]	10189	1			T1	5		T4	1		T13	43
valid_sources[0x5d]	10281	1			T1	6		T4	2		T5	2
valid_sources[0x5e]	11117	1			T1	2		T5	3		T13	34
valid_sources[0x5f]	10226	1			T1	4		T4	2		T5	5
valid_sources[0x60]	10482	1			T4	1		T5	2		T13	30
valid_sources[0x61]	10036	1			T1	3		T4	1		T5	8
valid_sources[0x62]	10293	1			T4	3		T5	4		T13	42
valid_sources[0x63]	12573	1			T1	2		T5	2		T13	36
valid_sources[0x64]	9247	1			T1	4		T4	1		T5	9
valid_sources[0x65]	10806	1			T4	2		T5	4		T13	30
valid_sources[0x66]	9939	1			T1	1		T4	2		T5	5
valid_sources[0x67]	10829	1			T1	1		T4	2		T5	2
valid_sources[0x68]	15099	1			T1	1		T4	5		T5	4
valid_sources[0x69]	11082	1			T1	4		T4	2		T5	2
valid_sources[0x6a]	17214	1			T1	4		T4	2		T5	4
valid_sources[0x6b]	14919	1			T1	9		T4	1		T5	7
valid_sources[0x6c]	10634	1			T1	7		T4	4		T5	2
valid_sources[0x6d]	9914	1			T1	5		T5	2		T13	37
valid_sources[0x6e]	9227	1			T4	1		T5	7		T13	33
valid_sources[0x6f]	12809	1			T1	1		T5	9		T13	37
valid_sources[0x70]	11772	1			T1	4		T4	3		T5	3
valid_sources[0x71]	14703	1			T1	2		T4	1		T5	7
valid_sources[0x72]	10592	1			T4	2		T5	5		T13	39
valid_sources[0x73]	13541	1			T1	2		T4	1		T5	2
valid_sources[0x74]	11043	1			T1	7		T4	2		T5	3
valid_sources[0x75]	13759	1			T1	3		T4	3		T5	6
valid_sources[0x76]	10963	1			T1	2		T4	2		T5	4
valid_sources[0x77]	11286	1			T1	1		T4	4		T5	5
valid_sources[0x78]	11507	1			T1	5		T5	8		T13	40
valid_sources[0x79]	13317	1			T1	1		T4	1		T5	3
valid_sources[0x7a]	11351	1			T1	6		T4	1		T5	4
valid_sources[0x7b]	10345	1			T1	4		T4	1		T5	5
valid_sources[0x7c]	11354	1			T1	6		T4	1		T5	1
valid_sources[0x7d]	15540	1			T1	3		T4	2		T5	5
valid_sources[0x7e]	17114	1			T1	3		T4	5		T5	5
valid_sources[0x7f]	10745	1			T1	2		T4	1		T5	3
valid_sources[0x80]	10602	1			T1	3		T4	2		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

315149

1

T1

131

T2

218

T3

123

values[0x0]

all_enables

biggest_size

141866

1

T1

13

T2

28

T3

16

values[0x1]

all_enables

biggest_size

127315

1

T1

9

T2

11

T3

10