Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19699870	14717	0	0
attest_sw_binding_0_rd_A	19699870	3284	0	0
attest_sw_binding_1_rd_A	19699870	3392	0	0
attest_sw_binding_2_rd_A	19699870	3337	0	0
attest_sw_binding_3_rd_A	19699870	3246	0	0
attest_sw_binding_4_rd_A	19699870	3348	0	0
attest_sw_binding_5_rd_A	19699870	3304	0	0
attest_sw_binding_6_rd_A	19699870	3261	0	0
attest_sw_binding_7_rd_A	19699870	3256	0	0
intr_enable_rd_A	19699870	4311	0	0
key_version_rd_A	19699870	3233	0	0
max_creator_key_ver_regwen_rd_A	19699870	3245	0	0
max_owner_int_key_ver_regwen_rd_A	19699870	3161	0	0
max_owner_key_ver_regwen_rd_A	19699870	3409	0	0
reseed_interval_regwen_rd_A	19699870	3289	0	0
salt_0_rd_A	19699870	3330	0	0
salt_1_rd_A	19699870	3168	0	0
salt_2_rd_A	19699870	3427	0	0
salt_3_rd_A	19699870	3210	0	0
salt_4_rd_A	19699870	3370	0	0
salt_5_rd_A	19699870	3169	0	0
salt_6_rd_A	19699870	3424	0	0
salt_7_rd_A	19699870	3327	0	0
sealing_sw_binding_0_rd_A	19699870	3256	0	0
sealing_sw_binding_1_rd_A	19699870	3072	0	0
sealing_sw_binding_2_rd_A	19699870	3434	0	0
sealing_sw_binding_3_rd_A	19699870	3407	0	0
sealing_sw_binding_4_rd_A	19699870	3209	0	0
sealing_sw_binding_5_rd_A	19699870	3337	0	0
sealing_sw_binding_6_rd_A	19699870	3288	0	0
sealing_sw_binding_7_rd_A	19699870	3193	0	0
sideload_clear_rd_A	19699870	3251	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	14717	0	0
T18	33579	1138	0	0
T66	0	272	0	0
T72	23091	0	0	0
T73	4545	0	0	0
T74	6330	0	0	0
T75	1947	0	0	0
T76	13208	0	0	0
T77	21501	0	0	0
T78	2334	0	0	0
T80	0	183	0	0
T84	14304	0	0	0
T94	0	48	0	0
T95	0	19	0	0
T96	0	339	0	0
T97	0	701	0	0
T98	0	45	0	0
T99	9441	0	0	0
T100	0	411	0	0
T183	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3284	0	0
T49	107751	0	0	0
T80	28601	21	0	0
T81	0	213	0	0
T86	0	30	0	0
T96	0	28	0	0
T142	0	13	0	0
T153	6624	0	0	0
T156	0	48	0	0
T184	0	11	0	0
T185	0	57	0	0
T186	0	15	0	0
T187	0	23	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3392	0	0
T49	107751	0	0	0
T80	28601	36	0	0
T81	0	251	0	0
T86	0	40	0	0
T96	0	41	0	0
T142	0	17	0	0
T153	6624	0	0	0
T156	0	38	0	0
T184	0	11	0	0
T185	0	51	0	0
T186	0	34	0	0
T187	0	29	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3337	0	0
T49	107751	0	0	0
T80	28601	37	0	0
T81	0	222	0	0
T86	0	33	0	0
T96	0	39	0	0
T142	0	25	0	0
T153	6624	0	0	0
T156	0	19	0	0
T184	0	7	0	0
T185	0	56	0	0
T186	0	34	0	0
T187	0	23	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3246	0	0
T49	107751	0	0	0
T80	28601	20	0	0
T81	0	238	0	0
T86	0	27	0	0
T96	0	8	0	0
T142	0	10	0	0
T153	6624	0	0	0
T156	0	45	0	0
T184	0	22	0	0
T185	0	88	0	0
T186	0	40	0	0
T187	0	11	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3348	0	0
T49	107751	0	0	0
T80	28601	32	0	0
T81	0	256	0	0
T86	0	12	0	0
T96	0	28	0	0
T142	0	20	0	0
T153	6624	0	0	0
T156	0	32	0	0
T184	0	10	0	0
T185	0	83	0	0
T186	0	22	0	0
T187	0	17	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3304	0	0
T49	107751	0	0	0
T80	28601	38	0	0
T81	0	230	0	0
T86	0	24	0	0
T96	0	37	0	0
T142	0	15	0	0
T153	6624	0	0	0
T156	0	21	0	0
T184	0	21	0	0
T185	0	61	0	0
T186	0	24	0	0
T187	0	36	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3261	0	0
T49	107751	0	0	0
T80	28601	11	0	0
T81	0	225	0	0
T86	0	37	0	0
T96	0	26	0	0
T142	0	20	0	0
T153	6624	0	0	0
T156	0	33	0	0
T184	0	16	0	0
T185	0	84	0	0
T186	0	34	0	0
T187	0	30	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3256	0	0
T49	107751	0	0	0
T80	28601	33	0	0
T81	0	267	0	0
T86	0	28	0	0
T96	0	34	0	0
T142	0	25	0	0
T153	6624	0	0	0
T156	0	38	0	0
T184	0	5	0	0
T185	0	45	0	0
T186	0	32	0	0
T187	0	24	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	4311	0	0
T42	18881	0	0	0
T45	44391	0	0	0
T68	139490	66	0	0
T79	10993	0	0	0
T80	28601	49	0	0
T96	0	33	0	0
T129	4477	0	0	0
T156	0	32	0	0
T188	153729	0	0	0
T189	63457	42	0	0
T190	1631	0	0	0
T195	0	7	0	0
T196	0	26	0	0
T197	0	15	0	0
T198	0	56	0	0
T199	0	101	0	0
T200	5887	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3233	0	0
T49	107751	0	0	0
T80	28601	34	0	0
T81	0	243	0	0
T86	0	26	0	0
T96	0	13	0	0
T142	0	18	0	0
T153	6624	0	0	0
T156	0	27	0	0
T184	0	17	0	0
T185	0	49	0	0
T186	0	18	0	0
T187	0	21	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3245	0	0
T49	107751	0	0	0
T80	28601	23	0	0
T81	0	233	0	0
T86	0	34	0	0
T96	0	31	0	0
T142	0	18	0	0
T153	6624	0	0	0
T156	0	21	0	0
T184	0	12	0	0
T185	0	60	0	0
T186	0	50	0	0
T187	0	21	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3161	0	0
T49	107751	0	0	0
T80	28601	35	0	0
T81	0	199	0	0
T86	0	34	0	0
T96	0	36	0	0
T142	0	32	0	0
T153	6624	0	0	0
T156	0	35	0	0
T184	0	11	0	0
T185	0	62	0	0
T186	0	35	0	0
T187	0	29	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3409	0	0
T49	107751	0	0	0
T80	28601	35	0	0
T81	0	260	0	0
T96	0	25	0	0
T142	0	15	0	0
T153	6624	0	0	0
T156	0	29	0	0
T184	0	21	0	0
T185	0	62	0	0
T186	0	31	0	0
T187	0	51	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0
T201	0	3	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3289	0	0
T49	107751	0	0	0
T80	28601	36	0	0
T81	0	202	0	0
T86	0	34	0	0
T96	0	26	0	0
T142	0	29	0	0
T153	6624	0	0	0
T156	0	48	0	0
T184	0	18	0	0
T185	0	56	0	0
T186	0	25	0	0
T187	0	40	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3330	0	0
T49	107751	0	0	0
T80	28601	48	0	0
T81	0	184	0	0
T86	0	33	0	0
T96	0	57	0	0
T142	0	26	0	0
T153	6624	0	0	0
T156	0	38	0	0
T184	0	4	0	0
T185	0	65	0	0
T186	0	25	0	0
T187	0	35	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3168	0	0
T49	107751	0	0	0
T80	28601	25	0	0
T81	0	207	0	0
T86	0	39	0	0
T96	0	17	0	0
T142	0	23	0	0
T153	6624	0	0	0
T156	0	29	0	0
T184	0	10	0	0
T185	0	51	0	0
T186	0	20	0	0
T187	0	24	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3427	0	0
T49	107751	0	0	0
T80	28601	42	0	0
T81	0	194	0	0
T86	0	42	0	0
T96	0	31	0	0
T142	0	39	0	0
T153	6624	0	0	0
T156	0	23	0	0
T184	0	8	0	0
T185	0	60	0	0
T186	0	42	0	0
T187	0	24	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3210	0	0
T49	107751	0	0	0
T80	28601	15	0	0
T81	0	253	0	0
T86	0	19	0	0
T96	0	18	0	0
T142	0	24	0	0
T153	6624	0	0	0
T156	0	10	0	0
T184	0	9	0	0
T185	0	47	0	0
T186	0	22	0	0
T187	0	18	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3370	0	0
T49	107751	0	0	0
T80	28601	37	0	0
T81	0	238	0	0
T86	0	25	0	0
T96	0	43	0	0
T142	0	44	0	0
T153	6624	0	0	0
T156	0	8	0	0
T184	0	38	0	0
T185	0	82	0	0
T186	0	42	0	0
T187	0	15	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3169	0	0
T49	107751	0	0	0
T80	28601	14	0	0
T81	0	206	0	0
T86	0	24	0	0
T96	0	22	0	0
T142	0	15	0	0
T153	6624	0	0	0
T156	0	40	0	0
T184	0	21	0	0
T185	0	46	0	0
T186	0	32	0	0
T187	0	36	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3424	0	0
T49	107751	0	0	0
T80	28601	27	0	0
T81	0	289	0	0
T86	0	21	0	0
T96	0	15	0	0
T142	0	31	0	0
T153	6624	0	0	0
T156	0	33	0	0
T184	0	2	0	0
T185	0	57	0	0
T186	0	33	0	0
T187	0	29	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3327	0	0
T49	107751	0	0	0
T80	28601	27	0	0
T81	0	213	0	0
T86	0	23	0	0
T96	0	42	0	0
T142	0	28	0	0
T153	6624	0	0	0
T156	0	48	0	0
T184	0	7	0	0
T185	0	67	0	0
T186	0	36	0	0
T187	0	33	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3256	0	0
T49	107751	0	0	0
T80	28601	27	0	0
T81	0	239	0	0
T86	0	32	0	0
T96	0	18	0	0
T142	0	18	0	0
T153	6624	0	0	0
T156	0	26	0	0
T184	0	19	0	0
T185	0	74	0	0
T186	0	21	0	0
T187	0	34	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3072	0	0
T49	107751	0	0	0
T80	28601	24	0	0
T81	0	256	0	0
T86	0	20	0	0
T96	0	32	0	0
T142	0	24	0	0
T153	6624	0	0	0
T156	0	29	0	0
T184	0	7	0	0
T185	0	54	0	0
T186	0	42	0	0
T187	0	43	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3434	0	0
T49	107751	0	0	0
T80	28601	29	0	0
T81	0	228	0	0
T86	0	40	0	0
T96	0	17	0	0
T142	0	18	0	0
T153	6624	0	0	0
T156	0	14	0	0
T184	0	17	0	0
T185	0	58	0	0
T186	0	28	0	0
T187	0	19	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3407	0	0
T49	107751	0	0	0
T80	28601	28	0	0
T81	0	239	0	0
T86	0	20	0	0
T96	0	58	0	0
T142	0	18	0	0
T153	6624	0	0	0
T156	0	18	0	0
T184	0	7	0	0
T185	0	52	0	0
T186	0	17	0	0
T187	0	39	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3209	0	0
T49	107751	0	0	0
T80	28601	27	0	0
T81	0	235	0	0
T86	0	18	0	0
T96	0	36	0	0
T142	0	22	0	0
T153	6624	0	0	0
T156	0	23	0	0
T184	0	19	0	0
T185	0	44	0	0
T186	0	26	0	0
T187	0	37	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3337	0	0
T49	107751	0	0	0
T80	28601	23	0	0
T81	0	255	0	0
T86	0	34	0	0
T96	0	49	0	0
T142	0	37	0	0
T153	6624	0	0	0
T156	0	42	0	0
T184	0	5	0	0
T185	0	47	0	0
T186	0	16	0	0
T187	0	29	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3288	0	0
T49	107751	0	0	0
T80	28601	34	0	0
T81	0	235	0	0
T86	0	21	0	0
T96	0	37	0	0
T142	0	26	0	0
T153	6624	0	0	0
T156	0	24	0	0
T184	0	8	0	0
T185	0	46	0	0
T186	0	19	0	0
T187	0	26	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3193	0	0
T49	107751	0	0	0
T80	28601	56	0	0
T81	0	253	0	0
T86	0	33	0	0
T96	0	30	0	0
T142	0	26	0	0
T153	6624	0	0	0
T156	0	48	0	0
T185	0	59	0	0
T186	0	20	0	0
T187	0	41	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0
T202	0	5	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19699870	3251	0	0
T49	107751	0	0	0
T80	28601	17	0	0
T81	0	235	0	0
T86	0	25	0	0
T96	0	35	0	0
T142	0	43	0	0
T153	6624	0	0	0
T156	0	19	0	0
T184	0	9	0	0
T185	0	62	0	0
T186	0	39	0	0
T187	0	21	0	0
T188	153729	0	0	0
T189	63457	0	0	0
T190	1631	0	0	0
T191	167336	0	0	0
T192	2735	0	0	0
T193	4320	0	0	0
T194	11968	0	0	0