Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4018475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

607177

1

T1

97

T2

383

T3

326

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4221788	1			T1	405		T2	228		T3	408
values[0x0]	200735	1			T1	56		T2	189		T3	117
values[0x1]	203129	1			T1	50		T2	187		T3	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2736030	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1889622

1

T1

233

T2

430

T3

421

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15943	1			T2	3		T4	1		T13	8
valid_sources[0x01]	21319	1			T2	3		T3	2		T4	1
valid_sources[0x02]	14070	1			T1	3		T2	3		T3	2
valid_sources[0x03]	13276	1			T1	3		T15	6		T44	1
valid_sources[0x04]	14885	1			T3	3		T16	6		T44	1
valid_sources[0x05]	13450	1			T1	2		T2	1		T3	2
valid_sources[0x06]	14105	1			T2	2		T3	2		T4	2
valid_sources[0x07]	13794	1			T1	1		T2	3		T3	4
valid_sources[0x08]	17639	1			T1	1		T2	1		T3	4
valid_sources[0x09]	16761	1			T1	2		T3	1		T4	1
valid_sources[0x0a]	15460	1			T1	4		T3	1		T4	2
valid_sources[0x0b]	18331	1			T1	5		T2	2		T3	1
valid_sources[0x0c]	13652	1			T1	3		T2	4		T3	2
valid_sources[0x0d]	15221	1			T1	1		T2	2		T3	1
valid_sources[0x0e]	14041	1			T1	3		T2	4		T4	1
valid_sources[0x0f]	13550	1			T1	2		T2	3		T3	1
valid_sources[0x10]	13817	1			T1	2		T2	4		T3	2
valid_sources[0x11]	14925	1			T1	2		T2	2		T3	5
valid_sources[0x12]	14465	1			T1	7		T2	2		T4	2
valid_sources[0x13]	26832	1			T1	5		T2	2		T3	6
valid_sources[0x14]	14595	1			T1	1		T2	2		T3	2
valid_sources[0x15]	22928	1			T1	2		T2	2		T3	1
valid_sources[0x16]	13590	1			T1	3		T2	3		T3	3
valid_sources[0x17]	24846	1			T1	2		T3	5		T4	1
valid_sources[0x18]	13845	1			T2	1		T3	5		T4	1
valid_sources[0x19]	13446	1			T1	2		T2	2		T3	2
valid_sources[0x1a]	14575	1			T1	4		T2	2		T3	2
valid_sources[0x1b]	30126	1			T1	2		T2	3		T4	1
valid_sources[0x1c]	13977	1			T1	1		T2	2		T3	3
valid_sources[0x1d]	15157	1			T3	4		T15	3		T16	16
valid_sources[0x1e]	13628	1			T1	1		T2	6		T3	9
valid_sources[0x1f]	20387	1			T1	4		T2	5		T3	8
valid_sources[0x20]	13603	1			T1	1		T2	1		T3	2
valid_sources[0x21]	15105	1			T1	2		T2	1		T3	4
valid_sources[0x22]	14825	1			T1	3		T2	2		T3	5
valid_sources[0x23]	14499	1			T2	1		T3	10		T4	7
valid_sources[0x24]	16706	1			T1	2		T2	4		T3	3
valid_sources[0x25]	15010	1			T1	1		T2	2		T3	2
valid_sources[0x26]	31095	1			T2	5		T4	3		T13	2
valid_sources[0x27]	15418	1			T1	3		T2	3		T3	1
valid_sources[0x28]	29769	1			T1	1		T2	2		T3	4
valid_sources[0x29]	14655	1			T1	3		T2	2		T3	5
valid_sources[0x2a]	22920	1			T1	2		T2	1		T3	2
valid_sources[0x2b]	15663	1			T1	2		T2	1		T3	1
valid_sources[0x2c]	13287	1			T1	1		T3	1		T4	1
valid_sources[0x2d]	14116	1			T1	1		T2	2		T3	2
valid_sources[0x2e]	15197	1			T1	2		T2	2		T3	2
valid_sources[0x2f]	13357	1			T1	2		T2	5		T4	4
valid_sources[0x30]	13534	1			T1	2		T2	1		T3	5
valid_sources[0x31]	14641	1			T1	3		T2	1		T3	12
valid_sources[0x32]	14012	1			T1	3		T2	2		T3	1
valid_sources[0x33]	22778	1			T1	1		T2	2		T3	5
valid_sources[0x34]	14854	1			T1	2		T3	2		T13	3
valid_sources[0x35]	25357	1			T1	3		T3	5		T4	2
valid_sources[0x36]	19957	1			T1	3		T2	5		T3	2
valid_sources[0x37]	14218	1			T1	3		T2	2		T3	3
valid_sources[0x38]	15263	1			T2	9		T3	1		T4	2
valid_sources[0x39]	16550	1			T1	5		T2	2		T3	6
valid_sources[0x3a]	19497	1			T1	3		T2	3		T3	1
valid_sources[0x3b]	15266	1			T1	1		T2	3		T3	9
valid_sources[0x3c]	14267	1			T1	5		T2	5		T4	1
valid_sources[0x3d]	14809	1			T2	3		T3	4		T4	2
valid_sources[0x3e]	14580	1			T1	3		T2	2		T3	2
valid_sources[0x3f]	14399	1			T4	2		T13	2		T15	1
valid_sources[0x40]	14201	1			T1	1		T2	3		T3	3
valid_sources[0x41]	13867	1			T1	1		T2	1		T4	2
valid_sources[0x42]	14166	1			T1	2		T2	6		T4	5
valid_sources[0x43]	15620	1			T2	2		T4	1		T15	4
valid_sources[0x44]	15092	1			T1	2		T2	4		T3	5
valid_sources[0x45]	15521	1			T3	1		T4	1		T13	6
valid_sources[0x46]	14670	1			T1	2		T2	2		T3	1
valid_sources[0x47]	13749	1			T1	1		T3	2		T4	3
valid_sources[0x48]	13783	1			T1	2		T2	3		T3	2
valid_sources[0x49]	14396	1			T1	4		T2	4		T3	1
valid_sources[0x4a]	14971	1			T1	2		T2	1		T3	3
valid_sources[0x4b]	14306	1			T1	3		T2	5		T3	5
valid_sources[0x4c]	15949	1			T1	1		T2	3		T3	2
valid_sources[0x4d]	26306	1			T1	3		T2	2		T3	1
valid_sources[0x4e]	15833	1			T1	2		T2	2		T3	1
valid_sources[0x4f]	14183	1			T2	1		T3	1		T4	4
valid_sources[0x50]	15516	1			T1	1		T2	2		T3	4
valid_sources[0x51]	27155	1			T1	2		T2	2		T3	5
valid_sources[0x52]	13957	1			T1	2		T2	1		T3	1
valid_sources[0x53]	13386	1			T1	3		T2	2		T3	2
valid_sources[0x54]	13327	1			T1	6		T2	1		T15	2
valid_sources[0x55]	16035	1			T1	4		T2	2		T3	4
valid_sources[0x56]	14111	1			T1	5		T2	1		T13	4
valid_sources[0x57]	15449	1			T1	1		T3	3		T4	1
valid_sources[0x58]	20134	1			T1	2		T2	3		T3	4
valid_sources[0x59]	15982	1			T1	3		T2	1		T3	1
valid_sources[0x5a]	69722	1			T1	2		T2	5		T4	1
valid_sources[0x5b]	14022	1			T1	1		T2	2		T4	3
valid_sources[0x5c]	25972	1			T2	1		T4	1		T13	4
valid_sources[0x5d]	15424	1			T1	6		T2	6		T3	1
valid_sources[0x5e]	18123	1			T1	2		T2	12		T3	1
valid_sources[0x5f]	19490	1			T1	1		T2	2		T3	6
valid_sources[0x60]	15127	1			T3	1		T4	1		T44	2
valid_sources[0x61]	41845	1			T1	2		T2	4		T3	4
valid_sources[0x62]	13508	1			T1	2		T2	4		T3	3
valid_sources[0x63]	13795	1			T2	5		T3	4		T15	2
valid_sources[0x64]	38336	1			T1	1		T2	2		T4	3
valid_sources[0x65]	14216	1			T1	2		T2	2		T3	2
valid_sources[0x66]	16596	1			T1	2		T2	4		T3	6
valid_sources[0x67]	14998	1			T3	5		T13	2		T15	2
valid_sources[0x68]	16859	1			T1	2		T2	2		T4	1
valid_sources[0x69]	14439	1			T1	1		T2	2		T3	1
valid_sources[0x6a]	14856	1			T1	1		T2	2		T3	3
valid_sources[0x6b]	16358	1			T1	1		T2	3		T3	8
valid_sources[0x6c]	19644	1			T1	1		T2	2		T3	8
valid_sources[0x6d]	225939	1			T1	2		T2	3		T3	7
valid_sources[0x6e]	14415	1			T1	2		T2	3		T4	1
valid_sources[0x6f]	15624	1			T1	4		T2	4		T3	2
valid_sources[0x70]	14480	1			T1	3		T2	2		T3	5
valid_sources[0x71]	15943	1			T1	1		T2	5		T3	6
valid_sources[0x72]	13469	1			T1	5		T2	1		T3	7
valid_sources[0x73]	17243	1			T1	2		T2	1		T3	2
valid_sources[0x74]	13885	1			T1	3		T2	2		T3	2
valid_sources[0x75]	13892	1			T1	4		T2	2		T3	3
valid_sources[0x76]	31896	1			T1	2		T2	3		T4	3
valid_sources[0x77]	13586	1			T1	3		T15	8		T120	2
valid_sources[0x78]	17128	1			T1	1		T2	2		T4	2
valid_sources[0x79]	19404	1			T1	1		T2	2		T3	4
valid_sources[0x7a]	14419	1			T1	1		T2	1		T3	1
valid_sources[0x7b]	15494	1			T1	3		T2	6		T3	4
valid_sources[0x7c]	13652	1			T2	2		T3	9		T15	2
valid_sources[0x7d]	28918	1			T1	5		T2	1		T3	1
valid_sources[0x7e]	14680	1			T1	3		T2	3		T3	2
valid_sources[0x7f]	13878	1			T1	2		T2	2		T3	2
valid_sources[0x80]	26627	1			T1	1		T2	2		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333209

1

T1

22

T2

93

T3

150

values[0x0]

all_enables

biggest_size

144116

1

T1

42

T2

145

T3

79

values[0x1]

all_enables

biggest_size

129852

1

T1

33

T2

145

T3

97