Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27647101	12267	0	0
attest_sw_binding_0_rd_A	27647101	2880	0	0
attest_sw_binding_1_rd_A	27647101	2935	0	0
attest_sw_binding_2_rd_A	27647101	3083	0	0
attest_sw_binding_3_rd_A	27647101	3354	0	0
attest_sw_binding_4_rd_A	27647101	3127	0	0
attest_sw_binding_5_rd_A	27647101	2963	0	0
attest_sw_binding_6_rd_A	27647101	2933	0	0
attest_sw_binding_7_rd_A	27647101	3263	0	0
intr_enable_rd_A	27647101	3701	0	0
key_version_rd_A	27647101	3180	0	0
max_creator_key_ver_regwen_rd_A	27647101	3068	0	0
max_owner_int_key_ver_regwen_rd_A	27647101	3120	0	0
max_owner_key_ver_regwen_rd_A	27647101	3169	0	0
reseed_interval_regwen_rd_A	27647101	3013	0	0
salt_0_rd_A	27647101	2892	0	0
salt_1_rd_A	27647101	3099	0	0
salt_2_rd_A	27647101	2946	0	0
salt_3_rd_A	27647101	3210	0	0
salt_4_rd_A	27647101	3076	0	0
salt_5_rd_A	27647101	3076	0	0
salt_6_rd_A	27647101	3093	0	0
salt_7_rd_A	27647101	2996	0	0
sealing_sw_binding_0_rd_A	27647101	3038	0	0
sealing_sw_binding_1_rd_A	27647101	3073	0	0
sealing_sw_binding_2_rd_A	27647101	3148	0	0
sealing_sw_binding_3_rd_A	27647101	3104	0	0
sealing_sw_binding_4_rd_A	27647101	2873	0	0
sealing_sw_binding_5_rd_A	27647101	3129	0	0
sealing_sw_binding_6_rd_A	27647101	2997	0	0
sealing_sw_binding_7_rd_A	27647101	3095	0	0
sideload_clear_rd_A	27647101	2916	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	12267	0	0
T28	11771	118	0	0
T36	10451	0	0	0
T45	0	275	0	0
T46	0	254	0	0
T47	0	259	0	0
T48	0	225	0	0
T49	0	46	0	0
T50	0	54	0	0
T51	0	133	0	0
T52	0	164	0	0
T53	0	323	0	0
T54	1923	0	0	0
T55	1982	0	0	0
T56	3076	0	0	0
T57	3159	0	0	0
T58	5581	0	0	0
T59	2947	0	0	0
T60	15389	0	0	0
T61	7461	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2880	0	0
T47	48929	9	0	0
T50	0	54	0	0
T51	0	53	0	0
T52	0	62	0	0
T104	3327	0	0	0
T161	0	19	0	0
T168	0	13	0	0
T195	0	31	0	0
T196	0	46	0	0
T197	0	83	0	0
T198	0	75	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2935	0	0
T47	48929	44	0	0
T50	0	49	0	0
T51	0	48	0	0
T52	0	65	0	0
T104	3327	0	0	0
T161	0	29	0	0
T168	0	25	0	0
T195	0	23	0	0
T196	0	76	0	0
T197	0	61	0	0
T198	0	65	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3083	0	0
T47	48929	20	0	0
T50	0	48	0	0
T51	0	85	0	0
T52	0	77	0	0
T104	3327	0	0	0
T161	0	41	0	0
T168	0	16	0	0
T195	0	32	0	0
T196	0	63	0	0
T197	0	25	0	0
T198	0	58	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3354	0	0
T47	48929	28	0	0
T50	0	63	0	0
T51	0	55	0	0
T52	0	67	0	0
T104	3327	0	0	0
T161	0	42	0	0
T168	0	8	0	0
T195	0	8	0	0
T196	0	49	0	0
T197	0	60	0	0
T198	0	59	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3127	0	0
T47	48929	19	0	0
T50	0	54	0	0
T51	0	62	0	0
T52	0	45	0	0
T104	3327	0	0	0
T161	0	32	0	0
T168	0	18	0	0
T195	0	9	0	0
T196	0	46	0	0
T197	0	58	0	0
T198	0	66	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2963	0	0
T47	48929	19	0	0
T50	0	37	0	0
T51	0	70	0	0
T52	0	35	0	0
T104	3327	0	0	0
T161	0	47	0	0
T168	0	15	0	0
T195	0	46	0	0
T196	0	52	0	0
T197	0	41	0	0
T198	0	53	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2933	0	0
T47	48929	44	0	0
T50	0	23	0	0
T51	0	55	0	0
T52	0	53	0	0
T104	3327	0	0	0
T161	0	37	0	0
T168	0	5	0	0
T195	0	24	0	0
T196	0	48	0	0
T197	0	44	0	0
T198	0	83	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3263	0	0
T47	48929	46	0	0
T50	0	68	0	0
T51	0	42	0	0
T52	0	79	0	0
T104	3327	0	0	0
T161	0	29	0	0
T168	0	18	0	0
T195	0	30	0	0
T196	0	53	0	0
T197	0	37	0	0
T198	0	62	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3701	0	0
T7	0	19	0	0
T47	48929	18	0	0
T50	0	84	0	0
T51	0	117	0	0
T52	0	78	0	0
T104	3327	0	0	0
T168	0	15	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0
T207	0	33	0	0
T208	0	29	0	0
T209	0	5	0	0
T210	0	67	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3180	0	0
T47	48929	29	0	0
T50	0	67	0	0
T51	0	49	0	0
T52	0	60	0	0
T104	3327	0	0	0
T161	0	35	0	0
T168	0	13	0	0
T195	0	7	0	0
T196	0	49	0	0
T197	0	69	0	0
T198	0	85	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3068	0	0
T47	48929	21	0	0
T50	0	66	0	0
T51	0	66	0	0
T52	0	61	0	0
T104	3327	0	0	0
T161	0	32	0	0
T168	0	11	0	0
T195	0	23	0	0
T196	0	35	0	0
T197	0	61	0	0
T198	0	86	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3120	0	0
T47	48929	41	0	0
T50	0	65	0	0
T51	0	69	0	0
T52	0	63	0	0
T104	3327	0	0	0
T161	0	49	0	0
T168	0	25	0	0
T195	0	28	0	0
T196	0	60	0	0
T197	0	56	0	0
T198	0	59	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3169	0	0
T47	48929	26	0	0
T50	0	67	0	0
T51	0	69	0	0
T52	0	76	0	0
T104	3327	0	0	0
T161	0	37	0	0
T168	0	21	0	0
T195	0	18	0	0
T196	0	61	0	0
T197	0	65	0	0
T198	0	31	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3013	0	0
T47	48929	37	0	0
T50	0	56	0	0
T51	0	57	0	0
T52	0	47	0	0
T104	3327	0	0	0
T161	0	43	0	0
T168	0	10	0	0
T195	0	20	0	0
T196	0	30	0	0
T197	0	81	0	0
T198	0	61	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2892	0	0
T47	48929	16	0	0
T50	0	36	0	0
T51	0	56	0	0
T52	0	51	0	0
T104	3327	0	0	0
T161	0	42	0	0
T168	0	6	0	0
T195	0	10	0	0
T196	0	22	0	0
T197	0	52	0	0
T198	0	38	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3099	0	0
T47	48929	49	0	0
T50	0	64	0	0
T51	0	67	0	0
T52	0	37	0	0
T104	3327	0	0	0
T161	0	44	0	0
T168	0	21	0	0
T195	0	13	0	0
T196	0	104	0	0
T197	0	60	0	0
T198	0	37	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2946	0	0
T47	48929	24	0	0
T50	0	48	0	0
T51	0	47	0	0
T52	0	52	0	0
T104	3327	0	0	0
T161	0	39	0	0
T168	0	8	0	0
T195	0	6	0	0
T196	0	57	0	0
T197	0	38	0	0
T198	0	88	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3210	0	0
T47	48929	13	0	0
T50	0	62	0	0
T51	0	33	0	0
T52	0	80	0	0
T104	3327	0	0	0
T168	0	21	0	0
T195	0	17	0	0
T196	0	54	0	0
T197	0	50	0	0
T198	0	58	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0
T211	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3076	0	0
T47	48929	37	0	0
T50	0	53	0	0
T51	0	61	0	0
T52	0	51	0	0
T104	3327	0	0	0
T161	0	46	0	0
T168	0	18	0	0
T195	0	24	0	0
T196	0	24	0	0
T197	0	44	0	0
T198	0	40	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3076	0	0
T47	48929	21	0	0
T50	0	51	0	0
T51	0	42	0	0
T52	0	76	0	0
T104	3327	0	0	0
T168	0	10	0	0
T195	0	14	0	0
T196	0	58	0	0
T197	0	48	0	0
T198	0	78	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0
T212	0	5	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3093	0	0
T47	48929	41	0	0
T50	0	58	0	0
T51	0	61	0	0
T52	0	64	0	0
T104	3327	0	0	0
T161	0	29	0	0
T168	0	8	0	0
T195	0	18	0	0
T196	0	58	0	0
T197	0	46	0	0
T198	0	66	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2996	0	0
T47	48929	14	0	0
T50	0	59	0	0
T51	0	56	0	0
T52	0	63	0	0
T104	3327	0	0	0
T161	0	51	0	0
T168	0	13	0	0
T195	0	16	0	0
T196	0	63	0	0
T197	0	60	0	0
T198	0	63	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3038	0	0
T47	48929	42	0	0
T50	0	50	0	0
T51	0	73	0	0
T52	0	72	0	0
T104	3327	0	0	0
T168	0	32	0	0
T195	0	21	0	0
T196	0	50	0	0
T197	0	55	0	0
T198	0	36	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0
T213	0	8	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3073	0	0
T47	48929	31	0	0
T50	0	93	0	0
T51	0	35	0	0
T52	0	44	0	0
T104	3327	0	0	0
T161	0	35	0	0
T168	0	10	0	0
T195	0	6	0	0
T196	0	67	0	0
T197	0	49	0	0
T198	0	62	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3148	0	0
T47	48929	29	0	0
T50	0	48	0	0
T51	0	66	0	0
T52	0	77	0	0
T104	3327	0	0	0
T161	0	32	0	0
T168	0	32	0	0
T195	0	17	0	0
T196	0	65	0	0
T197	0	71	0	0
T198	0	84	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3104	0	0
T47	48929	38	0	0
T50	0	59	0	0
T51	0	64	0	0
T52	0	67	0	0
T104	3327	0	0	0
T168	0	5	0	0
T195	0	20	0	0
T196	0	49	0	0
T197	0	60	0	0
T198	0	50	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0
T214	0	6	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2873	0	0
T47	48929	43	0	0
T50	0	36	0	0
T51	0	45	0	0
T52	0	50	0	0
T104	3327	0	0	0
T161	0	51	0	0
T168	0	22	0	0
T195	0	13	0	0
T196	0	59	0	0
T197	0	64	0	0
T198	0	53	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3129	0	0
T47	48929	33	0	0
T50	0	56	0	0
T51	0	64	0	0
T52	0	58	0	0
T104	3327	0	0	0
T168	0	17	0	0
T195	0	46	0	0
T196	0	58	0	0
T197	0	39	0	0
T198	0	64	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0
T215	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2997	0	0
T47	48929	27	0	0
T50	0	64	0	0
T51	0	72	0	0
T52	0	57	0	0
T104	3327	0	0	0
T161	0	60	0	0
T168	0	14	0	0
T195	0	27	0	0
T196	0	54	0	0
T197	0	55	0	0
T198	0	65	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	3095	0	0
T47	48929	18	0	0
T50	0	63	0	0
T51	0	58	0	0
T52	0	68	0	0
T104	3327	0	0	0
T161	0	56	0	0
T168	0	20	0	0
T195	0	27	0	0
T196	0	42	0	0
T197	0	43	0	0
T198	0	56	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27647101	2916	0	0
T47	48929	16	0	0
T50	0	76	0	0
T51	0	41	0	0
T52	0	63	0	0
T104	3327	0	0	0
T161	0	35	0	0
T168	0	15	0	0
T195	0	26	0	0
T196	0	70	0	0
T197	0	41	0	0
T198	0	57	0	0
T199	19435	0	0	0
T200	8174	0	0	0
T201	55845	0	0	0
T202	13829	0	0	0
T203	7160	0	0	0
T204	1443	0	0	0
T205	7977	0	0	0
T206	5354	0	0	0