Unified Coverage Report :: Module :: prim_subreg_ext

Module : prim_subreg_ext

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_test	100.00	100.00
tb.dut.u_reg.u_alert_test_recov_operation_err	100.00	100.00
tb.dut.u_reg.u_alert_test_fatal_fault_err	100.00	100.00
tb.dut.u_reg.u_cfg_regwen	100.00	100.00
tb.dut.u_reg.u_sw_binding_regwen	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_intr_test

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.09			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_recov_operation_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.09			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_fatal_fault_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.09			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cfg_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.09			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_sw_binding_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.09			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subreg_ext

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T28 T60 T100 

Line Coverage for Instance : tb.dut.u_reg.u_intr_test

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T28 T45 T103 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_recov_operation_err

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T17 T99 T117 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_fault_err

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T17 T99 T117 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_cfg_regwen

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T28 T60 T100 

Line Coverage for Instance : tb.dut.u_reg.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T28 T45 T46