Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3076835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

605966

1

T1

192

T2

145

T3

302

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3275711	1			T1	556		T2	578		T3	428
values[0x0]	201433	1			T1	54		T2	39		T3	101
values[0x1]	205657	1			T1	44		T2	42		T3	101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2108760	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1574041

1

T1

309

T2

281

T3

377

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11582	1			T3	1		T11	19		T14	2
valid_sources[0x01]	11370	1			T2	2		T3	1		T11	6
valid_sources[0x02]	15463	1			T3	4		T11	8		T12	1
valid_sources[0x03]	11569	1			T2	8		T3	4		T4	17
valid_sources[0x04]	25179	1			T2	3		T11	9		T12	9
valid_sources[0x05]	12222	1			T2	1		T3	1		T4	3
valid_sources[0x06]	14544	1			T2	2		T4	1		T11	15
valid_sources[0x07]	14130	1			T2	1		T3	1		T11	4
valid_sources[0x08]	11801	1			T2	3		T3	3		T4	5
valid_sources[0x09]	20378	1			T3	5		T4	7		T11	22
valid_sources[0x0a]	13841	1			T2	5		T3	2		T4	2
valid_sources[0x0b]	15807	1			T2	4		T3	4		T11	16
valid_sources[0x0c]	24177	1			T2	4		T4	4		T11	4
valid_sources[0x0d]	12697	1			T2	5		T3	1		T4	4
valid_sources[0x0e]	14461	1			T2	1		T3	5		T11	14
valid_sources[0x0f]	13471	1			T2	5		T4	4		T11	5
valid_sources[0x10]	11108	1			T2	1		T3	3		T4	2
valid_sources[0x11]	11815	1			T3	4		T4	8		T11	17
valid_sources[0x12]	11757	1			T3	4		T11	13		T12	22
valid_sources[0x13]	11356	1			T2	2		T3	3		T4	4
valid_sources[0x14]	18163	1			T2	5		T3	3		T4	2
valid_sources[0x15]	11502	1			T2	8		T3	2		T4	9
valid_sources[0x16]	19600	1			T2	1		T4	9		T11	6
valid_sources[0x17]	62818	1			T2	8		T3	3		T4	3
valid_sources[0x18]	15171	1			T2	3		T11	15		T13	3
valid_sources[0x19]	12362	1			T2	1		T3	1		T11	15
valid_sources[0x1a]	27683	1			T2	1		T3	2		T11	10
valid_sources[0x1b]	11641	1			T2	2		T3	4		T4	5
valid_sources[0x1c]	11265	1			T2	3		T3	2		T11	10
valid_sources[0x1d]	12127	1			T3	4		T4	15		T11	11
valid_sources[0x1e]	12268	1			T2	7		T3	3		T11	8
valid_sources[0x1f]	17988	1			T1	654		T3	4		T11	11
valid_sources[0x20]	12291	1			T2	2		T3	5		T4	1
valid_sources[0x21]	12505	1			T2	2		T3	2		T4	10
valid_sources[0x22]	12189	1			T2	5		T3	6		T11	10
valid_sources[0x23]	11053	1			T4	19		T11	8		T13	4
valid_sources[0x24]	13918	1			T2	1		T3	3		T11	15
valid_sources[0x25]	12056	1			T2	1		T3	3		T11	19
valid_sources[0x26]	13153	1			T3	5		T4	8		T11	5
valid_sources[0x27]	12404	1			T2	2		T3	3		T4	15
valid_sources[0x28]	14692	1			T2	6		T4	4		T11	10
valid_sources[0x29]	11601	1			T3	6		T11	7		T12	29
valid_sources[0x2a]	13581	1			T3	2		T11	11		T12	12
valid_sources[0x2b]	21007	1			T2	1		T3	1		T11	13
valid_sources[0x2c]	10978	1			T2	2		T3	2		T11	17
valid_sources[0x2d]	11929	1			T2	17		T3	2		T4	12
valid_sources[0x2e]	11709	1			T2	7		T11	11		T12	14
valid_sources[0x2f]	26731	1			T2	3		T3	2		T11	11
valid_sources[0x30]	11491	1			T2	3		T3	1		T4	5
valid_sources[0x31]	10984	1			T3	1		T11	9		T13	6
valid_sources[0x32]	13638	1			T2	9		T3	1		T11	12
valid_sources[0x33]	11324	1			T2	3		T3	4		T11	19
valid_sources[0x34]	14698	1			T2	11		T3	1		T11	7
valid_sources[0x35]	11623	1			T3	1		T4	9		T11	8
valid_sources[0x36]	13573	1			T2	2		T3	2		T4	5
valid_sources[0x37]	12418	1			T2	3		T3	3		T4	5
valid_sources[0x38]	11787	1			T3	5		T11	13		T12	10
valid_sources[0x39]	11401	1			T2	4		T3	1		T4	2
valid_sources[0x3a]	14819	1			T2	1		T3	4		T11	8
valid_sources[0x3b]	12241	1			T2	1		T3	1		T11	8
valid_sources[0x3c]	15375	1			T2	5		T3	2		T11	12
valid_sources[0x3d]	11497	1			T2	2		T3	4		T11	8
valid_sources[0x3e]	10461	1			T2	3		T3	2		T4	4
valid_sources[0x3f]	13231	1			T2	1		T3	1		T11	11
valid_sources[0x40]	12433	1			T2	4		T3	8		T11	8
valid_sources[0x41]	11162	1			T2	4		T3	2		T4	1
valid_sources[0x42]	10649	1			T3	1		T11	9		T14	2
valid_sources[0x43]	11365	1			T2	4		T3	5		T4	3
valid_sources[0x44]	11839	1			T3	3		T4	17		T11	4
valid_sources[0x45]	11415	1			T3	1		T4	9		T11	7
valid_sources[0x46]	29459	1			T3	1		T4	2		T11	6
valid_sources[0x47]	13147	1			T2	2		T3	1		T11	10
valid_sources[0x48]	17068	1			T3	5		T11	7		T12	13
valid_sources[0x49]	17185	1			T3	2		T4	5		T11	15
valid_sources[0x4a]	12406	1			T2	9		T3	3		T4	3
valid_sources[0x4b]	10862	1			T2	3		T3	3		T4	6
valid_sources[0x4c]	12057	1			T3	4		T11	13		T13	5
valid_sources[0x4d]	19569	1			T2	1		T3	6		T4	7
valid_sources[0x4e]	12609	1			T2	5		T3	2		T4	4
valid_sources[0x4f]	12094	1			T2	4		T4	10		T11	11
valid_sources[0x50]	10825	1			T2	3		T3	7		T4	1
valid_sources[0x51]	13316	1			T3	3		T11	7		T12	8
valid_sources[0x52]	14234	1			T2	16		T3	2		T4	9
valid_sources[0x53]	19575	1			T2	2		T3	2		T4	5
valid_sources[0x54]	24131	1			T2	5		T3	1		T4	3
valid_sources[0x55]	67142	1			T2	9		T4	4		T11	13
valid_sources[0x56]	17416	1			T2	2		T3	1		T4	1
valid_sources[0x57]	11009	1			T3	3		T11	8		T12	7
valid_sources[0x58]	11348	1			T2	1		T3	3		T11	11
valid_sources[0x59]	14969	1			T2	4		T3	2		T4	5
valid_sources[0x5a]	11612	1			T2	4		T3	2		T4	7
valid_sources[0x5b]	12418	1			T2	1		T3	2		T11	18
valid_sources[0x5c]	12207	1			T3	1		T11	8		T32	33
valid_sources[0x5d]	17950	1			T3	3		T4	8		T11	7
valid_sources[0x5e]	12240	1			T2	1		T3	5		T11	13
valid_sources[0x5f]	12009	1			T3	1		T11	12		T13	2
valid_sources[0x60]	20598	1			T11	13		T12	26		T13	6
valid_sources[0x61]	12724	1			T2	3		T3	3		T11	7
valid_sources[0x62]	11589	1			T2	9		T3	3		T11	22
valid_sources[0x63]	11359	1			T2	1		T4	13		T11	13
valid_sources[0x64]	12994	1			T2	3		T3	2		T11	8
valid_sources[0x65]	11537	1			T2	1		T3	2		T4	2
valid_sources[0x66]	12495	1			T2	3		T3	1		T4	1
valid_sources[0x67]	11817	1			T3	2		T11	7		T12	14
valid_sources[0x68]	10762	1			T3	2		T11	14		T12	8
valid_sources[0x69]	13099	1			T2	6		T3	1		T11	8
valid_sources[0x6a]	14707	1			T2	5		T3	3		T4	1
valid_sources[0x6b]	11898	1			T2	2		T3	2		T4	3
valid_sources[0x6c]	11927	1			T2	4		T3	1		T11	10
valid_sources[0x6d]	13985	1			T2	2		T3	3		T11	16
valid_sources[0x6e]	14705	1			T2	5		T3	3		T11	22
valid_sources[0x6f]	12644	1			T2	4		T3	7		T11	16
valid_sources[0x70]	14628	1			T2	1		T3	5		T4	4
valid_sources[0x71]	11235	1			T3	1		T4	4		T11	15
valid_sources[0x72]	11298	1			T2	6		T3	1		T11	13
valid_sources[0x73]	11135	1			T2	4		T3	1		T4	1
valid_sources[0x74]	12085	1			T2	2		T3	4		T11	10
valid_sources[0x75]	11469	1			T3	3		T4	10		T11	12
valid_sources[0x76]	12433	1			T2	3		T3	6		T11	11
valid_sources[0x77]	18515	1			T3	4		T11	17		T12	18
valid_sources[0x78]	10973	1			T3	1		T4	17		T11	12
valid_sources[0x79]	11419	1			T2	1		T3	5		T11	11
valid_sources[0x7a]	10842	1			T2	6		T3	1		T11	8
valid_sources[0x7b]	13869	1			T2	9		T3	1		T4	1
valid_sources[0x7c]	14505	1			T11	6		T12	5		T13	3
valid_sources[0x7d]	12962	1			T2	1		T3	3		T11	14
valid_sources[0x7e]	12747	1			T2	1		T3	2		T11	5
valid_sources[0x7f]	11482	1			T2	6		T3	6		T4	5
valid_sources[0x80]	11994	1			T3	3		T11	7		T12	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

330100

1

T1

158

T2

122

T3

167

values[0x0]

all_enables

biggest_size

144946

1

T1

21

T2

15

T3

70

values[0x1]

all_enables

biggest_size

130920

1

T1

13

T2

8

T3

65