Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24186549	18310	0	0
attest_sw_binding_0_rd_A	24186549	2403	0	0
attest_sw_binding_1_rd_A	24186549	2250	0	0
attest_sw_binding_2_rd_A	24186549	2422	0	0
attest_sw_binding_3_rd_A	24186549	2382	0	0
attest_sw_binding_4_rd_A	24186549	2423	0	0
attest_sw_binding_5_rd_A	24186549	2514	0	0
attest_sw_binding_6_rd_A	24186549	2435	0	0
attest_sw_binding_7_rd_A	24186549	2412	0	0
intr_enable_rd_A	24186549	3049	0	0
key_version_rd_A	24186549	2424	0	0
max_creator_key_ver_regwen_rd_A	24186549	2280	0	0
max_owner_int_key_ver_regwen_rd_A	24186549	2532	0	0
max_owner_key_ver_regwen_rd_A	24186549	2624	0	0
reseed_interval_regwen_rd_A	24186549	2348	0	0
salt_0_rd_A	24186549	2566	0	0
salt_1_rd_A	24186549	2646	0	0
salt_2_rd_A	24186549	2321	0	0
salt_3_rd_A	24186549	2528	0	0
salt_4_rd_A	24186549	2550	0	0
salt_5_rd_A	24186549	2447	0	0
salt_6_rd_A	24186549	2448	0	0
salt_7_rd_A	24186549	2375	0	0
sealing_sw_binding_0_rd_A	24186549	2428	0	0
sealing_sw_binding_1_rd_A	24186549	2362	0	0
sealing_sw_binding_2_rd_A	24186549	2491	0	0
sealing_sw_binding_3_rd_A	24186549	2504	0	0
sealing_sw_binding_4_rd_A	24186549	2476	0	0
sealing_sw_binding_5_rd_A	24186549	2533	0	0
sealing_sw_binding_6_rd_A	24186549	2617	0	0
sealing_sw_binding_7_rd_A	24186549	2430	0	0
sideload_clear_rd_A	24186549	2458	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	18310	0	0
T5	0	396	0	0
T35	5379	0	0	0
T36	11356	0	0	0
T37	4458	0	0	0
T45	3856	0	0	0
T48	20635	974	0	0
T51	0	32	0	0
T52	0	97	0	0
T53	0	258	0	0
T54	0	94	0	0
T55	0	258	0	0
T56	0	701	0	0
T57	6469	0	0	0
T58	11149	0	0	0
T59	42906	0	0	0
T60	4762	0	0	0
T61	10173	0	0	0
T63	0	747	0	0
T65	0	749	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2403	0	0
T74	0	18	0	0
T90	253608	0	0	0
T107	0	6	0	0
T108	0	34	0	0
T109	0	36	0	0
T144	0	8	0	0
T145	0	4	0	0
T171	4738	0	0	0
T175	16781	32	0	0
T176	0	9	0	0
T177	0	38	0	0
T178	0	31	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2250	0	0
T74	0	10	0	0
T90	253608	0	0	0
T107	0	20	0	0
T108	0	27	0	0
T109	0	22	0	0
T145	0	1	0	0
T171	4738	0	0	0
T175	16781	18	0	0
T176	0	31	0	0
T177	0	27	0	0
T178	0	25	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	14	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2422	0	0
T74	0	16	0	0
T90	253608	0	0	0
T107	0	29	0	0
T108	0	33	0	0
T109	0	26	0	0
T144	0	3	0	0
T145	0	3	0	0
T171	4738	0	0	0
T175	16781	19	0	0
T176	0	16	0	0
T177	0	32	0	0
T178	0	21	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2382	0	0
T74	0	7	0	0
T90	253608	0	0	0
T107	0	13	0	0
T108	0	49	0	0
T109	0	21	0	0
T144	0	3	0	0
T145	0	3	0	0
T171	4738	0	0	0
T175	16781	13	0	0
T176	0	21	0	0
T177	0	43	0	0
T178	0	22	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2423	0	0
T74	0	40	0	0
T90	253608	0	0	0
T107	0	8	0	0
T108	0	43	0	0
T109	0	14	0	0
T144	0	5	0	0
T145	0	5	0	0
T171	4738	0	0	0
T175	16781	22	0	0
T176	0	13	0	0
T177	0	60	0	0
T178	0	12	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2514	0	0
T74	0	60	0	0
T90	253608	0	0	0
T107	0	30	0	0
T108	0	46	0	0
T109	0	24	0	0
T144	0	4	0	0
T145	0	3	0	0
T171	4738	0	0	0
T175	16781	20	0	0
T176	0	11	0	0
T177	0	40	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	5	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2435	0	0
T74	0	46	0	0
T90	253608	0	0	0
T107	0	5	0	0
T108	0	33	0	0
T109	0	20	0	0
T144	0	1	0	0
T145	0	6	0	0
T171	4738	0	0	0
T175	16781	16	0	0
T176	0	23	0	0
T177	0	59	0	0
T178	0	17	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2412	0	0
T74	0	2	0	0
T90	253608	0	0	0
T107	0	29	0	0
T108	0	33	0	0
T109	0	18	0	0
T144	0	9	0	0
T145	0	3	0	0
T171	4738	0	0	0
T175	16781	28	0	0
T176	0	23	0	0
T177	0	39	0	0
T178	0	15	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	3049	0	0
T53	32969	0	0	0
T72	191008	0	0	0
T175	0	41	0	0
T187	20374	17	0	0
T188	0	94	0	0
T189	0	40	0	0
T190	0	20	0	0
T191	0	15	0	0
T192	0	29	0	0
T193	0	59	0	0
T194	0	45	0	0
T195	0	9	0	0
T196	7672	0	0	0
T197	18689	0	0	0
T198	2178	0	0	0
T199	50628	0	0	0
T200	1059	0	0	0
T201	4408	0	0	0
T202	4483	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2424	0	0
T74	0	29	0	0
T90	253608	0	0	0
T107	0	12	0	0
T108	0	40	0	0
T109	0	11	0	0
T145	0	2	0	0
T171	4738	0	0	0
T175	16781	21	0	0
T176	0	16	0	0
T177	0	39	0	0
T178	0	17	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	2	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2280	0	0
T74	0	33	0	0
T90	253608	0	0	0
T107	0	20	0	0
T108	0	31	0	0
T109	0	35	0	0
T145	0	3	0	0
T171	4738	0	0	0
T175	16781	26	0	0
T176	0	18	0	0
T177	0	32	0	0
T178	0	33	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	4	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2532	0	0
T74	0	13	0	0
T90	253608	0	0	0
T107	0	13	0	0
T108	0	45	0	0
T109	0	35	0	0
T144	0	10	0	0
T145	0	3	0	0
T171	4738	0	0	0
T175	16781	28	0	0
T176	0	18	0	0
T177	0	44	0	0
T178	0	21	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2624	0	0
T74	0	28	0	0
T90	253608	0	0	0
T107	0	17	0	0
T108	0	43	0	0
T109	0	56	0	0
T144	0	3	0	0
T171	4738	0	0	0
T175	16781	22	0	0
T176	0	18	0	0
T177	0	49	0	0
T178	0	17	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	7	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2348	0	0
T74	0	33	0	0
T90	253608	0	0	0
T107	0	24	0	0
T108	0	49	0	0
T109	0	41	0	0
T144	0	6	0	0
T145	0	4	0	0
T171	4738	0	0	0
T175	16781	28	0	0
T176	0	24	0	0
T177	0	36	0	0
T178	0	16	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2566	0	0
T74	0	76	0	0
T90	253608	0	0	0
T107	0	28	0	0
T108	0	63	0	0
T109	0	30	0	0
T144	0	1	0	0
T171	4738	0	0	0
T175	16781	42	0	0
T176	0	9	0	0
T177	0	45	0	0
T178	0	28	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	17	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2646	0	0
T74	0	38	0	0
T90	253608	0	0	0
T107	0	31	0	0
T108	0	31	0	0
T109	0	31	0	0
T144	0	5	0	0
T145	0	4	0	0
T171	4738	0	0	0
T175	16781	21	0	0
T176	0	12	0	0
T177	0	39	0	0
T178	0	15	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2321	0	0
T74	0	16	0	0
T90	253608	0	0	0
T107	0	19	0	0
T108	0	42	0	0
T109	0	33	0	0
T144	0	3	0	0
T145	0	8	0	0
T171	4738	0	0	0
T175	16781	26	0	0
T176	0	17	0	0
T177	0	52	0	0
T178	0	13	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2528	0	0
T74	0	34	0	0
T90	253608	0	0	0
T107	0	14	0	0
T108	0	43	0	0
T109	0	25	0	0
T145	0	2	0	0
T171	4738	0	0	0
T175	16781	36	0	0
T176	0	7	0	0
T177	0	34	0	0
T178	0	8	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2550	0	0
T74	0	30	0	0
T90	253608	0	0	0
T107	0	38	0	0
T108	0	43	0	0
T109	0	23	0	0
T144	0	10	0	0
T145	0	7	0	0
T171	4738	0	0	0
T175	16781	16	0	0
T176	0	16	0	0
T177	0	30	0	0
T178	0	22	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2447	0	0
T74	0	23	0	0
T90	253608	0	0	0
T107	0	29	0	0
T108	0	43	0	0
T109	0	4	0	0
T144	0	2	0	0
T145	0	7	0	0
T171	4738	0	0	0
T175	16781	19	0	0
T176	0	18	0	0
T177	0	37	0	0
T178	0	29	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2448	0	0
T74	0	11	0	0
T90	253608	0	0	0
T107	0	19	0	0
T108	0	32	0	0
T109	0	47	0	0
T144	0	3	0	0
T145	0	5	0	0
T171	4738	0	0	0
T175	16781	34	0	0
T176	0	5	0	0
T177	0	43	0	0
T178	0	15	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2375	0	0
T90	253608	0	0	0
T107	0	28	0	0
T108	0	49	0	0
T109	0	41	0	0
T110	0	33	0	0
T145	0	7	0	0
T171	4738	0	0	0
T175	16781	32	0	0
T176	0	22	0	0
T177	0	31	0	0
T178	0	21	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	9	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2428	0	0
T74	0	19	0	0
T90	253608	0	0	0
T107	0	22	0	0
T108	0	48	0	0
T109	0	13	0	0
T145	0	4	0	0
T171	4738	0	0	0
T175	16781	29	0	0
T176	0	25	0	0
T177	0	49	0	0
T178	0	12	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	6	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2362	0	0
T74	0	13	0	0
T90	253608	0	0	0
T107	0	32	0	0
T108	0	58	0	0
T109	0	36	0	0
T144	0	2	0	0
T171	4738	0	0	0
T175	16781	33	0	0
T176	0	18	0	0
T177	0	42	0	0
T178	0	10	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	15	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2491	0	0
T28	10433	0	0	0
T74	0	19	0	0
T107	0	27	0	0
T108	0	36	0	0
T109	0	25	0	0
T144	0	4	0	0
T145	0	1	0	0
T175	0	28	0	0
T176	0	14	0	0
T177	0	46	0	0
T201	4408	4	0	0
T202	4483	0	0	0
T203	5966	0	0	0
T204	165732	0	0	0
T205	5819	0	0	0
T206	9353	0	0	0
T207	11317	0	0	0
T208	6968	0	0	0
T209	8414	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2504	0	0
T74	0	49	0	0
T90	253608	0	0	0
T107	0	17	0	0
T108	0	55	0	0
T109	0	23	0	0
T144	0	10	0	0
T145	0	1	0	0
T171	4738	0	0	0
T175	16781	34	0	0
T176	0	12	0	0
T177	0	50	0	0
T178	0	22	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2476	0	0
T74	0	21	0	0
T90	253608	0	0	0
T107	0	24	0	0
T108	0	49	0	0
T109	0	28	0	0
T145	0	8	0	0
T171	4738	0	0	0
T175	16781	35	0	0
T176	0	20	0	0
T177	0	43	0	0
T178	0	25	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2533	0	0
T74	0	74	0	0
T90	253608	0	0	0
T107	0	40	0	0
T108	0	37	0	0
T109	0	28	0	0
T145	0	8	0	0
T171	4738	0	0	0
T175	16781	28	0	0
T176	0	22	0	0
T177	0	52	0	0
T178	0	26	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	5	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2617	0	0
T74	0	59	0	0
T90	253608	0	0	0
T107	0	24	0	0
T108	0	42	0	0
T109	0	26	0	0
T144	0	15	0	0
T145	0	6	0	0
T171	4738	0	0	0
T175	16781	29	0	0
T176	0	12	0	0
T177	0	50	0	0
T178	0	10	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2430	0	0
T74	0	41	0	0
T90	253608	0	0	0
T107	0	29	0	0
T108	0	44	0	0
T109	0	34	0	0
T144	0	2	0	0
T145	0	7	0	0
T171	4738	0	0	0
T175	16781	11	0	0
T176	0	11	0	0
T177	0	43	0	0
T178	0	26	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24186549	2458	0	0
T74	0	15	0	0
T90	253608	0	0	0
T107	0	22	0	0
T108	0	28	0	0
T109	0	35	0	0
T145	0	2	0	0
T171	4738	0	0	0
T175	16781	17	0	0
T176	0	16	0	0
T177	0	28	0	0
T178	0	27	0	0
T179	9914	0	0	0
T180	28266	0	0	0
T181	86173	0	0	0
T182	5477	0	0	0
T183	2735	0	0	0
T184	20192	0	0	0
T185	6758	0	0	0
T186	0	14	0	0