| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.43 | 98.99 | 98.07 | 98.43 | 97.67 | 98.92 | 98.63 | 91.27 |
| T1010 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.1273960760 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:22 PM UTC 24 | 26764212 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.2314386106 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:22 PM UTC 24 | 16831931 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.2844181414 | Sep 24 08:00:18 PM UTC 24 | Sep 24 08:00:22 PM UTC 24 | 195508942 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.1351851701 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:22 PM UTC 24 | 72132456 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.801330745 | Sep 24 08:00:11 PM UTC 24 | Sep 24 08:00:22 PM UTC 24 | 261767351 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2688034156 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:23 PM UTC 24 | 86416673 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1829159161 | Sep 24 08:00:16 PM UTC 24 | Sep 24 08:00:23 PM UTC 24 | 1136925503 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.72513889 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:23 PM UTC 24 | 19872956 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.4052408524 | Sep 24 08:00:25 PM UTC 24 | Sep 24 08:00:28 PM UTC 24 | 27539835 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.2474911688 | Sep 24 08:00:18 PM UTC 24 | Sep 24 08:00:23 PM UTC 24 | 145871768 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.4285231213 | Sep 24 08:00:24 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 93235427 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.546674989 | Sep 24 08:00:14 PM UTC 24 | Sep 24 08:00:23 PM UTC 24 | 339533878 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.4247133302 | Sep 24 08:00:23 PM UTC 24 | Sep 24 08:00:27 PM UTC 24 | 239987268 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3479355110 | Sep 24 08:00:16 PM UTC 24 | Sep 24 08:00:23 PM UTC 24 | 1046168524 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.226274178 | Sep 24 08:00:21 PM UTC 24 | Sep 24 08:00:24 PM UTC 24 | 22560551 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1140033424 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:24 PM UTC 24 | 91022152 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2127367744 | Sep 24 08:00:21 PM UTC 24 | Sep 24 08:00:25 PM UTC 24 | 100451080 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2266100347 | Sep 24 08:00:12 PM UTC 24 | Sep 24 08:00:25 PM UTC 24 | 1481662455 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3834361615 | Sep 24 08:00:21 PM UTC 24 | Sep 24 08:00:25 PM UTC 24 | 92677106 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.3544348203 | Sep 24 08:00:23 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 41858111 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2353310151 | Sep 24 08:00:23 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 13228661 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1566473229 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 161942124 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4171891368 | Sep 24 08:00:23 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 76708821 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2769338427 | Sep 24 08:00:16 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 1694726932 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3865168163 | Sep 24 08:00:24 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 105185862 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3756808315 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:26 PM UTC 24 | 196354090 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3391561410 | Sep 24 08:00:24 PM UTC 24 | Sep 24 08:00:27 PM UTC 24 | 91195788 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2628737526 | Sep 24 08:00:21 PM UTC 24 | Sep 24 08:00:27 PM UTC 24 | 441848826 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2163100677 | Sep 24 08:00:18 PM UTC 24 | Sep 24 08:00:27 PM UTC 24 | 3542910925 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.828194220 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:28 PM UTC 24 | 1130241538 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3931766901 | Sep 24 08:00:26 PM UTC 24 | Sep 24 08:00:28 PM UTC 24 | 41742046 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3491844004 | Sep 24 08:00:25 PM UTC 24 | Sep 24 08:00:28 PM UTC 24 | 163314009 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1586585284 | Sep 24 08:00:25 PM UTC 24 | Sep 24 08:00:29 PM UTC 24 | 66177329 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2908538841 | Sep 24 08:00:24 PM UTC 24 | Sep 24 08:00:29 PM UTC 24 | 210847255 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.533760491 | Sep 24 08:00:25 PM UTC 24 | Sep 24 08:00:29 PM UTC 24 | 378637559 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3713133160 | Sep 24 08:00:23 PM UTC 24 | Sep 24 08:00:29 PM UTC 24 | 388137012 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.3704813275 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 26793917 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3533567386 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 39289211 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2414930351 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 29052016 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.715468863 | Sep 24 08:00:20 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 1660655119 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.947418446 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 32164467 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1500564427 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 12542250 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3943063885 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 16954673 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4021175808 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 23281443 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.106106964 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 67646438 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.838707062 | Sep 24 08:00:28 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 39925677 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.166571457 | Sep 24 08:00:27 PM UTC 24 | Sep 24 08:00:30 PM UTC 24 | 116949339 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2589048034 | Sep 24 08:00:23 PM UTC 24 | Sep 24 08:00:31 PM UTC 24 | 1882709907 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3355591383 | Sep 24 08:00:27 PM UTC 24 | Sep 24 08:00:31 PM UTC 24 | 70821535 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1517340226 | Sep 24 08:00:27 PM UTC 24 | Sep 24 08:00:31 PM UTC 24 | 64658263 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3084514778 | Sep 24 08:00:24 PM UTC 24 | Sep 24 08:00:31 PM UTC 24 | 264896714 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1918486526 | Sep 24 08:00:25 PM UTC 24 | Sep 24 08:00:31 PM UTC 24 | 249223575 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1016192267 | Sep 24 08:00:24 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 707846094 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.2193673439 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 14391302 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.231030556 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 16959541 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.64506002 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 13784672 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3538765116 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 18009589 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.679168447 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 16335321 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.2055387302 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 24516970 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2831862532 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 18804248 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.3171385753 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 81527765 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2002286999 | Sep 24 08:00:30 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 97600180 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2474067158 | Sep 24 08:00:25 PM UTC 24 | Sep 24 08:00:32 PM UTC 24 | 957324036 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3186247013 | Sep 24 08:00:26 PM UTC 24 | Sep 24 08:00:34 PM UTC 24 | 811745040 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3230084108 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:34 PM UTC 24 | 25433141 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3138289891 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:34 PM UTC 24 | 8141149 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2483136065 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 50661618 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.553670046 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 19186479 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2694946787 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 20354372 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.839195163 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 48683858 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.3595944577 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 10400134 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.3545325447 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 12918930 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2154518326 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 22717095 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.3200163867 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 26349591 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3373907233 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 36986685 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1693428314 | Sep 24 08:00:32 PM UTC 24 | Sep 24 08:00:35 PM UTC 24 | 15628485 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.1281061412 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 340599574 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 07:50:15 PM UTC 24 |
| Finished | Sep 24 07:50:22 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281061412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1281061412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.2311629308 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 721655603 ps |
| CPU time | 47.85 seconds |
| Started | Sep 24 07:52:14 PM UTC 24 |
| Finished | Sep 24 07:53:04 PM UTC 24 |
| Peak memory | 231548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311629308 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2311629308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.2125166497 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 736970395 ps |
| CPU time | 12.13 seconds |
| Started | Sep 24 07:50:26 PM UTC 24 |
| Finished | Sep 24 07:50:40 PM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2125166497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.2125166497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.647801549 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 6419260130 ps |
| CPU time | 52.64 seconds |
| Started | Sep 24 07:50:23 PM UTC 24 |
| Finished | Sep 24 07:51:17 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647801549 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.647801549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.129465901 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1536466778 ps |
| CPU time | 6.73 seconds |
| Started | Sep 24 07:50:27 PM UTC 24 |
| Finished | Sep 24 07:50:35 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129465901 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.129465901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.817912470 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 606200128 ps |
| CPU time | 24.59 seconds |
| Started | Sep 24 07:51:31 PM UTC 24 |
| Finished | Sep 24 07:51:57 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=817912470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_ stress_all_with_rand_reset.817912470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2670302387 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 512960868 ps |
| CPU time | 5.25 seconds |
| Started | Sep 24 07:59:32 PM UTC 24 |
| Finished | Sep 24 07:59:38 PM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670302387 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.2670302387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3171058253 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1223043291 ps |
| CPU time | 7.73 seconds |
| Started | Sep 24 07:50:10 PM UTC 24 |
| Finished | Sep 24 07:50:19 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171058253 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3171058253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.3864346962 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 70313411 ps |
| CPU time | 4.09 seconds |
| Started | Sep 24 07:50:21 PM UTC 24 |
| Finished | Sep 24 07:50:26 PM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864346962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3864346962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.565462856 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 12966498710 ps |
| CPU time | 64.77 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:53:05 PM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565462856 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.565462856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.2887519214 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 269626902 ps |
| CPU time | 6.69 seconds |
| Started | Sep 24 07:50:36 PM UTC 24 |
| Finished | Sep 24 07:50:44 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887519214 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2887519214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.2264883588 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7958788819 ps |
| CPU time | 124.81 seconds |
| Started | Sep 24 07:51:22 PM UTC 24 |
| Finished | Sep 24 07:53:29 PM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264883588 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2264883588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.2819729777 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 436680941 ps |
| CPU time | 6.21 seconds |
| Started | Sep 24 07:52:10 PM UTC 24 |
| Finished | Sep 24 07:52:18 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819729777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2819729777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.1101481940 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 96750798 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 07:50:50 PM UTC 24 |
| Finished | Sep 24 07:50:56 PM UTC 24 |
| Peak memory | 228100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101481940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1101481940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.1076493087 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 16634086615 ps |
| CPU time | 160.43 seconds |
| Started | Sep 24 07:51:13 PM UTC 24 |
| Finished | Sep 24 07:53:56 PM UTC 24 |
| Peak memory | 227724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076493087 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1076493087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.732608321 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 530535794 ps |
| CPU time | 4.13 seconds |
| Started | Sep 24 07:59:33 PM UTC 24 |
| Finished | Sep 24 07:59:38 PM UTC 24 |
| Peak memory | 232188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732608321 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.732608321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.616774287 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 698668449 ps |
| CPU time | 41.16 seconds |
| Started | Sep 24 07:56:18 PM UTC 24 |
| Finished | Sep 24 07:57:01 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616774287 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.616774287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.444520484 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 615254143 ps |
| CPU time | 31.52 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:54:01 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444520484 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.444520484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.36881091 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 145545179 ps |
| CPU time | 7.52 seconds |
| Started | Sep 24 07:51:03 PM UTC 24 |
| Finished | Sep 24 07:51:12 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36881091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.36881091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.3443522642 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 406249840 ps |
| CPU time | 9.32 seconds |
| Started | Sep 24 07:51:26 PM UTC 24 |
| Finished | Sep 24 07:51:37 PM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443522642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3443522642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.2858287832 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 176813730 ps |
| CPU time | 9.96 seconds |
| Started | Sep 24 07:56:55 PM UTC 24 |
| Finished | Sep 24 07:57:06 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858287832 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2858287832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3533374481 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3333694785 ps |
| CPU time | 47.91 seconds |
| Started | Sep 24 07:59:29 PM UTC 24 |
| Finished | Sep 24 08:00:18 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533374481 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3533374481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.1215564817 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 702886754 ps |
| CPU time | 13.79 seconds |
| Started | Sep 24 07:51:11 PM UTC 24 |
| Finished | Sep 24 07:51:26 PM UTC 24 |
| Peak memory | 223560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215564817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1215564817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.1521869278 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 86774301 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 07:52:46 PM UTC 24 |
| Finished | Sep 24 07:52:52 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521869278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1521869278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.3314717737 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1355990910 ps |
| CPU time | 15.38 seconds |
| Started | Sep 24 07:52:16 PM UTC 24 |
| Finished | Sep 24 07:52:32 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3314717737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr _stress_all_with_rand_reset.3314717737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.2452879808 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 415711897 ps |
| CPU time | 14.29 seconds |
| Started | Sep 24 07:52:56 PM UTC 24 |
| Finished | Sep 24 07:53:11 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452879808 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2452879808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1434107012 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 420885625 ps |
| CPU time | 5.85 seconds |
| Started | Sep 24 07:56:47 PM UTC 24 |
| Finished | Sep 24 07:56:54 PM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434107012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1434107012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.1701597107 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 11026448346 ps |
| CPU time | 55.74 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:56:09 PM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701597107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1701597107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.4121200332 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 102946841 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 07:53:47 PM UTC 24 |
| Finished | Sep 24 07:53:53 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121200332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4121200332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.3481993798 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6771677735 ps |
| CPU time | 72.81 seconds |
| Started | Sep 24 07:54:00 PM UTC 24 |
| Finished | Sep 24 07:55:15 PM UTC 24 |
| Peak memory | 231676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481993798 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3481993798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.3478171972 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 53955725 ps |
| CPU time | 6.26 seconds |
| Started | Sep 24 07:51:42 PM UTC 24 |
| Finished | Sep 24 07:51:50 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478171972 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3478171972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.3124022908 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 227045607 ps |
| CPU time | 5.98 seconds |
| Started | Sep 24 07:54:38 PM UTC 24 |
| Finished | Sep 24 07:54:46 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124022908 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3124022908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.1645618512 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 119207322 ps |
| CPU time | 2.79 seconds |
| Started | Sep 24 07:52:48 PM UTC 24 |
| Finished | Sep 24 07:52:52 PM UTC 24 |
| Peak memory | 219452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645618512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1645618512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3186247013 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 811745040 ps |
| CPU time | 6.89 seconds |
| Started | Sep 24 08:00:26 PM UTC 24 |
| Finished | Sep 24 08:00:34 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186247013 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.3186247013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.1545192998 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 54003902 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 07:50:27 PM UTC 24 |
| Finished | Sep 24 07:50:30 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545192998 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1545192998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.1408246616 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 112090209 ps |
| CPU time | 3.98 seconds |
| Started | Sep 24 07:50:44 PM UTC 24 |
| Finished | Sep 24 07:50:49 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408246616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1408246616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.3899825013 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 33428399 ps |
| CPU time | 2.67 seconds |
| Started | Sep 24 07:52:13 PM UTC 24 |
| Finished | Sep 24 07:52:17 PM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899825013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3899825013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.4086143887 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 65161875926 ps |
| CPU time | 119.7 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:57:05 PM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086143887 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4086143887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.1632905613 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 8732677389 ps |
| CPU time | 44.31 seconds |
| Started | Sep 24 07:56:49 PM UTC 24 |
| Finished | Sep 24 07:57:35 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632905613 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1632905613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.1687036970 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 676540289 ps |
| CPU time | 7.92 seconds |
| Started | Sep 24 07:58:13 PM UTC 24 |
| Finished | Sep 24 07:58:22 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687036970 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1687036970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.715468863 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1660655119 ps |
| CPU time | 9.22 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715468863 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.715468863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.260390382 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 244061473 ps |
| CPU time | 6.56 seconds |
| Started | Sep 24 07:55:44 PM UTC 24 |
| Finished | Sep 24 07:55:52 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260390382 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.260390382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.319838549 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 664154875 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:52:04 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319838549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.319838549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.873123894 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 66347953 ps |
| CPU time | 5.29 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:46 PM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873123894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.873123894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.3953324037 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 129035116 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:45 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953324037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3953324037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.1413319643 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 135110971 ps |
| CPU time | 8.03 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:44 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413319643 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.1413319643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.1324467741 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 613464777 ps |
| CPU time | 4.59 seconds |
| Started | Sep 24 07:50:10 PM UTC 24 |
| Finished | Sep 24 07:50:16 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324467741 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1324467741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.348728252 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 904564924 ps |
| CPU time | 19.89 seconds |
| Started | Sep 24 07:56:14 PM UTC 24 |
| Finished | Sep 24 07:56:35 PM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=348728252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr _stress_all_with_rand_reset.348728252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.1063803358 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 692177958 ps |
| CPU time | 11.6 seconds |
| Started | Sep 24 07:57:56 PM UTC 24 |
| Finished | Sep 24 07:58:09 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063803358 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1063803358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.86960834 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 814615688 ps |
| CPU time | 22.91 seconds |
| Started | Sep 24 07:51:15 PM UTC 24 |
| Finished | Sep 24 07:51:39 PM UTC 24 |
| Peak memory | 261376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86960834 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.86960834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.456855521 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 135458997 ps |
| CPU time | 5.51 seconds |
| Started | Sep 24 07:56:55 PM UTC 24 |
| Finished | Sep 24 07:57:02 PM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456855521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.456855521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.3157715145 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1573278059 ps |
| CPU time | 36.41 seconds |
| Started | Sep 24 07:53:52 PM UTC 24 |
| Finished | Sep 24 07:54:30 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157715145 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3157715145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1445546778 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 86247869 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:25 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445546778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1445546778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.408202215 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 77174319 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 07:58:09 PM UTC 24 |
| Finished | Sep 24 07:58:14 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408202215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.408202215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.1802905565 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 47652829 ps |
| CPU time | 3.63 seconds |
| Started | Sep 24 07:50:50 PM UTC 24 |
| Finished | Sep 24 07:50:55 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802905565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1802905565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.3906227207 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 84712829 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 07:55:36 PM UTC 24 |
| Finished | Sep 24 07:55:40 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906227207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3906227207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3213620415 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 316249237 ps |
| CPU time | 5.5 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:42 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213620415 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.3213620415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.546674989 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 339533878 ps |
| CPU time | 7.8 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:23 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546674989 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.546674989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.18674808 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 818778630 ps |
| CPU time | 7.11 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:56 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18674808 -assert nopostproc +UVM_TESTNAM E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.18674808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.3580612102 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 363976460 ps |
| CPU time | 6.05 seconds |
| Started | Sep 24 07:55:01 PM UTC 24 |
| Finished | Sep 24 07:55:10 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580612102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3580612102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1265735187 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 137369978 ps |
| CPU time | 6.75 seconds |
| Started | Sep 24 07:54:43 PM UTC 24 |
| Finished | Sep 24 07:54:51 PM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265735187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1265735187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.625682775 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 853350991 ps |
| CPU time | 28.14 seconds |
| Started | Sep 24 07:55:30 PM UTC 24 |
| Finished | Sep 24 07:56:00 PM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=625682775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr _stress_all_with_rand_reset.625682775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.2733765552 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1739121423 ps |
| CPU time | 6.17 seconds |
| Started | Sep 24 07:56:11 PM UTC 24 |
| Finished | Sep 24 07:56:19 PM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733765552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2733765552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.2593495446 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 219114078 ps |
| CPU time | 6.36 seconds |
| Started | Sep 24 07:57:09 PM UTC 24 |
| Finished | Sep 24 07:57:17 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593495446 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2593495446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.110967679 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5657158205 ps |
| CPU time | 52.7 seconds |
| Started | Sep 24 07:57:24 PM UTC 24 |
| Finished | Sep 24 07:58:18 PM UTC 24 |
| Peak memory | 231640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110967679 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.110967679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2290379816 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 103440357 ps |
| CPU time | 3.54 seconds |
| Started | Sep 24 07:57:24 PM UTC 24 |
| Finished | Sep 24 07:57:28 PM UTC 24 |
| Peak memory | 219712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290379816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2290379816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.757226628 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 12549777567 ps |
| CPU time | 98.79 seconds |
| Started | Sep 24 07:58:09 PM UTC 24 |
| Finished | Sep 24 07:59:50 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757226628 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.757226628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.3743110043 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1448150964 ps |
| CPU time | 18.51 seconds |
| Started | Sep 24 07:58:30 PM UTC 24 |
| Finished | Sep 24 07:58:51 PM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743110043 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3743110043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.4023040718 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 377320152 ps |
| CPU time | 7.53 seconds |
| Started | Sep 24 07:54:07 PM UTC 24 |
| Finished | Sep 24 07:54:16 PM UTC 24 |
| Peak memory | 224148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023040718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4023040718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.1088857642 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 429688141 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:26 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088857642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1088857642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.1314633406 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 189574049 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 07:56:02 PM UTC 24 |
| Finished | Sep 24 07:56:07 PM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314633406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1314633406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.4184834117 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 61017454 ps |
| CPU time | 4.3 seconds |
| Started | Sep 24 07:57:22 PM UTC 24 |
| Finished | Sep 24 07:57:28 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184834117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4184834117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.3109430210 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 300092648 ps |
| CPU time | 4.47 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:45 PM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109430210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3109430210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.2151731176 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 52704903 ps |
| CPU time | 4.99 seconds |
| Started | Sep 24 07:54:20 PM UTC 24 |
| Finished | Sep 24 07:54:27 PM UTC 24 |
| Peak memory | 223348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151731176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2151731176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.780894845 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 251960258 ps |
| CPU time | 10.57 seconds |
| Started | Sep 24 07:54:14 PM UTC 24 |
| Finished | Sep 24 07:54:26 PM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780894845 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.780894845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.3534226795 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1043892243 ps |
| CPU time | 32.3 seconds |
| Started | Sep 24 07:54:45 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 231732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3534226795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymg r_stress_all_with_rand_reset.3534226795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.1662147387 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2525064100 ps |
| CPU time | 34.88 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:57 PM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662147387 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1662147387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.763752910 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 15321483557 ps |
| CPU time | 126.57 seconds |
| Started | Sep 24 07:55:29 PM UTC 24 |
| Finished | Sep 24 07:57:38 PM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763752910 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.763752910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.3938337414 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 123952098 ps |
| CPU time | 8.72 seconds |
| Started | Sep 24 07:57:18 PM UTC 24 |
| Finished | Sep 24 07:57:28 PM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938337414 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3938337414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.2406912725 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 44060929 ps |
| CPU time | 4.64 seconds |
| Started | Sep 24 07:52:25 PM UTC 24 |
| Finished | Sep 24 07:52:31 PM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406912725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2406912725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.2844181414 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 195508942 ps |
| CPU time | 3.37 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:22 PM UTC 24 |
| Peak memory | 225424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844181414 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.2844181414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3713133160 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 388137012 ps |
| CPU time | 4.85 seconds |
| Started | Sep 24 08:00:23 PM UTC 24 |
| Finished | Sep 24 08:00:29 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713133160 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.3713133160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.1391439648 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 109625402 ps |
| CPU time | 4.8 seconds |
| Started | Sep 24 07:59:47 PM UTC 24 |
| Finished | Sep 24 07:59:53 PM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391439648 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.1391439648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.3844756018 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1643203818 ps |
| CPU time | 5.79 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:16 PM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844756018 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.3844756018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.2424503933 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 178451414 ps |
| CPU time | 3.92 seconds |
| Started | Sep 24 07:50:21 PM UTC 24 |
| Finished | Sep 24 07:50:26 PM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424503933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2424503933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.2339474330 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 32350511 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 07:50:10 PM UTC 24 |
| Finished | Sep 24 07:50:14 PM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339474330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2339474330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.2366438054 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 199049607 ps |
| CPU time | 3.77 seconds |
| Started | Sep 24 07:50:23 PM UTC 24 |
| Finished | Sep 24 07:50:28 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366438054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2366438054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.3913931824 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 107096196 ps |
| CPU time | 4.96 seconds |
| Started | Sep 24 07:50:50 PM UTC 24 |
| Finished | Sep 24 07:50:56 PM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913931824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3913931824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.3950943522 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1988466540 ps |
| CPU time | 9.35 seconds |
| Started | Sep 24 07:53:44 PM UTC 24 |
| Finished | Sep 24 07:53:54 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950943522 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3950943522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.1429197102 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 281624285 ps |
| CPU time | 4.15 seconds |
| Started | Sep 24 07:54:01 PM UTC 24 |
| Finished | Sep 24 07:54:07 PM UTC 24 |
| Peak memory | 217340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429197102 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1429197102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2871443213 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 267931263 ps |
| CPU time | 14.77 seconds |
| Started | Sep 24 07:54:45 PM UTC 24 |
| Finished | Sep 24 07:55:01 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871443213 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2871443213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.1947998930 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 96535939 ps |
| CPU time | 6.32 seconds |
| Started | Sep 24 07:55:10 PM UTC 24 |
| Finished | Sep 24 07:55:18 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947998930 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1947998930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_random.2473232251 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 129816860 ps |
| CPU time | 6.83 seconds |
| Started | Sep 24 07:51:01 PM UTC 24 |
| Finished | Sep 24 07:51:09 PM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473232251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2473232251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.2732776503 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 84782884 ps |
| CPU time | 3.69 seconds |
| Started | Sep 24 07:56:20 PM UTC 24 |
| Finished | Sep 24 07:56:24 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732776503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2732776503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.2356764142 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 296575531 ps |
| CPU time | 6.85 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:51 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356764142 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2356764142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.2497695462 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 442954996 ps |
| CPU time | 18.47 seconds |
| Started | Sep 24 07:57:07 PM UTC 24 |
| Finished | Sep 24 07:57:27 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497695462 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2497695462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.253964720 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 402261699 ps |
| CPU time | 23.82 seconds |
| Started | Sep 24 07:58:16 PM UTC 24 |
| Finished | Sep 24 07:58:42 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253964720 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.253964720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.2192273620 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1325118186 ps |
| CPU time | 28.73 seconds |
| Started | Sep 24 07:58:32 PM UTC 24 |
| Finished | Sep 24 07:59:02 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192273620 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2192273620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.1590670949 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 76030942 ps |
| CPU time | 3.35 seconds |
| Started | Sep 24 07:59:16 PM UTC 24 |
| Finished | Sep 24 07:59:20 PM UTC 24 |
| Peak memory | 230312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590670949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1590670949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.4039675486 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2019361240 ps |
| CPU time | 48.42 seconds |
| Started | Sep 24 07:59:17 PM UTC 24 |
| Finished | Sep 24 08:00:07 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039675486 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4039675486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.2847489998 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 279812435 ps |
| CPU time | 6.13 seconds |
| Started | Sep 24 07:59:22 PM UTC 24 |
| Finished | Sep 24 07:59:30 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847489998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2847489998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.138095010 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 256905254 ps |
| CPU time | 5.39 seconds |
| Started | Sep 24 07:52:07 PM UTC 24 |
| Finished | Sep 24 07:52:14 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138095010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.138095010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.1531298544 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 722139081 ps |
| CPU time | 10.34 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:46 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531298544 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1531298544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.453656184 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 6139176964 ps |
| CPU time | 26.56 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 08:00:03 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453656184 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.453656184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3572517091 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 129140452 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:38 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572517091 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3572517091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3609577576 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 93167296 ps |
| CPU time | 2.39 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:39 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3609577576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w ith_rand_reset.3609577576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1133546523 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 21596520 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:38 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133546523 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1133546523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.824744623 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 20820455 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 07:59:33 PM UTC 24 |
| Finished | Sep 24 07:59:35 PM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824744623 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.824744623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2721487757 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 267790316 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:39 PM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721487757 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.2721487757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.964043723 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 19391652 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 07:59:33 PM UTC 24 |
| Finished | Sep 24 07:59:36 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964043723 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.964043723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.117021223 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 135403182 ps |
| CPU time | 6.13 seconds |
| Started | Sep 24 07:59:33 PM UTC 24 |
| Finished | Sep 24 07:59:40 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117021223 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.117021223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.1977042635 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 503114110 ps |
| CPU time | 8.92 seconds |
| Started | Sep 24 07:59:38 PM UTC 24 |
| Finished | Sep 24 07:59:48 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977042635 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1977042635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.606307351 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1328969199 ps |
| CPU time | 14.37 seconds |
| Started | Sep 24 07:59:37 PM UTC 24 |
| Finished | Sep 24 07:59:53 PM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606307351 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.606307351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3943936916 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 44342696 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 07:59:36 PM UTC 24 |
| Finished | Sep 24 07:59:39 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943936916 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3943936916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1183046054 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 41112125 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 07:59:39 PM UTC 24 |
| Finished | Sep 24 07:59:41 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1183046054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.1183046054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.2242709781 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 95072308 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 07:59:36 PM UTC 24 |
| Finished | Sep 24 07:59:39 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242709781 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2242709781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.1105030018 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 51871618 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 07:59:36 PM UTC 24 |
| Finished | Sep 24 07:59:38 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105030018 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1105030018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1191719244 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 76381329 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 07:59:39 PM UTC 24 |
| Finished | Sep 24 07:59:42 PM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191719244 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.1191719244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.899140854 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 180893731 ps |
| CPU time | 9.37 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:46 PM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899140854 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.899140854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.69471968 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 172112593 ps |
| CPU time | 3.87 seconds |
| Started | Sep 24 07:59:35 PM UTC 24 |
| Finished | Sep 24 07:59:40 PM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69471968 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.69471968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1495085583 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 109072213 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 08:00:11 PM UTC 24 |
| Finished | Sep 24 08:00:14 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1495085583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.1495085583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.1238934507 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 25656224 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:12 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238934507 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1238934507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.3857955963 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 76974635 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:11 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857955963 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3857955963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1807293557 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 158767353 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:14 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807293557 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.1807293557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.639375332 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 142764381 ps |
| CPU time | 4.77 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:15 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639375332 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.639375332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3360177199 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 572455012 ps |
| CPU time | 8.51 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:19 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360177199 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.3360177199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.2449382497 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 46632106 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:13 PM UTC 24 |
| Peak memory | 225352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449382497 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2449382497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.2308042359 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 270357033 ps |
| CPU time | 5.71 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:16 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308042359 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.2308042359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3407357615 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 61598647 ps |
| CPU time | 2.66 seconds |
| Started | Sep 24 08:00:12 PM UTC 24 |
| Finished | Sep 24 08:00:16 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3407357615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.3407357615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.1477069542 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 68610366 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 08:00:12 PM UTC 24 |
| Finished | Sep 24 08:00:15 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477069542 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1477069542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.1860692304 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 15573926 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:00:12 PM UTC 24 |
| Finished | Sep 24 08:00:14 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860692304 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1860692304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3554090747 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 521846046 ps |
| CPU time | 3.32 seconds |
| Started | Sep 24 08:00:12 PM UTC 24 |
| Finished | Sep 24 08:00:17 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554090747 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.3554090747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3820568448 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 513910705 ps |
| CPU time | 3.17 seconds |
| Started | Sep 24 08:00:11 PM UTC 24 |
| Finished | Sep 24 08:00:15 PM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820568448 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.3820568448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4112583080 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 236121934 ps |
| CPU time | 6.28 seconds |
| Started | Sep 24 08:00:11 PM UTC 24 |
| Finished | Sep 24 08:00:18 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112583080 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.4112583080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.937762480 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 49013654 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 08:00:11 PM UTC 24 |
| Finished | Sep 24 08:00:15 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937762480 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.937762480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.801330745 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 261767351 ps |
| CPU time | 10.45 seconds |
| Started | Sep 24 08:00:11 PM UTC 24 |
| Finished | Sep 24 08:00:22 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801330745 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.801330745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.28765361 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 64663599 ps |
| CPU time | 2.07 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:17 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=28765361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_wi th_rand_reset.28765361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.3518198597 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 25360788 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:17 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518198597 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3518198597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.173674988 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 10562159 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:16 PM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173674988 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.173674988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2537993136 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 484094012 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:18 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537993136 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.2537993136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1524004124 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 1268778601 ps |
| CPU time | 3.29 seconds |
| Started | Sep 24 08:00:12 PM UTC 24 |
| Finished | Sep 24 08:00:17 PM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524004124 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.1524004124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2266100347 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 1481662455 ps |
| CPU time | 11.14 seconds |
| Started | Sep 24 08:00:12 PM UTC 24 |
| Finished | Sep 24 08:00:25 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266100347 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.2266100347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.311334829 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 129534500 ps |
| CPU time | 3.88 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:19 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311334829 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.311334829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2867046003 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 31988024 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:19 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2867046003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.2867046003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.342637135 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 16835102 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:19 PM UTC 24 |
| Peak memory | 212668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342637135 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.342637135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.1519277341 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 41414300 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:18 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519277341 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1519277341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2467935152 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 288489943 ps |
| CPU time | 3.39 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:20 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467935152 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.2467935152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1234073094 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 72633318 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:18 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234073094 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.1234073094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1004840858 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 815287852 ps |
| CPU time | 5.83 seconds |
| Started | Sep 24 08:00:14 PM UTC 24 |
| Finished | Sep 24 08:00:21 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004840858 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.1004840858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1829159161 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1136925503 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:23 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829159161 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1829159161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3479355110 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1046168524 ps |
| CPU time | 6.41 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:23 PM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479355110 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.3479355110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2340314881 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 25369277 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:21 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2340314881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.2340314881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.2975446708 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 62339796 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:20 PM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975446708 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2975446708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.1711015847 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 10240311 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:20 PM UTC 24 |
| Peak memory | 212300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711015847 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1711015847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3227818843 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 81028203 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:21 PM UTC 24 |
| Peak memory | 215160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227818843 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.3227818843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2782802689 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 176144479 ps |
| CPU time | 3.77 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:21 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782802689 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.2782802689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2769338427 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1694726932 ps |
| CPU time | 8.61 seconds |
| Started | Sep 24 08:00:16 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769338427 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.2769338427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.2793664858 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 24197247 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:21 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793664858 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2793664858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.72513889 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 19872956 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:23 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=72513889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_wi th_rand_reset.72513889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.2314386106 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 16831931 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:22 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314386106 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2314386106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.1273960760 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 26764212 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:22 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273960760 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1273960760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1140033424 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 91022152 ps |
| CPU time | 3.15 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:24 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140033424 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.1140033424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1100251646 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 126336542 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:22 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100251646 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.1100251646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2163100677 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3542910925 ps |
| CPU time | 8.07 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:27 PM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163100677 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.2163100677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.2474911688 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 145871768 ps |
| CPU time | 3.73 seconds |
| Started | Sep 24 08:00:18 PM UTC 24 |
| Finished | Sep 24 08:00:23 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474911688 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2474911688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2127367744 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 100451080 ps |
| CPU time | 2.16 seconds |
| Started | Sep 24 08:00:21 PM UTC 24 |
| Finished | Sep 24 08:00:25 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2127367744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.2127367744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.226274178 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 22560551 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 08:00:21 PM UTC 24 |
| Finished | Sep 24 08:00:24 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226274178 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.226274178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.1351851701 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 72132456 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:22 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351851701 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1351851701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2628737526 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 441848826 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 08:00:21 PM UTC 24 |
| Finished | Sep 24 08:00:27 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628737526 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2628737526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1566473229 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 161942124 ps |
| CPU time | 4.98 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566473229 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.1566473229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3756808315 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 196354090 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756808315 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.3756808315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2688034156 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 86416673 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:23 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688034156 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2688034156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.828194220 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1130241538 ps |
| CPU time | 6.53 seconds |
| Started | Sep 24 08:00:20 PM UTC 24 |
| Finished | Sep 24 08:00:28 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828194220 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.828194220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3865168163 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 105185862 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:00:24 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3865168163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.3865168163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.3544348203 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 41858111 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:00:23 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544348203 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3544348203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2353310151 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 13228661 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:00:23 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353310151 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2353310151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4171891368 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 76708821 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:00:23 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171891368 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.4171891368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3834361615 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 92677106 ps |
| CPU time | 2.46 seconds |
| Started | Sep 24 08:00:21 PM UTC 24 |
| Finished | Sep 24 08:00:25 PM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834361615 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.3834361615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2589048034 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1882709907 ps |
| CPU time | 6.24 seconds |
| Started | Sep 24 08:00:23 PM UTC 24 |
| Finished | Sep 24 08:00:31 PM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589048034 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.2589048034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.4247133302 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 239987268 ps |
| CPU time | 2.24 seconds |
| Started | Sep 24 08:00:23 PM UTC 24 |
| Finished | Sep 24 08:00:27 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247133302 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4247133302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1586585284 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 66177329 ps |
| CPU time | 2.25 seconds |
| Started | Sep 24 08:00:25 PM UTC 24 |
| Finished | Sep 24 08:00:29 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1586585284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.1586585284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.4052408524 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 27539835 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:00:25 PM UTC 24 |
| Finished | Sep 24 08:00:28 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052408524 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.4052408524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.4285231213 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 93235427 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:00:24 PM UTC 24 |
| Finished | Sep 24 08:00:26 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285231213 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4285231213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3491844004 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 163314009 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:00:25 PM UTC 24 |
| Finished | Sep 24 08:00:28 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491844004 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3491844004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2908538841 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 210847255 ps |
| CPU time | 4.08 seconds |
| Started | Sep 24 08:00:24 PM UTC 24 |
| Finished | Sep 24 08:00:29 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908538841 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.2908538841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1016192267 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 707846094 ps |
| CPU time | 6.85 seconds |
| Started | Sep 24 08:00:24 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016192267 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.1016192267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3391561410 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 91195788 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:00:24 PM UTC 24 |
| Finished | Sep 24 08:00:27 PM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391561410 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3391561410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3084514778 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 264896714 ps |
| CPU time | 6.08 seconds |
| Started | Sep 24 08:00:24 PM UTC 24 |
| Finished | Sep 24 08:00:31 PM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084514778 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.3084514778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3355591383 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 70821535 ps |
| CPU time | 2.16 seconds |
| Started | Sep 24 08:00:27 PM UTC 24 |
| Finished | Sep 24 08:00:31 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3355591383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.3355591383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.166571457 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 116949339 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:00:27 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166571457 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.166571457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3931766901 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 41742046 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:00:26 PM UTC 24 |
| Finished | Sep 24 08:00:28 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931766901 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3931766901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1517340226 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 64658263 ps |
| CPU time | 2.27 seconds |
| Started | Sep 24 08:00:27 PM UTC 24 |
| Finished | Sep 24 08:00:31 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517340226 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.1517340226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1918486526 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 249223575 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 08:00:25 PM UTC 24 |
| Finished | Sep 24 08:00:31 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918486526 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.1918486526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2474067158 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 957324036 ps |
| CPU time | 5.91 seconds |
| Started | Sep 24 08:00:25 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474067158 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.2474067158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.533760491 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 378637559 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 08:00:25 PM UTC 24 |
| Finished | Sep 24 08:00:29 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533760491 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.533760491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.4165069424 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 510302577 ps |
| CPU time | 8.31 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:57 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165069424 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4165069424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.602786998 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 263939845 ps |
| CPU time | 17.86 seconds |
| Started | Sep 24 07:59:47 PM UTC 24 |
| Finished | Sep 24 08:00:07 PM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602786998 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.602786998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3793041967 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 111371587 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 07:59:47 PM UTC 24 |
| Finished | Sep 24 07:59:50 PM UTC 24 |
| Peak memory | 223052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793041967 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3793041967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1942809537 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 259062146 ps |
| CPU time | 3.11 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:52 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1942809537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.1942809537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.2875746761 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 78887131 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 07:59:47 PM UTC 24 |
| Finished | Sep 24 07:59:50 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875746761 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2875746761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.979627192 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 22720042 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 07:59:47 PM UTC 24 |
| Finished | Sep 24 07:59:50 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979627192 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.979627192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4270467384 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 106392280 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:52 PM UTC 24 |
| Peak memory | 215124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270467384 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.4270467384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3259631884 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 127246532 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 07:59:39 PM UTC 24 |
| Finished | Sep 24 07:59:44 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259631884 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.3259631884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.260086279 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 316570418 ps |
| CPU time | 8.65 seconds |
| Started | Sep 24 07:59:39 PM UTC 24 |
| Finished | Sep 24 07:59:49 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260086279 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.260086279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3792655002 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 810125460 ps |
| CPU time | 3.24 seconds |
| Started | Sep 24 07:59:39 PM UTC 24 |
| Finished | Sep 24 07:59:43 PM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792655002 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3792655002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.3704813275 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 26793917 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704813275 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3704813275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3533567386 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 39289211 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533567386 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3533567386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2414930351 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 29052016 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414930351 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2414930351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.3943063885 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 16954673 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943063885 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3943063885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.838707062 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 39925677 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838707062 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.838707062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.1500564427 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 12542250 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500564427 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1500564427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.947418446 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 32164467 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947418446 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.947418446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4021175808 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 23281443 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021175808 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4021175808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.106106964 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 67646438 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:00:28 PM UTC 24 |
| Finished | Sep 24 08:00:30 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106106964 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.106106964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.2193673439 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 14391302 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193673439 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2193673439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.2811394922 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1547081457 ps |
| CPU time | 15.91 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 08:00:05 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811394922 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2811394922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1616223777 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2690879122 ps |
| CPU time | 13.87 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 08:00:03 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616223777 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1616223777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3540425058 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 64831863 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:51 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540425058 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3540425058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3466952739 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 29504629 ps |
| CPU time | 2.75 seconds |
| Started | Sep 24 07:59:49 PM UTC 24 |
| Finished | Sep 24 07:59:53 PM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3466952739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.3466952739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.2496448570 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 12528578 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:50 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496448570 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2496448570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.2215009374 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 18363346 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:50 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215009374 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2215009374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3336917561 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 93677666 ps |
| CPU time | 3 seconds |
| Started | Sep 24 07:59:49 PM UTC 24 |
| Finished | Sep 24 07:59:53 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336917561 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.3336917561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4231761636 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 507158031 ps |
| CPU time | 3.39 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:52 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231761636 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.4231761636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1798139825 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 161919776 ps |
| CPU time | 10 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:59 PM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798139825 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.1798139825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.3242788930 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 48779447 ps |
| CPU time | 4.49 seconds |
| Started | Sep 24 07:59:48 PM UTC 24 |
| Finished | Sep 24 07:59:53 PM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242788930 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3242788930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.679168447 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 16335321 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679168447 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.679168447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.231030556 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 16959541 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231030556 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.231030556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.64506002 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 13784672 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64506002 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.64506002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.3171385753 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 81527765 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171385753 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3171385753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.2055387302 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 24516970 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055387302 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2055387302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2831862532 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 18804248 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831862532 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2831862532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2002286999 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 97600180 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002286999 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2002286999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3538765116 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 18009589 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 08:00:30 PM UTC 24 |
| Finished | Sep 24 08:00:32 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538765116 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3538765116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3138289891 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 8141149 ps |
| CPU time | 0.79 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:34 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138289891 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3138289891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3230084108 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 25433141 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:34 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230084108 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3230084108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.2843015332 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3064720232 ps |
| CPU time | 15.97 seconds |
| Started | Sep 24 07:59:52 PM UTC 24 |
| Finished | Sep 24 08:00:09 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843015332 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2843015332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2208330786 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 858809981 ps |
| CPU time | 12.43 seconds |
| Started | Sep 24 07:59:52 PM UTC 24 |
| Finished | Sep 24 08:00:05 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208330786 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2208330786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1431534884 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 39853749 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 07:59:52 PM UTC 24 |
| Finished | Sep 24 07:59:54 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431534884 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1431534884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3954101268 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 107481915 ps |
| CPU time | 2.57 seconds |
| Started | Sep 24 07:59:53 PM UTC 24 |
| Finished | Sep 24 07:59:57 PM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3954101268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w ith_rand_reset.3954101268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.1453126233 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 24849288 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 07:59:52 PM UTC 24 |
| Finished | Sep 24 07:59:54 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453126233 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1453126233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.2291949907 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 12109356 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 07:59:52 PM UTC 24 |
| Finished | Sep 24 07:59:54 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291949907 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2291949907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2281689605 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 245563856 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 07:59:53 PM UTC 24 |
| Finished | Sep 24 07:59:57 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281689605 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.2281689605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4158214825 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 175357366 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 07:59:49 PM UTC 24 |
| Finished | Sep 24 07:59:55 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158214825 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.4158214825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1444097607 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 218925488 ps |
| CPU time | 9.5 seconds |
| Started | Sep 24 07:59:50 PM UTC 24 |
| Finished | Sep 24 08:00:01 PM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444097607 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.1444097607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.1493588857 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2017158096 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 07:59:50 PM UTC 24 |
| Finished | Sep 24 07:59:56 PM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493588857 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1493588857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.1581865514 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 210812874 ps |
| CPU time | 5.42 seconds |
| Started | Sep 24 07:59:50 PM UTC 24 |
| Finished | Sep 24 07:59:57 PM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581865514 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.1581865514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2154518326 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 22717095 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154518326 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2154518326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.3545325447 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 12918930 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545325447 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3545325447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2694946787 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 20354372 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694946787 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2694946787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1693428314 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 15628485 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693428314 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1693428314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3373907233 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 36986685 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373907233 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3373907233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.553670046 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 19186479 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553670046 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.553670046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.3200163867 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 26349591 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200163867 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3200163867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.839195163 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 48683858 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839195163 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.839195163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.3595944577 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 10400134 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595944577 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3595944577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2483136065 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 50661618 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:00:32 PM UTC 24 |
| Finished | Sep 24 08:00:35 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483136065 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2483136065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2500292529 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 40311584 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 07:59:56 PM UTC 24 |
| Finished | Sep 24 07:59:59 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2500292529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.2500292529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1063863999 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 24900550 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 07:59:55 PM UTC 24 |
| Finished | Sep 24 07:59:58 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063863999 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1063863999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.2851406137 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 18364342 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 07:59:54 PM UTC 24 |
| Finished | Sep 24 07:59:57 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851406137 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2851406137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1591912099 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 200594947 ps |
| CPU time | 6.49 seconds |
| Started | Sep 24 07:59:55 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591912099 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1591912099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3233194124 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 277467849 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 07:59:53 PM UTC 24 |
| Finished | Sep 24 07:59:58 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233194124 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.3233194124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.517038874 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 637167100 ps |
| CPU time | 6.8 seconds |
| Started | Sep 24 07:59:54 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517038874 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.517038874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.2299555176 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 104104161 ps |
| CPU time | 3.24 seconds |
| Started | Sep 24 07:59:54 PM UTC 24 |
| Finished | Sep 24 07:59:59 PM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299555176 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2299555176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.1548384100 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 407525016 ps |
| CPU time | 6.94 seconds |
| Started | Sep 24 07:59:54 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 225416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548384100 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.1548384100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1277001626 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 43429285 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:03 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1277001626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w ith_rand_reset.1277001626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3389118662 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 41851194 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:01 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389118662 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3389118662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.2822726261 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 22546079 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:00 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822726261 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2822726261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.364188969 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 354977947 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364188969 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.364188969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.740322827 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 497372508 ps |
| CPU time | 5.3 seconds |
| Started | Sep 24 07:59:56 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740322827 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.740322827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2361508589 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 227384648 ps |
| CPU time | 8.26 seconds |
| Started | Sep 24 07:59:57 PM UTC 24 |
| Finished | Sep 24 08:00:06 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361508589 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.2361508589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.1272999900 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 109999949 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 07:59:57 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272999900 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1272999900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.2888293018 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 216492841 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 07:59:57 PM UTC 24 |
| Finished | Sep 24 08:00:01 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888293018 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.2888293018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.875320015 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 59172847 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 08:00:01 PM UTC 24 |
| Finished | Sep 24 08:00:10 PM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=875320015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_wi th_rand_reset.875320015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.1418983099 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 45418986 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:00:00 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418983099 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1418983099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.3270391086 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 10120056 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:00:00 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270391086 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3270391086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1378784755 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 63053993 ps |
| CPU time | 2.96 seconds |
| Started | Sep 24 08:00:00 PM UTC 24 |
| Finished | Sep 24 08:00:04 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378784755 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.1378784755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.38295432 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 52404499 ps |
| CPU time | 3.04 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:02 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38295432 -assert nopostproc +UVM_T ESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.38295432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3404657487 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 302933464 ps |
| CPU time | 9.16 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:09 PM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404657487 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.3404657487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.2283032320 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 427797595 ps |
| CPU time | 5.09 seconds |
| Started | Sep 24 07:59:58 PM UTC 24 |
| Finished | Sep 24 08:00:05 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283032320 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2283032320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.3934851203 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 223212124 ps |
| CPU time | 10.08 seconds |
| Started | Sep 24 07:59:59 PM UTC 24 |
| Finished | Sep 24 08:00:10 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934851203 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.3934851203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1306878962 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 202976701 ps |
| CPU time | 1.93 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:12 PM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1306878962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w ith_rand_reset.1306878962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.829818807 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 32577314 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:11 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829818807 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.829818807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.3520134405 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 39575382 ps |
| CPU time | 0.8 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:10 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520134405 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3520134405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.788063156 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 337057112 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:12 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788063156 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.788063156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1041190829 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 67522616 ps |
| CPU time | 2.01 seconds |
| Started | Sep 24 08:00:02 PM UTC 24 |
| Finished | Sep 24 08:00:10 PM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041190829 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.1041190829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3287560241 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 352507922 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 08:00:02 PM UTC 24 |
| Finished | Sep 24 08:00:12 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287560241 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.3287560241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.2111330991 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1418535459 ps |
| CPU time | 5.24 seconds |
| Started | Sep 24 08:00:02 PM UTC 24 |
| Finished | Sep 24 08:00:13 PM UTC 24 |
| Peak memory | 225428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111330991 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2111330991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1151708248 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 47706709 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:12 PM UTC 24 |
| Peak memory | 227060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1151708248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.1151708248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.3871916495 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 26906514 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:11 PM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871916495 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3871916495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.1517171774 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 14485814 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:11 PM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517171774 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1517171774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.410158518 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 89396234 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:14 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410158518 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.410158518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3360399334 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 547809574 ps |
| CPU time | 2.23 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:12 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360399334 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3360399334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4275248890 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 321997712 ps |
| CPU time | 6.53 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:16 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275248890 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.4275248890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.964522106 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 317272779 ps |
| CPU time | 3.06 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:13 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964522106 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.964522106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.2633587956 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 951176438 ps |
| CPU time | 5.98 seconds |
| Started | Sep 24 08:00:09 PM UTC 24 |
| Finished | Sep 24 08:00:16 PM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633587956 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.2633587956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1609359390 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 220623804 ps |
| CPU time | 4.85 seconds |
| Started | Sep 24 07:50:21 PM UTC 24 |
| Finished | Sep 24 07:50:27 PM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609359390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1609359390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_random.2947187161 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 221865116 ps |
| CPU time | 8.84 seconds |
| Started | Sep 24 07:50:10 PM UTC 24 |
| Finished | Sep 24 07:50:20 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947187161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2947187161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.4132451698 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 61644959 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 07:50:00 PM UTC 24 |
| Finished | Sep 24 07:50:04 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132451698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4132451698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.1303883503 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6081048142 ps |
| CPU time | 20.87 seconds |
| Started | Sep 24 07:50:04 PM UTC 24 |
| Finished | Sep 24 07:50:27 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303883503 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1303883503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.3847954447 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 131592438 ps |
| CPU time | 2.53 seconds |
| Started | Sep 24 07:50:22 PM UTC 24 |
| Finished | Sep 24 07:50:26 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847954447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3847954447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.3677982676 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 323059554 ps |
| CPU time | 4 seconds |
| Started | Sep 24 07:49:57 PM UTC 24 |
| Finished | Sep 24 07:50:02 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677982676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3677982676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.2049612631 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 186101846 ps |
| CPU time | 4.5 seconds |
| Started | Sep 24 07:50:16 PM UTC 24 |
| Finished | Sep 24 07:50:22 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049612631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2049612631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.2172675371 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 34857928 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 07:50:56 PM UTC 24 |
| Finished | Sep 24 07:50:58 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172675371 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2172675371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.1872741389 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 203010221 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 07:50:37 PM UTC 24 |
| Finished | Sep 24 07:50:41 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872741389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1872741389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.1802437202 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 114736498 ps |
| CPU time | 4.04 seconds |
| Started | Sep 24 07:50:41 PM UTC 24 |
| Finished | Sep 24 07:50:46 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802437202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1802437202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_random.3610822123 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 116168118 ps |
| CPU time | 7.68 seconds |
| Started | Sep 24 07:50:36 PM UTC 24 |
| Finished | Sep 24 07:50:44 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610822123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3610822123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.2996083452 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1808697786 ps |
| CPU time | 14.2 seconds |
| Started | Sep 24 07:50:55 PM UTC 24 |
| Finished | Sep 24 07:51:10 PM UTC 24 |
| Peak memory | 259332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996083452 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2996083452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.115040917 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 353649689 ps |
| CPU time | 5.64 seconds |
| Started | Sep 24 07:50:27 PM UTC 24 |
| Finished | Sep 24 07:50:34 PM UTC 24 |
| Peak memory | 217348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115040917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.115040917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.1093906014 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 94137871 ps |
| CPU time | 3.7 seconds |
| Started | Sep 24 07:50:31 PM UTC 24 |
| Finished | Sep 24 07:50:36 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093906014 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1093906014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.382371975 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 50554627 ps |
| CPU time | 4.2 seconds |
| Started | Sep 24 07:50:29 PM UTC 24 |
| Finished | Sep 24 07:50:34 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382371975 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.382371975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.862240712 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3212814563 ps |
| CPU time | 41.94 seconds |
| Started | Sep 24 07:50:35 PM UTC 24 |
| Finished | Sep 24 07:51:18 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862240712 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.862240712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3919217685 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1716345394 ps |
| CPU time | 23.41 seconds |
| Started | Sep 24 07:50:27 PM UTC 24 |
| Finished | Sep 24 07:50:52 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919217685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3919217685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3139136274 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 203204572 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 07:50:53 PM UTC 24 |
| Finished | Sep 24 07:50:59 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139136274 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3139136274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.1173620419 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1138656539 ps |
| CPU time | 14.36 seconds |
| Started | Sep 24 07:50:42 PM UTC 24 |
| Finished | Sep 24 07:50:58 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173620419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1173620419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.4186157398 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 71929733 ps |
| CPU time | 3.65 seconds |
| Started | Sep 24 07:50:50 PM UTC 24 |
| Finished | Sep 24 07:50:55 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186157398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4186157398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.584133350 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 9872045 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 07:53:40 PM UTC 24 |
| Finished | Sep 24 07:53:43 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584133350 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.584133350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.4232898421 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 555442240 ps |
| CPU time | 46.15 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:54:27 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232898421 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4232898421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.1721740188 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 64293068 ps |
| CPU time | 3.16 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:43 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721740188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1721740188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.3693343555 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 478672407 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:45 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693343555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3693343555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_random.368139202 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 343649836 ps |
| CPU time | 6.4 seconds |
| Started | Sep 24 07:53:33 PM UTC 24 |
| Finished | Sep 24 07:53:41 PM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368139202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.368139202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.1742521006 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 142232776 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:35 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742521006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1742521006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.241510610 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 178056597 ps |
| CPU time | 6.87 seconds |
| Started | Sep 24 07:53:31 PM UTC 24 |
| Finished | Sep 24 07:53:39 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241510610 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.241510610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.2195432413 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3897825491 ps |
| CPU time | 41.53 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:54:12 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195432413 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2195432413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.3324424009 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 666506950 ps |
| CPU time | 7.94 seconds |
| Started | Sep 24 07:53:32 PM UTC 24 |
| Finished | Sep 24 07:53:41 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324424009 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3324424009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.922089840 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 55702570 ps |
| CPU time | 3.66 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:44 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922089840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.922089840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1054414885 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 232802697 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:34 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054414885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1054414885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.2307922296 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 116649953 ps |
| CPU time | 9.3 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:50 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307922296 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2307922296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.2744218228 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 191024012 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 07:53:39 PM UTC 24 |
| Finished | Sep 24 07:53:44 PM UTC 24 |
| Peak memory | 217312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744218228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2744218228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.3152058485 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 14952409 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 07:53:52 PM UTC 24 |
| Finished | Sep 24 07:53:54 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152058485 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3152058485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.1785745949 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 534408776 ps |
| CPU time | 8.87 seconds |
| Started | Sep 24 07:53:45 PM UTC 24 |
| Finished | Sep 24 07:53:55 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785745949 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1785745949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.4119362818 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 224122444 ps |
| CPU time | 5.53 seconds |
| Started | Sep 24 07:53:49 PM UTC 24 |
| Finished | Sep 24 07:53:56 PM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119362818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4119362818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.370606707 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 177869054 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 07:53:46 PM UTC 24 |
| Finished | Sep 24 07:53:51 PM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370606707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.370606707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.2043825383 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 124060641 ps |
| CPU time | 4.83 seconds |
| Started | Sep 24 07:53:47 PM UTC 24 |
| Finished | Sep 24 07:53:53 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043825383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2043825383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.1579184211 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 250560523 ps |
| CPU time | 3.69 seconds |
| Started | Sep 24 07:53:46 PM UTC 24 |
| Finished | Sep 24 07:53:51 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579184211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1579184211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_random.1207918957 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 537817163 ps |
| CPU time | 7.73 seconds |
| Started | Sep 24 07:53:45 PM UTC 24 |
| Finished | Sep 24 07:53:54 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207918957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1207918957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.3783348088 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 95883584 ps |
| CPU time | 5.56 seconds |
| Started | Sep 24 07:53:42 PM UTC 24 |
| Finished | Sep 24 07:53:48 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783348088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3783348088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.2696591454 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 729486896 ps |
| CPU time | 6.67 seconds |
| Started | Sep 24 07:53:44 PM UTC 24 |
| Finished | Sep 24 07:53:52 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696591454 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2696591454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.2103445150 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 170384924 ps |
| CPU time | 7.11 seconds |
| Started | Sep 24 07:53:43 PM UTC 24 |
| Finished | Sep 24 07:53:51 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103445150 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2103445150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.3382649131 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 146681539 ps |
| CPU time | 3.57 seconds |
| Started | Sep 24 07:53:50 PM UTC 24 |
| Finished | Sep 24 07:53:55 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382649131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3382649131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.3958707217 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 182324688 ps |
| CPU time | 3.78 seconds |
| Started | Sep 24 07:53:41 PM UTC 24 |
| Finished | Sep 24 07:53:46 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958707217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3958707217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.1978540496 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 179864204 ps |
| CPU time | 6.96 seconds |
| Started | Sep 24 07:53:46 PM UTC 24 |
| Finished | Sep 24 07:53:54 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978540496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1978540496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.3526983075 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 101887330 ps |
| CPU time | 3.45 seconds |
| Started | Sep 24 07:53:52 PM UTC 24 |
| Finished | Sep 24 07:53:56 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526983075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3526983075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.2798460205 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 25188485 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 07:54:01 PM UTC 24 |
| Finished | Sep 24 07:54:04 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798460205 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2798460205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.3942375635 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 128823331 ps |
| CPU time | 3.75 seconds |
| Started | Sep 24 07:53:55 PM UTC 24 |
| Finished | Sep 24 07:54:00 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942375635 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3942375635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.2254955370 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 280112234 ps |
| CPU time | 4.65 seconds |
| Started | Sep 24 07:53:59 PM UTC 24 |
| Finished | Sep 24 07:54:05 PM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254955370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2254955370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.2636946829 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 188536561 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 07:53:56 PM UTC 24 |
| Finished | Sep 24 07:54:00 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636946829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2636946829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.483079486 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 52297570 ps |
| CPU time | 3.83 seconds |
| Started | Sep 24 07:53:58 PM UTC 24 |
| Finished | Sep 24 07:54:03 PM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483079486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.483079486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.1767467105 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 89229324 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 07:53:58 PM UTC 24 |
| Finished | Sep 24 07:54:01 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767467105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1767467105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.2321200752 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 151686249 ps |
| CPU time | 4.06 seconds |
| Started | Sep 24 07:53:56 PM UTC 24 |
| Finished | Sep 24 07:54:02 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321200752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2321200752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_random.727366375 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 66730486 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 07:53:55 PM UTC 24 |
| Finished | Sep 24 07:54:00 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727366375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.727366375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.361219746 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 55928495 ps |
| CPU time | 3.92 seconds |
| Started | Sep 24 07:53:54 PM UTC 24 |
| Finished | Sep 24 07:53:59 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361219746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.361219746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.3773033755 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 373144854 ps |
| CPU time | 3.96 seconds |
| Started | Sep 24 07:53:55 PM UTC 24 |
| Finished | Sep 24 07:54:00 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773033755 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3773033755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.2481529247 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 774026886 ps |
| CPU time | 25.3 seconds |
| Started | Sep 24 07:53:54 PM UTC 24 |
| Finished | Sep 24 07:54:21 PM UTC 24 |
| Peak memory | 217348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481529247 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2481529247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.3103205055 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 38655947 ps |
| CPU time | 3.02 seconds |
| Started | Sep 24 07:53:55 PM UTC 24 |
| Finished | Sep 24 07:53:59 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103205055 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3103205055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.3045388881 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 30293082 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 07:54:00 PM UTC 24 |
| Finished | Sep 24 07:54:04 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045388881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3045388881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.462804093 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 70956923 ps |
| CPU time | 4.4 seconds |
| Started | Sep 24 07:53:53 PM UTC 24 |
| Finished | Sep 24 07:53:59 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462804093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.462804093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.3549450142 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 164186045 ps |
| CPU time | 9.36 seconds |
| Started | Sep 24 07:54:01 PM UTC 24 |
| Finished | Sep 24 07:54:12 PM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3549450142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg r_stress_all_with_rand_reset.3549450142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.3470663190 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 738794599 ps |
| CPU time | 23.69 seconds |
| Started | Sep 24 07:53:58 PM UTC 24 |
| Finished | Sep 24 07:54:23 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470663190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3470663190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.2764709236 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 95876689 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 07:54:00 PM UTC 24 |
| Finished | Sep 24 07:54:05 PM UTC 24 |
| Peak memory | 219572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764709236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2764709236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.3051397431 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 45504170 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 07:54:13 PM UTC 24 |
| Finished | Sep 24 07:54:15 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051397431 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3051397431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.948638073 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 141394590 ps |
| CPU time | 3.76 seconds |
| Started | Sep 24 07:54:04 PM UTC 24 |
| Finished | Sep 24 07:54:09 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948638073 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.948638073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.2738306300 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 27392333 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 07:54:05 PM UTC 24 |
| Finished | Sep 24 07:54:09 PM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738306300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2738306300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.4212923483 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 120376002 ps |
| CPU time | 5.36 seconds |
| Started | Sep 24 07:54:06 PM UTC 24 |
| Finished | Sep 24 07:54:13 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212923483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4212923483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.2299232160 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1284600230 ps |
| CPU time | 5.98 seconds |
| Started | Sep 24 07:54:06 PM UTC 24 |
| Finished | Sep 24 07:54:13 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299232160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2299232160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.4290147319 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 81641565 ps |
| CPU time | 6.02 seconds |
| Started | Sep 24 07:54:05 PM UTC 24 |
| Finished | Sep 24 07:54:12 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290147319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4290147319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_random.3429521469 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 596776789 ps |
| CPU time | 12.59 seconds |
| Started | Sep 24 07:54:03 PM UTC 24 |
| Finished | Sep 24 07:54:16 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429521469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3429521469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.2908870305 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 29833875 ps |
| CPU time | 3.25 seconds |
| Started | Sep 24 07:54:01 PM UTC 24 |
| Finished | Sep 24 07:54:06 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908870305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2908870305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.3385052183 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1914895914 ps |
| CPU time | 7.94 seconds |
| Started | Sep 24 07:54:03 PM UTC 24 |
| Finished | Sep 24 07:54:12 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385052183 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3385052183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.3230767203 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 67833988 ps |
| CPU time | 3.7 seconds |
| Started | Sep 24 07:54:03 PM UTC 24 |
| Finished | Sep 24 07:54:07 PM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230767203 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3230767203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.1125555350 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 153621806 ps |
| CPU time | 5.66 seconds |
| Started | Sep 24 07:54:08 PM UTC 24 |
| Finished | Sep 24 07:54:15 PM UTC 24 |
| Peak memory | 219468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125555350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1125555350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.2493789194 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2921354782 ps |
| CPU time | 18.73 seconds |
| Started | Sep 24 07:54:01 PM UTC 24 |
| Finished | Sep 24 07:54:21 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493789194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2493789194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.2546720642 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3224794746 ps |
| CPU time | 33.88 seconds |
| Started | Sep 24 07:54:09 PM UTC 24 |
| Finished | Sep 24 07:54:45 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546720642 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2546720642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.271466991 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 160012074 ps |
| CPU time | 10.44 seconds |
| Started | Sep 24 07:54:13 PM UTC 24 |
| Finished | Sep 24 07:54:24 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=271466991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr _stress_all_with_rand_reset.271466991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.3159532780 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 125414513 ps |
| CPU time | 8.45 seconds |
| Started | Sep 24 07:54:06 PM UTC 24 |
| Finished | Sep 24 07:54:16 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159532780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3159532780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.3116670185 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 252258416 ps |
| CPU time | 2.73 seconds |
| Started | Sep 24 07:54:09 PM UTC 24 |
| Finished | Sep 24 07:54:13 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116670185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3116670185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.99832728 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 53316959 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 07:54:23 PM UTC 24 |
| Finished | Sep 24 07:54:25 PM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99832728 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.99832728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2220129751 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 40736823 ps |
| CPU time | 4.61 seconds |
| Started | Sep 24 07:54:16 PM UTC 24 |
| Finished | Sep 24 07:54:22 PM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220129751 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2220129751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.947489508 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 60279248 ps |
| CPU time | 4.02 seconds |
| Started | Sep 24 07:54:16 PM UTC 24 |
| Finished | Sep 24 07:54:21 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947489508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.947489508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.459568269 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 24039744 ps |
| CPU time | 2.59 seconds |
| Started | Sep 24 07:54:20 PM UTC 24 |
| Finished | Sep 24 07:54:24 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459568269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.459568269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.3497760444 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 357723127 ps |
| CPU time | 4.71 seconds |
| Started | Sep 24 07:54:17 PM UTC 24 |
| Finished | Sep 24 07:54:23 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497760444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3497760444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_random.1084832347 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 259743364 ps |
| CPU time | 6.41 seconds |
| Started | Sep 24 07:54:16 PM UTC 24 |
| Finished | Sep 24 07:54:24 PM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084832347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1084832347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.3634613501 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 385307512 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 07:54:13 PM UTC 24 |
| Finished | Sep 24 07:54:19 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634613501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3634613501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.4036855410 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 77822108 ps |
| CPU time | 5.05 seconds |
| Started | Sep 24 07:54:14 PM UTC 24 |
| Finished | Sep 24 07:54:20 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036855410 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4036855410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.87195853 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 82001118 ps |
| CPU time | 4.51 seconds |
| Started | Sep 24 07:54:14 PM UTC 24 |
| Finished | Sep 24 07:54:20 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87195853 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.87195853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.1593841238 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 89494934 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 07:54:22 PM UTC 24 |
| Finished | Sep 24 07:54:25 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593841238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1593841238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.3302799530 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 724611348 ps |
| CPU time | 7.05 seconds |
| Started | Sep 24 07:54:13 PM UTC 24 |
| Finished | Sep 24 07:54:21 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302799530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3302799530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.865741447 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4501699379 ps |
| CPU time | 28.71 seconds |
| Started | Sep 24 07:54:22 PM UTC 24 |
| Finished | Sep 24 07:54:52 PM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865741447 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.865741447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.2433738559 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 533022346 ps |
| CPU time | 5.08 seconds |
| Started | Sep 24 07:54:17 PM UTC 24 |
| Finished | Sep 24 07:54:23 PM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433738559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2433738559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.1708352714 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 35090217 ps |
| CPU time | 2.27 seconds |
| Started | Sep 24 07:54:22 PM UTC 24 |
| Finished | Sep 24 07:54:25 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708352714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1708352714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.104693555 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 44961045 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 07:54:35 PM UTC 24 |
| Finished | Sep 24 07:54:37 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104693555 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.104693555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.1618902827 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 40859228 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:36 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618902827 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1618902827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.221752347 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1755558218 ps |
| CPU time | 13.35 seconds |
| Started | Sep 24 07:54:31 PM UTC 24 |
| Finished | Sep 24 07:54:45 PM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221752347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.221752347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.1893642374 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 134221713 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:34 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893642374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1893642374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.183186598 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4261024965 ps |
| CPU time | 35.24 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:55:07 PM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183186598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.183186598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3494932646 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 297408512 ps |
| CPU time | 8.62 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:40 PM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494932646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3494932646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.2419046665 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 92774823 ps |
| CPU time | 5.53 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:37 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419046665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2419046665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_random.2904003238 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 131730830 ps |
| CPU time | 4.16 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:36 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904003238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2904003238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.2593363563 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 359677831 ps |
| CPU time | 7.51 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:39 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593363563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2593363563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.2208724877 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 375476615 ps |
| CPU time | 6.51 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:38 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208724877 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2208724877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.2426681395 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 147369211 ps |
| CPU time | 5.48 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:37 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426681395 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2426681395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.3084198971 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 63038839 ps |
| CPU time | 2.47 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:34 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084198971 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3084198971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2835937816 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 66841797 ps |
| CPU time | 2.78 seconds |
| Started | Sep 24 07:54:31 PM UTC 24 |
| Finished | Sep 24 07:54:35 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835937816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2835937816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.2245591070 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 830997614 ps |
| CPU time | 15.82 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:47 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245591070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2245591070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.993262475 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 967856808 ps |
| CPU time | 44.87 seconds |
| Started | Sep 24 07:54:32 PM UTC 24 |
| Finished | Sep 24 07:55:18 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993262475 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.993262475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.3072249060 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5789427129 ps |
| CPU time | 30.87 seconds |
| Started | Sep 24 07:54:35 PM UTC 24 |
| Finished | Sep 24 07:55:07 PM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3072249060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg r_stress_all_with_rand_reset.3072249060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.842095959 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 227161356 ps |
| CPU time | 8.77 seconds |
| Started | Sep 24 07:54:30 PM UTC 24 |
| Finished | Sep 24 07:54:41 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842095959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.842095959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3186553181 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 89213991 ps |
| CPU time | 2.69 seconds |
| Started | Sep 24 07:54:31 PM UTC 24 |
| Finished | Sep 24 07:54:34 PM UTC 24 |
| Peak memory | 217304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186553181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3186553181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.2134219844 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 14523158 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 07:54:46 PM UTC 24 |
| Finished | Sep 24 07:54:48 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134219844 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2134219844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.535231709 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 75635748 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 07:54:39 PM UTC 24 |
| Finished | Sep 24 07:54:44 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535231709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.535231709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.2456848908 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 91913602 ps |
| CPU time | 2.83 seconds |
| Started | Sep 24 07:54:42 PM UTC 24 |
| Finished | Sep 24 07:54:46 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456848908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2456848908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.1450446625 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 376485932 ps |
| CPU time | 13.22 seconds |
| Started | Sep 24 07:54:42 PM UTC 24 |
| Finished | Sep 24 07:54:56 PM UTC 24 |
| Peak memory | 231224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450446625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1450446625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.922490502 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 95841490 ps |
| CPU time | 3.75 seconds |
| Started | Sep 24 07:54:40 PM UTC 24 |
| Finished | Sep 24 07:54:44 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922490502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.922490502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_random.917756877 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 27915157 ps |
| CPU time | 3.22 seconds |
| Started | Sep 24 07:54:38 PM UTC 24 |
| Finished | Sep 24 07:54:43 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917756877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.917756877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.3745039194 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 39060612 ps |
| CPU time | 3.49 seconds |
| Started | Sep 24 07:54:36 PM UTC 24 |
| Finished | Sep 24 07:54:41 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745039194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3745039194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.3778286377 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 131519516 ps |
| CPU time | 4.35 seconds |
| Started | Sep 24 07:54:36 PM UTC 24 |
| Finished | Sep 24 07:54:42 PM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778286377 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3778286377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.2072415970 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 453991934 ps |
| CPU time | 8.31 seconds |
| Started | Sep 24 07:54:36 PM UTC 24 |
| Finished | Sep 24 07:54:46 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072415970 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2072415970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3602212233 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 194549884 ps |
| CPU time | 6.35 seconds |
| Started | Sep 24 07:54:38 PM UTC 24 |
| Finished | Sep 24 07:54:46 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602212233 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3602212233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.1255953140 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 149082228 ps |
| CPU time | 3.04 seconds |
| Started | Sep 24 07:54:43 PM UTC 24 |
| Finished | Sep 24 07:54:47 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255953140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1255953140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.2619112839 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 381404899 ps |
| CPU time | 7.65 seconds |
| Started | Sep 24 07:54:35 PM UTC 24 |
| Finished | Sep 24 07:54:44 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619112839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2619112839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.3123256596 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 935847798 ps |
| CPU time | 9.77 seconds |
| Started | Sep 24 07:54:42 PM UTC 24 |
| Finished | Sep 24 07:54:52 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123256596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3123256596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.834443636 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 68795392 ps |
| CPU time | 3.91 seconds |
| Started | Sep 24 07:54:45 PM UTC 24 |
| Finished | Sep 24 07:54:50 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834443636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.834443636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2796480824 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 25797876 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:55:05 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796480824 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2796480824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.1174626628 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 32486628 ps |
| CPU time | 3.81 seconds |
| Started | Sep 24 07:54:48 PM UTC 24 |
| Finished | Sep 24 07:54:53 PM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174626628 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1174626628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.3117754804 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 62665852 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 07:54:49 PM UTC 24 |
| Finished | Sep 24 07:54:53 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117754804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3117754804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.1543852447 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 38062115 ps |
| CPU time | 2.5 seconds |
| Started | Sep 24 07:55:01 PM UTC 24 |
| Finished | Sep 24 07:55:06 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543852447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1543852447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.1888313556 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 60785203 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 07:55:01 PM UTC 24 |
| Finished | Sep 24 07:55:06 PM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888313556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1888313556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.951788313 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 307637199 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 07:54:57 PM UTC 24 |
| Finished | Sep 24 07:55:02 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951788313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.951788313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_random.2948156445 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 877916858 ps |
| CPU time | 11.77 seconds |
| Started | Sep 24 07:54:48 PM UTC 24 |
| Finished | Sep 24 07:55:01 PM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948156445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2948156445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.3974350869 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 122027948 ps |
| CPU time | 5.79 seconds |
| Started | Sep 24 07:54:46 PM UTC 24 |
| Finished | Sep 24 07:54:53 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974350869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3974350869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.117207036 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 136326290 ps |
| CPU time | 4.07 seconds |
| Started | Sep 24 07:54:47 PM UTC 24 |
| Finished | Sep 24 07:54:52 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117207036 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.117207036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.145772259 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 148381748 ps |
| CPU time | 6.45 seconds |
| Started | Sep 24 07:54:46 PM UTC 24 |
| Finished | Sep 24 07:54:54 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145772259 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.145772259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.1333737544 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 156813991 ps |
| CPU time | 4.31 seconds |
| Started | Sep 24 07:54:47 PM UTC 24 |
| Finished | Sep 24 07:54:52 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333737544 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1333737544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.871241210 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 103994018 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 07:55:01 PM UTC 24 |
| Finished | Sep 24 07:55:07 PM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871241210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.871241210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.403407531 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 183051055 ps |
| CPU time | 7.96 seconds |
| Started | Sep 24 07:54:46 PM UTC 24 |
| Finished | Sep 24 07:54:55 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403407531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.403407531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.2788781367 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 69878565 ps |
| CPU time | 4.34 seconds |
| Started | Sep 24 07:55:01 PM UTC 24 |
| Finished | Sep 24 07:55:07 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788781367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2788781367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.3913839793 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 322335348 ps |
| CPU time | 4.85 seconds |
| Started | Sep 24 07:55:01 PM UTC 24 |
| Finished | Sep 24 07:55:08 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913839793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3913839793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.3819531423 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 47320434 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:15 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819531423 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3819531423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.283245390 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 40954706 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:16 PM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283245390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.283245390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.4057024029 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1798399523 ps |
| CPU time | 18.42 seconds |
| Started | Sep 24 07:55:10 PM UTC 24 |
| Finished | Sep 24 07:55:30 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057024029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4057024029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.276839605 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 182098092 ps |
| CPU time | 6.19 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 223352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276839605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.276839605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.2356023277 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 62022863 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:16 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356023277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2356023277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_random.2378934462 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 428711055 ps |
| CPU time | 7.56 seconds |
| Started | Sep 24 07:55:10 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378934462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2378934462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.1623689396 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 131545121 ps |
| CPU time | 5.43 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:55:09 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623689396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1623689396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.2713141867 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5235802566 ps |
| CPU time | 54.52 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:55:59 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713141867 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2713141867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.3433189418 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1003344932 ps |
| CPU time | 23.58 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:55:28 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433189418 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3433189418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.1169108003 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 106840264 ps |
| CPU time | 5.53 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:55:09 PM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169108003 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1169108003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.4133736757 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 182567819 ps |
| CPU time | 5.91 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133736757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4133736757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.270284520 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 130597194 ps |
| CPU time | 5.19 seconds |
| Started | Sep 24 07:55:02 PM UTC 24 |
| Finished | Sep 24 07:55:09 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270284520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.270284520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.1196733487 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 9657180614 ps |
| CPU time | 35.14 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:49 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196733487 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1196733487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.3700373014 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 585285075 ps |
| CPU time | 8.09 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:21 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700373014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3700373014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.2957807606 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 103483845 ps |
| CPU time | 3.86 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:17 PM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957807606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2957807606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.462529025 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 18033099 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:23 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462529025 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.462529025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.598222240 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 31650313 ps |
| CPU time | 3.07 seconds |
| Started | Sep 24 07:55:17 PM UTC 24 |
| Finished | Sep 24 07:55:21 PM UTC 24 |
| Peak memory | 223800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598222240 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.598222240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.3035983573 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1279219145 ps |
| CPU time | 5.61 seconds |
| Started | Sep 24 07:55:18 PM UTC 24 |
| Finished | Sep 24 07:55:24 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035983573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3035983573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.2786859878 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 388987595 ps |
| CPU time | 5.93 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:27 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786859878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2786859878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.4070448303 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1888530455 ps |
| CPU time | 5.72 seconds |
| Started | Sep 24 07:55:19 PM UTC 24 |
| Finished | Sep 24 07:55:26 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070448303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4070448303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_random.4180148185 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 618661262 ps |
| CPU time | 9.5 seconds |
| Started | Sep 24 07:55:17 PM UTC 24 |
| Finished | Sep 24 07:55:27 PM UTC 24 |
| Peak memory | 223812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180148185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4180148185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.4259209871 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1098437146 ps |
| CPU time | 13.7 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:27 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259209871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4259209871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.42209006 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 65873139 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 07:55:15 PM UTC 24 |
| Finished | Sep 24 07:55:21 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42209006 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.42209006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.3251376108 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1006566259 ps |
| CPU time | 4.7 seconds |
| Started | Sep 24 07:55:13 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251376108 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3251376108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.1352721368 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 113808115 ps |
| CPU time | 2.51 seconds |
| Started | Sep 24 07:55:15 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352721368 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1352721368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.219340557 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 533641618 ps |
| CPU time | 16.15 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:38 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219340557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.219340557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.1935880178 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 144147316 ps |
| CPU time | 5.8 seconds |
| Started | Sep 24 07:55:12 PM UTC 24 |
| Finished | Sep 24 07:55:19 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935880178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1935880178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.3598388567 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 255868111 ps |
| CPU time | 14.48 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:36 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3598388567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymg r_stress_all_with_rand_reset.3598388567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.2269843292 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 788994288 ps |
| CPU time | 5.96 seconds |
| Started | Sep 24 07:55:19 PM UTC 24 |
| Finished | Sep 24 07:55:26 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269843292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2269843292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.720448985 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 36779268 ps |
| CPU time | 2.82 seconds |
| Started | Sep 24 07:55:20 PM UTC 24 |
| Finished | Sep 24 07:55:25 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720448985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.720448985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1982630980 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 11016348 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 07:51:17 PM UTC 24 |
| Finished | Sep 24 07:51:19 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982630980 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1982630980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.821828140 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 65607848 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 07:51:06 PM UTC 24 |
| Finished | Sep 24 07:51:12 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821828140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.821828140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.2051414915 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 316946847 ps |
| CPU time | 7.81 seconds |
| Started | Sep 24 07:51:10 PM UTC 24 |
| Finished | Sep 24 07:51:18 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051414915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2051414915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.2079731680 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 82676453 ps |
| CPU time | 2.68 seconds |
| Started | Sep 24 07:51:10 PM UTC 24 |
| Finished | Sep 24 07:51:13 PM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079731680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2079731680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.2228300172 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 79835213 ps |
| CPU time | 4.45 seconds |
| Started | Sep 24 07:51:06 PM UTC 24 |
| Finished | Sep 24 07:51:12 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228300172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2228300172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.3254713872 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 171882707 ps |
| CPU time | 4.55 seconds |
| Started | Sep 24 07:50:59 PM UTC 24 |
| Finished | Sep 24 07:51:04 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254713872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3254713872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.2361135530 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 218810805 ps |
| CPU time | 8.98 seconds |
| Started | Sep 24 07:50:59 PM UTC 24 |
| Finished | Sep 24 07:51:09 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361135530 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2361135530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.3455807480 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 133324515 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 07:50:59 PM UTC 24 |
| Finished | Sep 24 07:51:03 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455807480 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3455807480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.3986458194 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 910239598 ps |
| CPU time | 24.32 seconds |
| Started | Sep 24 07:51:00 PM UTC 24 |
| Finished | Sep 24 07:51:26 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986458194 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3986458194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.766905385 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 126501238 ps |
| CPU time | 4.81 seconds |
| Started | Sep 24 07:51:13 PM UTC 24 |
| Finished | Sep 24 07:51:19 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766905385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.766905385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.3585807891 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 641151417 ps |
| CPU time | 19.36 seconds |
| Started | Sep 24 07:50:56 PM UTC 24 |
| Finished | Sep 24 07:51:17 PM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585807891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3585807891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.2662486618 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 223669851 ps |
| CPU time | 6.95 seconds |
| Started | Sep 24 07:51:06 PM UTC 24 |
| Finished | Sep 24 07:51:15 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662486618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2662486618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.2289597225 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 80537957 ps |
| CPU time | 2.59 seconds |
| Started | Sep 24 07:51:13 PM UTC 24 |
| Finished | Sep 24 07:51:17 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289597225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2289597225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.4078880663 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 26424797 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 07:55:30 PM UTC 24 |
| Finished | Sep 24 07:55:33 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078880663 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4078880663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.3258024227 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 274792376 ps |
| CPU time | 8.78 seconds |
| Started | Sep 24 07:55:25 PM UTC 24 |
| Finished | Sep 24 07:55:35 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258024227 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3258024227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.1297380787 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 48918775 ps |
| CPU time | 2.56 seconds |
| Started | Sep 24 07:55:29 PM UTC 24 |
| Finished | Sep 24 07:55:32 PM UTC 24 |
| Peak memory | 228104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297380787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1297380787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.4236504634 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 102103621 ps |
| CPU time | 3.72 seconds |
| Started | Sep 24 07:55:25 PM UTC 24 |
| Finished | Sep 24 07:55:30 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236504634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4236504634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.492193124 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 280629687 ps |
| CPU time | 4.34 seconds |
| Started | Sep 24 07:55:28 PM UTC 24 |
| Finished | Sep 24 07:55:33 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492193124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.492193124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.4147831443 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 70017329 ps |
| CPU time | 3.37 seconds |
| Started | Sep 24 07:55:29 PM UTC 24 |
| Finished | Sep 24 07:55:33 PM UTC 24 |
| Peak memory | 223552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147831443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.4147831443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.2118089820 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 346063318 ps |
| CPU time | 5.14 seconds |
| Started | Sep 24 07:55:26 PM UTC 24 |
| Finished | Sep 24 07:55:33 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118089820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2118089820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_random.2527060783 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 98799547 ps |
| CPU time | 4.3 seconds |
| Started | Sep 24 07:55:25 PM UTC 24 |
| Finished | Sep 24 07:55:31 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527060783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2527060783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.2195249687 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 81035294 ps |
| CPU time | 3 seconds |
| Started | Sep 24 07:55:24 PM UTC 24 |
| Finished | Sep 24 07:55:28 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195249687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2195249687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.1328873617 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 107665041 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 07:55:24 PM UTC 24 |
| Finished | Sep 24 07:55:29 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328873617 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1328873617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.2790835375 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 181987435 ps |
| CPU time | 6.77 seconds |
| Started | Sep 24 07:55:24 PM UTC 24 |
| Finished | Sep 24 07:55:32 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790835375 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2790835375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.167807984 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 130120875 ps |
| CPU time | 3.59 seconds |
| Started | Sep 24 07:55:24 PM UTC 24 |
| Finished | Sep 24 07:55:29 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167807984 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.167807984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.2380301608 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 127386360 ps |
| CPU time | 5.94 seconds |
| Started | Sep 24 07:55:29 PM UTC 24 |
| Finished | Sep 24 07:55:36 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380301608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2380301608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.2408423613 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 835940769 ps |
| CPU time | 15.91 seconds |
| Started | Sep 24 07:55:24 PM UTC 24 |
| Finished | Sep 24 07:55:41 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408423613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2408423613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.3015476882 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 329746594 ps |
| CPU time | 5.96 seconds |
| Started | Sep 24 07:55:26 PM UTC 24 |
| Finished | Sep 24 07:55:33 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015476882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3015476882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.103509720 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1221451404 ps |
| CPU time | 8.02 seconds |
| Started | Sep 24 07:55:29 PM UTC 24 |
| Finished | Sep 24 07:55:38 PM UTC 24 |
| Peak memory | 219648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103509720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.103509720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.4294958544 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 15127207 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 07:55:40 PM UTC 24 |
| Finished | Sep 24 07:55:42 PM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294958544 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4294958544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.3606307356 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3094779427 ps |
| CPU time | 42.18 seconds |
| Started | Sep 24 07:55:34 PM UTC 24 |
| Finished | Sep 24 07:56:17 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606307356 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3606307356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.2656238992 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 777604189 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 07:55:37 PM UTC 24 |
| Finished | Sep 24 07:55:43 PM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656238992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2656238992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.4170509826 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 239588163 ps |
| CPU time | 4.22 seconds |
| Started | Sep 24 07:55:34 PM UTC 24 |
| Finished | Sep 24 07:55:39 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170509826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4170509826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.3478577218 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4404387194 ps |
| CPU time | 41.32 seconds |
| Started | Sep 24 07:55:36 PM UTC 24 |
| Finished | Sep 24 07:56:19 PM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478577218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3478577218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.851182769 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1864413800 ps |
| CPU time | 8.61 seconds |
| Started | Sep 24 07:55:35 PM UTC 24 |
| Finished | Sep 24 07:55:45 PM UTC 24 |
| Peak memory | 231556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851182769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.851182769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_random.2260766303 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3447018228 ps |
| CPU time | 28.58 seconds |
| Started | Sep 24 07:55:34 PM UTC 24 |
| Finished | Sep 24 07:56:04 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260766303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2260766303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.371562255 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 246612609 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 07:55:31 PM UTC 24 |
| Finished | Sep 24 07:55:36 PM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371562255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.371562255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.2887081918 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 361361215 ps |
| CPU time | 6.54 seconds |
| Started | Sep 24 07:55:32 PM UTC 24 |
| Finished | Sep 24 07:55:40 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887081918 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2887081918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.389302655 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 25906295 ps |
| CPU time | 2.92 seconds |
| Started | Sep 24 07:55:31 PM UTC 24 |
| Finished | Sep 24 07:55:35 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389302655 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.389302655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.435112967 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 178414779 ps |
| CPU time | 9.9 seconds |
| Started | Sep 24 07:55:34 PM UTC 24 |
| Finished | Sep 24 07:55:45 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435112967 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.435112967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.4104588834 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 427370724 ps |
| CPU time | 4.72 seconds |
| Started | Sep 24 07:55:37 PM UTC 24 |
| Finished | Sep 24 07:55:43 PM UTC 24 |
| Peak memory | 217284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104588834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4104588834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.1169043686 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 270110140 ps |
| CPU time | 4.74 seconds |
| Started | Sep 24 07:55:31 PM UTC 24 |
| Finished | Sep 24 07:55:37 PM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169043686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1169043686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.2390481156 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 76724132022 ps |
| CPU time | 468.76 seconds |
| Started | Sep 24 07:55:38 PM UTC 24 |
| Finished | Sep 24 08:03:34 PM UTC 24 |
| Peak memory | 231084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390481156 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2390481156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.2895261238 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2878622125 ps |
| CPU time | 31.58 seconds |
| Started | Sep 24 07:55:35 PM UTC 24 |
| Finished | Sep 24 07:56:08 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895261238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2895261238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.2864963963 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 47441037 ps |
| CPU time | 3.7 seconds |
| Started | Sep 24 07:55:37 PM UTC 24 |
| Finished | Sep 24 07:55:42 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864963963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2864963963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.3286315429 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 42335736 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 07:55:53 PM UTC 24 |
| Finished | Sep 24 07:55:55 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286315429 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3286315429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.4035405530 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 804095797 ps |
| CPU time | 7.31 seconds |
| Started | Sep 24 07:55:50 PM UTC 24 |
| Finished | Sep 24 07:55:58 PM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035405530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4035405530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.1844618910 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 263392927 ps |
| CPU time | 11.43 seconds |
| Started | Sep 24 07:55:44 PM UTC 24 |
| Finished | Sep 24 07:55:57 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844618910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1844618910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.54970003 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1177823436 ps |
| CPU time | 14.38 seconds |
| Started | Sep 24 07:55:46 PM UTC 24 |
| Finished | Sep 24 07:56:02 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54970003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.54970003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.1162242037 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 213254537 ps |
| CPU time | 4.21 seconds |
| Started | Sep 24 07:55:48 PM UTC 24 |
| Finished | Sep 24 07:55:54 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162242037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1162242037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.3769114847 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 784245063 ps |
| CPU time | 5.71 seconds |
| Started | Sep 24 07:55:45 PM UTC 24 |
| Finished | Sep 24 07:55:52 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769114847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3769114847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_random.1495569419 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 114861387 ps |
| CPU time | 6.13 seconds |
| Started | Sep 24 07:55:43 PM UTC 24 |
| Finished | Sep 24 07:55:50 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495569419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1495569419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.43818007 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1357308145 ps |
| CPU time | 12.55 seconds |
| Started | Sep 24 07:55:41 PM UTC 24 |
| Finished | Sep 24 07:55:54 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43818007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.43818007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.2322125495 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 143409729 ps |
| CPU time | 6.29 seconds |
| Started | Sep 24 07:55:42 PM UTC 24 |
| Finished | Sep 24 07:55:49 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322125495 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2322125495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.869274338 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1158732047 ps |
| CPU time | 5.8 seconds |
| Started | Sep 24 07:55:41 PM UTC 24 |
| Finished | Sep 24 07:55:48 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869274338 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.869274338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.2033041954 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 3443598351 ps |
| CPU time | 43 seconds |
| Started | Sep 24 07:55:43 PM UTC 24 |
| Finished | Sep 24 07:56:27 PM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033041954 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2033041954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.2853958134 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 207372529 ps |
| CPU time | 9.01 seconds |
| Started | Sep 24 07:55:50 PM UTC 24 |
| Finished | Sep 24 07:56:00 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853958134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2853958134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.1420456720 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 144529274 ps |
| CPU time | 4.69 seconds |
| Started | Sep 24 07:55:40 PM UTC 24 |
| Finished | Sep 24 07:55:45 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420456720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1420456720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.3583255460 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2713364251 ps |
| CPU time | 25.03 seconds |
| Started | Sep 24 07:55:51 PM UTC 24 |
| Finished | Sep 24 07:56:17 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583255460 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3583255460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all_with_rand_reset.223275303 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 174840616 ps |
| CPU time | 6.9 seconds |
| Started | Sep 24 07:55:53 PM UTC 24 |
| Finished | Sep 24 07:56:01 PM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=223275303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr _stress_all_with_rand_reset.223275303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.2460220032 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 131694410 ps |
| CPU time | 8.92 seconds |
| Started | Sep 24 07:55:45 PM UTC 24 |
| Finished | Sep 24 07:55:55 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460220032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2460220032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.3071277450 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 23279463 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 07:56:05 PM UTC 24 |
| Finished | Sep 24 07:56:08 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071277450 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3071277450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.1089337761 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 922792975 ps |
| CPU time | 54.35 seconds |
| Started | Sep 24 07:55:57 PM UTC 24 |
| Finished | Sep 24 07:56:53 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089337761 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1089337761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.4207905034 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 576716452 ps |
| CPU time | 16.18 seconds |
| Started | Sep 24 07:55:59 PM UTC 24 |
| Finished | Sep 24 07:56:16 PM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207905034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4207905034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.2638071545 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 158784459 ps |
| CPU time | 5.26 seconds |
| Started | Sep 24 07:56:01 PM UTC 24 |
| Finished | Sep 24 07:56:07 PM UTC 24 |
| Peak memory | 231496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638071545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2638071545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.3500193003 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 212444568 ps |
| CPU time | 5.66 seconds |
| Started | Sep 24 07:56:01 PM UTC 24 |
| Finished | Sep 24 07:56:08 PM UTC 24 |
| Peak memory | 231436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500193003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3500193003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.928812161 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 54800620 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 07:56:00 PM UTC 24 |
| Finished | Sep 24 07:56:05 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928812161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.928812161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_random.884115663 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 429489502 ps |
| CPU time | 9.83 seconds |
| Started | Sep 24 07:55:57 PM UTC 24 |
| Finished | Sep 24 07:56:08 PM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884115663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.884115663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.680585179 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 4415801631 ps |
| CPU time | 40.67 seconds |
| Started | Sep 24 07:55:55 PM UTC 24 |
| Finished | Sep 24 07:56:37 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680585179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.680585179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.1979933870 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 66943904 ps |
| CPU time | 3 seconds |
| Started | Sep 24 07:55:56 PM UTC 24 |
| Finished | Sep 24 07:56:00 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979933870 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1979933870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.872571820 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1187894680 ps |
| CPU time | 8.72 seconds |
| Started | Sep 24 07:55:56 PM UTC 24 |
| Finished | Sep 24 07:56:06 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872571820 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.872571820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.3081831398 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 100257678 ps |
| CPU time | 2.41 seconds |
| Started | Sep 24 07:55:57 PM UTC 24 |
| Finished | Sep 24 07:56:01 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081831398 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3081831398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.224006105 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 27384558 ps |
| CPU time | 2.23 seconds |
| Started | Sep 24 07:56:02 PM UTC 24 |
| Finished | Sep 24 07:56:05 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224006105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.224006105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2731541412 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 119473248 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 07:55:55 PM UTC 24 |
| Finished | Sep 24 07:56:01 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731541412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2731541412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.137554399 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1374033649 ps |
| CPU time | 13.77 seconds |
| Started | Sep 24 07:56:03 PM UTC 24 |
| Finished | Sep 24 07:56:18 PM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137554399 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.137554399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.31536523 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 745845941 ps |
| CPU time | 20.68 seconds |
| Started | Sep 24 07:56:04 PM UTC 24 |
| Finished | Sep 24 07:56:26 PM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=31536523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_ stress_all_with_rand_reset.31536523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.1660264462 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 270416610 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 07:56:02 PM UTC 24 |
| Finished | Sep 24 07:56:07 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660264462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1660264462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.3376495888 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 40617974 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 07:56:15 PM UTC 24 |
| Finished | Sep 24 07:56:17 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376495888 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3376495888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.2661369130 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 121957168 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 07:56:09 PM UTC 24 |
| Finished | Sep 24 07:56:14 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661369130 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2661369130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.1439107966 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 88057402 ps |
| CPU time | 3.35 seconds |
| Started | Sep 24 07:56:12 PM UTC 24 |
| Finished | Sep 24 07:56:17 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439107966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1439107966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.4238186696 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 454558472 ps |
| CPU time | 10.87 seconds |
| Started | Sep 24 07:56:09 PM UTC 24 |
| Finished | Sep 24 07:56:21 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238186696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4238186696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.2228921357 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 287499603 ps |
| CPU time | 6.77 seconds |
| Started | Sep 24 07:56:10 PM UTC 24 |
| Finished | Sep 24 07:56:18 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228921357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2228921357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.4272973154 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 409152767 ps |
| CPU time | 4.51 seconds |
| Started | Sep 24 07:56:09 PM UTC 24 |
| Finished | Sep 24 07:56:15 PM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272973154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4272973154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.4060977411 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 106808074 ps |
| CPU time | 3.88 seconds |
| Started | Sep 24 07:56:07 PM UTC 24 |
| Finished | Sep 24 07:56:11 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060977411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4060977411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1792906079 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 132063027 ps |
| CPU time | 4.22 seconds |
| Started | Sep 24 07:56:08 PM UTC 24 |
| Finished | Sep 24 07:56:13 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792906079 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1792906079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.3323365849 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 230303808 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 07:56:07 PM UTC 24 |
| Finished | Sep 24 07:56:10 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323365849 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3323365849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.3961902476 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 142196526 ps |
| CPU time | 3.03 seconds |
| Started | Sep 24 07:56:08 PM UTC 24 |
| Finished | Sep 24 07:56:12 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961902476 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3961902476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.2845003477 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 36183121 ps |
| CPU time | 2.61 seconds |
| Started | Sep 24 07:56:12 PM UTC 24 |
| Finished | Sep 24 07:56:16 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845003477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2845003477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.891670990 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 75912036 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 07:56:06 PM UTC 24 |
| Finished | Sep 24 07:56:11 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891670990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.891670990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.208161536 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2883409003 ps |
| CPU time | 40.44 seconds |
| Started | Sep 24 07:56:14 PM UTC 24 |
| Finished | Sep 24 07:56:56 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208161536 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.208161536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.800855926 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 514562783 ps |
| CPU time | 6.16 seconds |
| Started | Sep 24 07:56:09 PM UTC 24 |
| Finished | Sep 24 07:56:16 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800855926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.800855926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.3555778465 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 182578284 ps |
| CPU time | 2.56 seconds |
| Started | Sep 24 07:56:12 PM UTC 24 |
| Finished | Sep 24 07:56:16 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555778465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3555778465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.2244441793 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 33110218 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 07:56:24 PM UTC 24 |
| Finished | Sep 24 07:56:26 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244441793 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2244441793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.1971261518 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 622793681 ps |
| CPU time | 4.09 seconds |
| Started | Sep 24 07:56:20 PM UTC 24 |
| Finished | Sep 24 07:56:25 PM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971261518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1971261518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.2105436496 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 836544025 ps |
| CPU time | 3.17 seconds |
| Started | Sep 24 07:56:18 PM UTC 24 |
| Finished | Sep 24 07:56:22 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105436496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2105436496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.217635600 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 35891822 ps |
| CPU time | 3.2 seconds |
| Started | Sep 24 07:56:20 PM UTC 24 |
| Finished | Sep 24 07:56:24 PM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217635600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.217635600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.1483103487 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 238980779 ps |
| CPU time | 4.57 seconds |
| Started | Sep 24 07:56:18 PM UTC 24 |
| Finished | Sep 24 07:56:24 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483103487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1483103487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_random.2662036052 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 98609527 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 07:56:18 PM UTC 24 |
| Finished | Sep 24 07:56:23 PM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662036052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2662036052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.3113498349 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2981901847 ps |
| CPU time | 17.67 seconds |
| Started | Sep 24 07:56:17 PM UTC 24 |
| Finished | Sep 24 07:56:36 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113498349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3113498349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.2605592318 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 166171969 ps |
| CPU time | 5.06 seconds |
| Started | Sep 24 07:56:17 PM UTC 24 |
| Finished | Sep 24 07:56:23 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605592318 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2605592318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.4166629860 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 464990734 ps |
| CPU time | 14.72 seconds |
| Started | Sep 24 07:56:17 PM UTC 24 |
| Finished | Sep 24 07:56:33 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166629860 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4166629860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.4160978916 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 365232673 ps |
| CPU time | 4.98 seconds |
| Started | Sep 24 07:56:17 PM UTC 24 |
| Finished | Sep 24 07:56:23 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160978916 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4160978916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.1044891890 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 383646115 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 07:56:21 PM UTC 24 |
| Finished | Sep 24 07:56:25 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044891890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1044891890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.1065296278 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 188872572 ps |
| CPU time | 3.36 seconds |
| Started | Sep 24 07:56:16 PM UTC 24 |
| Finished | Sep 24 07:56:20 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065296278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1065296278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.3603357092 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1339919938 ps |
| CPU time | 20.06 seconds |
| Started | Sep 24 07:56:22 PM UTC 24 |
| Finished | Sep 24 07:56:43 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603357092 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3603357092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.1617582374 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 195166464 ps |
| CPU time | 6.25 seconds |
| Started | Sep 24 07:56:20 PM UTC 24 |
| Finished | Sep 24 07:56:27 PM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617582374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1617582374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3899997836 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 42519757 ps |
| CPU time | 2.79 seconds |
| Started | Sep 24 07:56:21 PM UTC 24 |
| Finished | Sep 24 07:56:25 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899997836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3899997836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.1242896604 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 44485673 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 07:56:33 PM UTC 24 |
| Finished | Sep 24 07:56:35 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242896604 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1242896604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2611284154 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 108258366 ps |
| CPU time | 4.28 seconds |
| Started | Sep 24 07:56:26 PM UTC 24 |
| Finished | Sep 24 07:56:31 PM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611284154 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2611284154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.1157045349 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 252983492 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 07:56:29 PM UTC 24 |
| Finished | Sep 24 07:56:33 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157045349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1157045349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.3136856411 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 778731859 ps |
| CPU time | 4.49 seconds |
| Started | Sep 24 07:56:26 PM UTC 24 |
| Finished | Sep 24 07:56:31 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136856411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3136856411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.1560154149 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 80283857 ps |
| CPU time | 2.74 seconds |
| Started | Sep 24 07:56:28 PM UTC 24 |
| Finished | Sep 24 07:56:32 PM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560154149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1560154149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2384517087 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 65980067 ps |
| CPU time | 2.7 seconds |
| Started | Sep 24 07:56:28 PM UTC 24 |
| Finished | Sep 24 07:56:32 PM UTC 24 |
| Peak memory | 231284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384517087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2384517087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.3720938362 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 92477352 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 07:56:27 PM UTC 24 |
| Finished | Sep 24 07:56:34 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720938362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3720938362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_random.50366006 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 6636437776 ps |
| CPU time | 70.6 seconds |
| Started | Sep 24 07:56:26 PM UTC 24 |
| Finished | Sep 24 07:57:38 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50366006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.50366006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.2144600698 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 28949142 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 07:56:24 PM UTC 24 |
| Finished | Sep 24 07:56:28 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144600698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2144600698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.1340400308 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 61295536 ps |
| CPU time | 4.52 seconds |
| Started | Sep 24 07:56:26 PM UTC 24 |
| Finished | Sep 24 07:56:31 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340400308 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1340400308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.2487833313 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 112222701 ps |
| CPU time | 3.41 seconds |
| Started | Sep 24 07:56:24 PM UTC 24 |
| Finished | Sep 24 07:56:29 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487833313 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2487833313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.1034498185 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 20751927 ps |
| CPU time | 2.65 seconds |
| Started | Sep 24 07:56:26 PM UTC 24 |
| Finished | Sep 24 07:56:29 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034498185 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1034498185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.1071088053 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 331980525 ps |
| CPU time | 4.48 seconds |
| Started | Sep 24 07:56:29 PM UTC 24 |
| Finished | Sep 24 07:56:35 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071088053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1071088053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.3828816387 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 118773221 ps |
| CPU time | 5.32 seconds |
| Started | Sep 24 07:56:24 PM UTC 24 |
| Finished | Sep 24 07:56:31 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828816387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3828816387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.3255623554 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 365965289 ps |
| CPU time | 19.33 seconds |
| Started | Sep 24 07:56:31 PM UTC 24 |
| Finished | Sep 24 07:56:52 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255623554 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3255623554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.709255960 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 875780446 ps |
| CPU time | 24.91 seconds |
| Started | Sep 24 07:56:27 PM UTC 24 |
| Finished | Sep 24 07:56:53 PM UTC 24 |
| Peak memory | 223296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709255960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.709255960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.926031160 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 83618539 ps |
| CPU time | 2.24 seconds |
| Started | Sep 24 07:56:30 PM UTC 24 |
| Finished | Sep 24 07:56:34 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926031160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.926031160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.714416625 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 53860633 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 07:56:40 PM UTC 24 |
| Finished | Sep 24 07:56:42 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714416625 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.714416625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.3589633018 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 69416233 ps |
| CPU time | 4.78 seconds |
| Started | Sep 24 07:56:35 PM UTC 24 |
| Finished | Sep 24 07:56:41 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589633018 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3589633018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.3323738285 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 499221633 ps |
| CPU time | 7.78 seconds |
| Started | Sep 24 07:56:38 PM UTC 24 |
| Finished | Sep 24 07:56:47 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323738285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3323738285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.856673626 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 153724139 ps |
| CPU time | 2.54 seconds |
| Started | Sep 24 07:56:36 PM UTC 24 |
| Finished | Sep 24 07:56:40 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856673626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.856673626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.2457224493 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 142746422 ps |
| CPU time | 7.16 seconds |
| Started | Sep 24 07:56:36 PM UTC 24 |
| Finished | Sep 24 07:56:45 PM UTC 24 |
| Peak memory | 231452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457224493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2457224493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.3551560812 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 136895605 ps |
| CPU time | 4 seconds |
| Started | Sep 24 07:56:37 PM UTC 24 |
| Finished | Sep 24 07:56:42 PM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551560812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3551560812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.1205021346 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 75869269 ps |
| CPU time | 4.31 seconds |
| Started | Sep 24 07:56:36 PM UTC 24 |
| Finished | Sep 24 07:56:42 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205021346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1205021346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_random.4226451195 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 249626612 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 07:56:35 PM UTC 24 |
| Finished | Sep 24 07:56:40 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226451195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4226451195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.3037224267 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 129882533 ps |
| CPU time | 3 seconds |
| Started | Sep 24 07:56:33 PM UTC 24 |
| Finished | Sep 24 07:56:37 PM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037224267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3037224267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2262009976 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 76636467 ps |
| CPU time | 2.2 seconds |
| Started | Sep 24 07:56:34 PM UTC 24 |
| Finished | Sep 24 07:56:37 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262009976 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2262009976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1325705101 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 90660884 ps |
| CPU time | 4.65 seconds |
| Started | Sep 24 07:56:33 PM UTC 24 |
| Finished | Sep 24 07:56:39 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325705101 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1325705101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.1918018126 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 72773955 ps |
| CPU time | 3.49 seconds |
| Started | Sep 24 07:56:34 PM UTC 24 |
| Finished | Sep 24 07:56:39 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918018126 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1918018126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.3368580112 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 79203098 ps |
| CPU time | 2.46 seconds |
| Started | Sep 24 07:56:38 PM UTC 24 |
| Finished | Sep 24 07:56:41 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368580112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3368580112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.1251255541 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 49720965 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 07:56:33 PM UTC 24 |
| Finished | Sep 24 07:56:38 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251255541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1251255541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.2099750097 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 27591078030 ps |
| CPU time | 126.3 seconds |
| Started | Sep 24 07:56:39 PM UTC 24 |
| Finished | Sep 24 07:58:48 PM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099750097 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2099750097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.3250230678 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 591040028 ps |
| CPU time | 20.9 seconds |
| Started | Sep 24 07:56:36 PM UTC 24 |
| Finished | Sep 24 07:56:59 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250230678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3250230678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.3665856155 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 270014975 ps |
| CPU time | 3.19 seconds |
| Started | Sep 24 07:56:38 PM UTC 24 |
| Finished | Sep 24 07:56:42 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665856155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3665856155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.2499555821 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 56735383 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 07:56:51 PM UTC 24 |
| Finished | Sep 24 07:56:54 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499555821 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2499555821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.749994621 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 64284437 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:46 PM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749994621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.749994621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.2747825886 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 877036536 ps |
| CPU time | 7.65 seconds |
| Started | Sep 24 07:56:45 PM UTC 24 |
| Finished | Sep 24 07:56:53 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747825886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2747825886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.146843341 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 261066106 ps |
| CPU time | 3.29 seconds |
| Started | Sep 24 07:56:46 PM UTC 24 |
| Finished | Sep 24 07:56:50 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146843341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.146843341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.228098557 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 104897250 ps |
| CPU time | 5.31 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:50 PM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228098557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.228098557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_random.3139126362 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 59677336 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:48 PM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139126362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3139126362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.647210288 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 339019441 ps |
| CPU time | 5.86 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:50 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647210288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.647210288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.1342297826 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 262835121 ps |
| CPU time | 10.37 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:55 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342297826 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1342297826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.2086647292 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 903010455 ps |
| CPU time | 7.87 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:52 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086647292 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2086647292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.2564052629 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 52232247 ps |
| CPU time | 3.67 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:48 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564052629 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2564052629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.3721092845 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 648508740 ps |
| CPU time | 20.82 seconds |
| Started | Sep 24 07:56:48 PM UTC 24 |
| Finished | Sep 24 07:57:10 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721092845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3721092845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.3612173791 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 777642921 ps |
| CPU time | 18.72 seconds |
| Started | Sep 24 07:56:40 PM UTC 24 |
| Finished | Sep 24 07:57:00 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612173791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3612173791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.3951025117 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 196088359 ps |
| CPU time | 10.23 seconds |
| Started | Sep 24 07:56:43 PM UTC 24 |
| Finished | Sep 24 07:56:55 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951025117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3951025117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.131760522 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 89219636 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 07:56:49 PM UTC 24 |
| Finished | Sep 24 07:56:53 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131760522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.131760522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.1199556553 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 61543418 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 07:56:59 PM UTC 24 |
| Finished | Sep 24 07:57:01 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199556553 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1199556553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.3747060527 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 273347185 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 07:56:56 PM UTC 24 |
| Finished | Sep 24 07:57:01 PM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747060527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3747060527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2312947546 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 41398333 ps |
| CPU time | 2.56 seconds |
| Started | Sep 24 07:56:55 PM UTC 24 |
| Finished | Sep 24 07:56:59 PM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312947546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2312947546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.3963866803 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 52408188 ps |
| CPU time | 5.1 seconds |
| Started | Sep 24 07:56:56 PM UTC 24 |
| Finished | Sep 24 07:57:03 PM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963866803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3963866803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.446187491 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1032722637 ps |
| CPU time | 6.89 seconds |
| Started | Sep 24 07:56:55 PM UTC 24 |
| Finished | Sep 24 07:57:03 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446187491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.446187491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_random.1360915666 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 246046487 ps |
| CPU time | 11.03 seconds |
| Started | Sep 24 07:56:55 PM UTC 24 |
| Finished | Sep 24 07:57:07 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360915666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1360915666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.3141201503 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4930871088 ps |
| CPU time | 21.97 seconds |
| Started | Sep 24 07:56:51 PM UTC 24 |
| Finished | Sep 24 07:57:15 PM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141201503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3141201503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.2989949727 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 176173288 ps |
| CPU time | 9.47 seconds |
| Started | Sep 24 07:56:54 PM UTC 24 |
| Finished | Sep 24 07:57:04 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989949727 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2989949727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.3369591061 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 42029142 ps |
| CPU time | 2.92 seconds |
| Started | Sep 24 07:56:52 PM UTC 24 |
| Finished | Sep 24 07:56:57 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369591061 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3369591061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.2401364513 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 21244888 ps |
| CPU time | 2.57 seconds |
| Started | Sep 24 07:56:54 PM UTC 24 |
| Finished | Sep 24 07:56:57 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401364513 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2401364513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.2701304928 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 108644743 ps |
| CPU time | 4.23 seconds |
| Started | Sep 24 07:56:56 PM UTC 24 |
| Finished | Sep 24 07:57:02 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701304928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2701304928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.737863025 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 161261591 ps |
| CPU time | 3.38 seconds |
| Started | Sep 24 07:56:51 PM UTC 24 |
| Finished | Sep 24 07:56:56 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737863025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.737863025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.1106045499 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1096923526 ps |
| CPU time | 30.5 seconds |
| Started | Sep 24 07:56:57 PM UTC 24 |
| Finished | Sep 24 07:57:29 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106045499 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1106045499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2981505424 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 164572365 ps |
| CPU time | 7.42 seconds |
| Started | Sep 24 07:56:55 PM UTC 24 |
| Finished | Sep 24 07:57:04 PM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981505424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2981505424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.17942075 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1362629214 ps |
| CPU time | 11.82 seconds |
| Started | Sep 24 07:56:56 PM UTC 24 |
| Finished | Sep 24 07:57:09 PM UTC 24 |
| Peak memory | 219312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17942075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.17942075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.3666217705 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 16711183 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 07:51:33 PM UTC 24 |
| Finished | Sep 24 07:51:35 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666217705 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3666217705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.1113547071 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 125115927 ps |
| CPU time | 4.86 seconds |
| Started | Sep 24 07:51:27 PM UTC 24 |
| Finished | Sep 24 07:51:33 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113547071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1113547071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.3479196432 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 296534004 ps |
| CPU time | 3.03 seconds |
| Started | Sep 24 07:51:22 PM UTC 24 |
| Finished | Sep 24 07:51:26 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479196432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3479196432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.1751022935 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 132662329 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 07:51:26 PM UTC 24 |
| Finished | Sep 24 07:51:32 PM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751022935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1751022935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.1928289625 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 65657498 ps |
| CPU time | 4.46 seconds |
| Started | Sep 24 07:51:23 PM UTC 24 |
| Finished | Sep 24 07:51:29 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928289625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1928289625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_random.478356604 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2581064389 ps |
| CPU time | 30.59 seconds |
| Started | Sep 24 07:51:22 PM UTC 24 |
| Finished | Sep 24 07:51:54 PM UTC 24 |
| Peak memory | 217316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478356604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.478356604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.1434808666 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1602056838 ps |
| CPU time | 17.6 seconds |
| Started | Sep 24 07:51:32 PM UTC 24 |
| Finished | Sep 24 07:51:51 PM UTC 24 |
| Peak memory | 259408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434808666 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1434808666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.2050891198 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 143839574 ps |
| CPU time | 7.16 seconds |
| Started | Sep 24 07:51:18 PM UTC 24 |
| Finished | Sep 24 07:51:27 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050891198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2050891198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.482526395 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 434887715 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 07:51:20 PM UTC 24 |
| Finished | Sep 24 07:51:26 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482526395 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.482526395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.1565504549 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4377592765 ps |
| CPU time | 48.43 seconds |
| Started | Sep 24 07:51:20 PM UTC 24 |
| Finished | Sep 24 07:52:09 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565504549 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1565504549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.1188399673 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 205419608 ps |
| CPU time | 3.55 seconds |
| Started | Sep 24 07:51:20 PM UTC 24 |
| Finished | Sep 24 07:51:24 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188399673 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1188399673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.2675150451 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 43743272 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 07:51:27 PM UTC 24 |
| Finished | Sep 24 07:51:31 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675150451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2675150451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.1113252240 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 37685142 ps |
| CPU time | 3.37 seconds |
| Started | Sep 24 07:51:17 PM UTC 24 |
| Finished | Sep 24 07:51:22 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113252240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1113252240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.2649059963 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 12182295435 ps |
| CPU time | 284.78 seconds |
| Started | Sep 24 07:51:30 PM UTC 24 |
| Finished | Sep 24 07:56:19 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649059963 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2649059963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.2097886365 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 58876549 ps |
| CPU time | 3.56 seconds |
| Started | Sep 24 07:51:25 PM UTC 24 |
| Finished | Sep 24 07:51:30 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097886365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2097886365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.214130781 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 220606374 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 07:51:28 PM UTC 24 |
| Finished | Sep 24 07:51:33 PM UTC 24 |
| Peak memory | 219312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214130781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.214130781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.4052682085 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 40773690 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 07:57:07 PM UTC 24 |
| Finished | Sep 24 07:57:09 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052682085 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4052682085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.2056442367 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 55017486 ps |
| CPU time | 5.37 seconds |
| Started | Sep 24 07:57:03 PM UTC 24 |
| Finished | Sep 24 07:57:10 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056442367 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2056442367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.313925649 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 319771648 ps |
| CPU time | 5.52 seconds |
| Started | Sep 24 07:57:06 PM UTC 24 |
| Finished | Sep 24 07:57:12 PM UTC 24 |
| Peak memory | 226124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313925649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.313925649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.973525104 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 305217792 ps |
| CPU time | 3.94 seconds |
| Started | Sep 24 07:57:03 PM UTC 24 |
| Finished | Sep 24 07:57:08 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973525104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.973525104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.3052265020 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 17448446 ps |
| CPU time | 2.75 seconds |
| Started | Sep 24 07:57:04 PM UTC 24 |
| Finished | Sep 24 07:57:08 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052265020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3052265020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.2698062255 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 96276394 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 07:57:04 PM UTC 24 |
| Finished | Sep 24 07:57:09 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698062255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2698062255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.799104262 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 146263254 ps |
| CPU time | 3.27 seconds |
| Started | Sep 24 07:57:03 PM UTC 24 |
| Finished | Sep 24 07:57:07 PM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799104262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.799104262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_random.2154759428 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 87211034 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 07:57:02 PM UTC 24 |
| Finished | Sep 24 07:57:06 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154759428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2154759428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.4115758978 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 124788957 ps |
| CPU time | 4.89 seconds |
| Started | Sep 24 07:57:00 PM UTC 24 |
| Finished | Sep 24 07:57:06 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115758978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4115758978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.2693600247 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 69656795 ps |
| CPU time | 3.62 seconds |
| Started | Sep 24 07:57:02 PM UTC 24 |
| Finished | Sep 24 07:57:07 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693600247 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2693600247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.1340683640 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 6237734592 ps |
| CPU time | 29.42 seconds |
| Started | Sep 24 07:57:01 PM UTC 24 |
| Finished | Sep 24 07:57:32 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340683640 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1340683640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.961305135 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 126068987 ps |
| CPU time | 5.71 seconds |
| Started | Sep 24 07:57:02 PM UTC 24 |
| Finished | Sep 24 07:57:09 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961305135 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.961305135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.273952770 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1030631029 ps |
| CPU time | 9.49 seconds |
| Started | Sep 24 07:57:06 PM UTC 24 |
| Finished | Sep 24 07:57:16 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273952770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.273952770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.2326294956 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 153511583 ps |
| CPU time | 5.2 seconds |
| Started | Sep 24 07:57:00 PM UTC 24 |
| Finished | Sep 24 07:57:06 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326294956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2326294956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.3389365904 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1153542704 ps |
| CPU time | 17.56 seconds |
| Started | Sep 24 07:57:07 PM UTC 24 |
| Finished | Sep 24 07:57:26 PM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3389365904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg r_stress_all_with_rand_reset.3389365904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3882678578 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 82537181 ps |
| CPU time | 4.01 seconds |
| Started | Sep 24 07:57:04 PM UTC 24 |
| Finished | Sep 24 07:57:09 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882678578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3882678578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.4250323687 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 65541186 ps |
| CPU time | 2.07 seconds |
| Started | Sep 24 07:57:07 PM UTC 24 |
| Finished | Sep 24 07:57:10 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250323687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4250323687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.1266343790 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 117229549 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 07:57:15 PM UTC 24 |
| Finished | Sep 24 07:57:17 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266343790 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1266343790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.3127031408 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 105165761 ps |
| CPU time | 2.74 seconds |
| Started | Sep 24 07:57:11 PM UTC 24 |
| Finished | Sep 24 07:57:15 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127031408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3127031408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.2466661867 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3052050811 ps |
| CPU time | 21.08 seconds |
| Started | Sep 24 07:57:11 PM UTC 24 |
| Finished | Sep 24 07:57:33 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466661867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2466661867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.2555240387 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 383321343 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 07:57:11 PM UTC 24 |
| Finished | Sep 24 07:57:17 PM UTC 24 |
| Peak memory | 231484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555240387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2555240387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.2901336796 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 72334000 ps |
| CPU time | 2.58 seconds |
| Started | Sep 24 07:57:11 PM UTC 24 |
| Finished | Sep 24 07:57:15 PM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901336796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2901336796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.342388000 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 107937027 ps |
| CPU time | 5.37 seconds |
| Started | Sep 24 07:57:11 PM UTC 24 |
| Finished | Sep 24 07:57:17 PM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342388000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.342388000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_random.1756275876 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2762176093 ps |
| CPU time | 23.01 seconds |
| Started | Sep 24 07:57:09 PM UTC 24 |
| Finished | Sep 24 07:57:34 PM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756275876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1756275876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.198777041 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 161682191 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 07:57:08 PM UTC 24 |
| Finished | Sep 24 07:57:13 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198777041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.198777041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.3610556882 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 372946619 ps |
| CPU time | 9.42 seconds |
| Started | Sep 24 07:57:09 PM UTC 24 |
| Finished | Sep 24 07:57:20 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610556882 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3610556882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.4140591009 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2934052534 ps |
| CPU time | 26.02 seconds |
| Started | Sep 24 07:57:08 PM UTC 24 |
| Finished | Sep 24 07:57:35 PM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140591009 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4140591009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.3810861160 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 106251126 ps |
| CPU time | 3.55 seconds |
| Started | Sep 24 07:57:09 PM UTC 24 |
| Finished | Sep 24 07:57:14 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810861160 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3810861160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.1349649442 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 208489635 ps |
| CPU time | 3.59 seconds |
| Started | Sep 24 07:57:13 PM UTC 24 |
| Finished | Sep 24 07:57:18 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349649442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1349649442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.3864719855 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1933537760 ps |
| CPU time | 4.27 seconds |
| Started | Sep 24 07:57:08 PM UTC 24 |
| Finished | Sep 24 07:57:13 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864719855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3864719855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.398263199 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 919297158 ps |
| CPU time | 7.43 seconds |
| Started | Sep 24 07:57:14 PM UTC 24 |
| Finished | Sep 24 07:57:23 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398263199 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.398263199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.1001504816 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 479053073 ps |
| CPU time | 5.66 seconds |
| Started | Sep 24 07:57:11 PM UTC 24 |
| Finished | Sep 24 07:57:18 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001504816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1001504816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2942039045 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 187725844 ps |
| CPU time | 2.21 seconds |
| Started | Sep 24 07:57:13 PM UTC 24 |
| Finished | Sep 24 07:57:16 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942039045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2942039045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.3238117365 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 44260068 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 07:57:25 PM UTC 24 |
| Finished | Sep 24 07:57:27 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238117365 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3238117365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.3377758594 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 223705464 ps |
| CPU time | 3.36 seconds |
| Started | Sep 24 07:57:19 PM UTC 24 |
| Finished | Sep 24 07:57:23 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377758594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3377758594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1917924704 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 112389998 ps |
| CPU time | 6.56 seconds |
| Started | Sep 24 07:57:20 PM UTC 24 |
| Finished | Sep 24 07:57:28 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917924704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1917924704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.940967817 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 354030214 ps |
| CPU time | 6.04 seconds |
| Started | Sep 24 07:57:22 PM UTC 24 |
| Finished | Sep 24 07:57:29 PM UTC 24 |
| Peak memory | 223424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940967817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.940967817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.864866195 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 285083121 ps |
| CPU time | 6.22 seconds |
| Started | Sep 24 07:57:19 PM UTC 24 |
| Finished | Sep 24 07:57:26 PM UTC 24 |
| Peak memory | 219664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864866195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.864866195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_random.2654713634 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2176667014 ps |
| CPU time | 58.4 seconds |
| Started | Sep 24 07:57:18 PM UTC 24 |
| Finished | Sep 24 07:58:18 PM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654713634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2654713634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.2766449664 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 289522968 ps |
| CPU time | 10.14 seconds |
| Started | Sep 24 07:57:15 PM UTC 24 |
| Finished | Sep 24 07:57:27 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766449664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2766449664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.3066591198 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 96393172 ps |
| CPU time | 5.39 seconds |
| Started | Sep 24 07:57:18 PM UTC 24 |
| Finished | Sep 24 07:57:24 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066591198 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3066591198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.167168909 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 98305750 ps |
| CPU time | 4.87 seconds |
| Started | Sep 24 07:57:18 PM UTC 24 |
| Finished | Sep 24 07:57:23 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167168909 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.167168909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.5361854 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 139353062 ps |
| CPU time | 4.34 seconds |
| Started | Sep 24 07:57:18 PM UTC 24 |
| Finished | Sep 24 07:57:23 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5361854 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.5361854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.1030035073 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 267404220 ps |
| CPU time | 4.83 seconds |
| Started | Sep 24 07:57:22 PM UTC 24 |
| Finished | Sep 24 07:57:28 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030035073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1030035073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.1248077233 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 50356784 ps |
| CPU time | 3.35 seconds |
| Started | Sep 24 07:57:15 PM UTC 24 |
| Finished | Sep 24 07:57:20 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248077233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1248077233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1306214068 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 230449439 ps |
| CPU time | 4.49 seconds |
| Started | Sep 24 07:57:19 PM UTC 24 |
| Finished | Sep 24 07:57:25 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306214068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1306214068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.295363770 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 41745910 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 07:57:33 PM UTC 24 |
| Finished | Sep 24 07:57:35 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295363770 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.295363770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.688408911 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 349109150 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 07:57:28 PM UTC 24 |
| Finished | Sep 24 07:57:33 PM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688408911 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.688408911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.2857861275 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 120307478 ps |
| CPU time | 6.94 seconds |
| Started | Sep 24 07:57:30 PM UTC 24 |
| Finished | Sep 24 07:57:38 PM UTC 24 |
| Peak memory | 227912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857861275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2857861275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.1872657384 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 530589764 ps |
| CPU time | 6.08 seconds |
| Started | Sep 24 07:57:28 PM UTC 24 |
| Finished | Sep 24 07:57:36 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872657384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1872657384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.3656287416 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 31989424 ps |
| CPU time | 3.15 seconds |
| Started | Sep 24 07:57:30 PM UTC 24 |
| Finished | Sep 24 07:57:34 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656287416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3656287416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.3217607713 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 105575993 ps |
| CPU time | 7.35 seconds |
| Started | Sep 24 07:57:30 PM UTC 24 |
| Finished | Sep 24 07:57:38 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217607713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3217607713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.4153619115 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 265370551 ps |
| CPU time | 4.67 seconds |
| Started | Sep 24 07:57:28 PM UTC 24 |
| Finished | Sep 24 07:57:34 PM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153619115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4153619115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_random.334112530 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 981043803 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 07:57:28 PM UTC 24 |
| Finished | Sep 24 07:57:35 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334112530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.334112530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.904922453 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 103581334 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 07:57:26 PM UTC 24 |
| Finished | Sep 24 07:57:29 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904922453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.904922453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.1039295539 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 424316498 ps |
| CPU time | 7.94 seconds |
| Started | Sep 24 07:57:27 PM UTC 24 |
| Finished | Sep 24 07:57:36 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039295539 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1039295539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.3866773893 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 70861098 ps |
| CPU time | 4.05 seconds |
| Started | Sep 24 07:57:27 PM UTC 24 |
| Finished | Sep 24 07:57:32 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866773893 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3866773893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.2663636647 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 73519002 ps |
| CPU time | 2.72 seconds |
| Started | Sep 24 07:57:28 PM UTC 24 |
| Finished | Sep 24 07:57:32 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663636647 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2663636647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.592097316 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 28652388 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 07:57:31 PM UTC 24 |
| Finished | Sep 24 07:57:35 PM UTC 24 |
| Peak memory | 223552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592097316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.592097316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.2112182561 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 582029006 ps |
| CPU time | 6 seconds |
| Started | Sep 24 07:57:25 PM UTC 24 |
| Finished | Sep 24 07:57:32 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112182561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2112182561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3739138872 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 172796562 ps |
| CPU time | 6.54 seconds |
| Started | Sep 24 07:57:33 PM UTC 24 |
| Finished | Sep 24 07:57:41 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739138872 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3739138872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.2102387216 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 551970284 ps |
| CPU time | 10.54 seconds |
| Started | Sep 24 07:57:33 PM UTC 24 |
| Finished | Sep 24 07:57:45 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2102387216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymg r_stress_all_with_rand_reset.2102387216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.2129486599 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 148502873 ps |
| CPU time | 7.27 seconds |
| Started | Sep 24 07:57:28 PM UTC 24 |
| Finished | Sep 24 07:57:37 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129486599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2129486599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.151841865 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 47881592 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 07:57:31 PM UTC 24 |
| Finished | Sep 24 07:57:34 PM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151841865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.151841865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.3595770818 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 31569159 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:57:42 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595770818 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3595770818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.3409532348 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 176321978 ps |
| CPU time | 11.33 seconds |
| Started | Sep 24 07:57:36 PM UTC 24 |
| Finished | Sep 24 07:57:48 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409532348 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3409532348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.2561775382 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 522212854 ps |
| CPU time | 5.64 seconds |
| Started | Sep 24 07:57:37 PM UTC 24 |
| Finished | Sep 24 07:57:44 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561775382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2561775382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.1709792387 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2259428992 ps |
| CPU time | 21.21 seconds |
| Started | Sep 24 07:57:36 PM UTC 24 |
| Finished | Sep 24 07:57:58 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709792387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1709792387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.1376192143 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 171984989 ps |
| CPU time | 4.15 seconds |
| Started | Sep 24 07:57:37 PM UTC 24 |
| Finished | Sep 24 07:57:42 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376192143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1376192143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.1479316528 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 79186173 ps |
| CPU time | 4.05 seconds |
| Started | Sep 24 07:57:37 PM UTC 24 |
| Finished | Sep 24 07:57:42 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479316528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1479316528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.2204225523 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 52777107 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 07:57:36 PM UTC 24 |
| Finished | Sep 24 07:57:41 PM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204225523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2204225523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_random.3775917220 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1047102904 ps |
| CPU time | 8.66 seconds |
| Started | Sep 24 07:57:36 PM UTC 24 |
| Finished | Sep 24 07:57:45 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775917220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3775917220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.1675033316 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 39577526 ps |
| CPU time | 2.92 seconds |
| Started | Sep 24 07:57:34 PM UTC 24 |
| Finished | Sep 24 07:57:38 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675033316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1675033316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.229636287 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 180491317 ps |
| CPU time | 3.73 seconds |
| Started | Sep 24 07:57:34 PM UTC 24 |
| Finished | Sep 24 07:57:39 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229636287 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.229636287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.2529296861 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 229836166 ps |
| CPU time | 3.88 seconds |
| Started | Sep 24 07:57:34 PM UTC 24 |
| Finished | Sep 24 07:57:39 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529296861 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2529296861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.329026585 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 68702927 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 07:57:36 PM UTC 24 |
| Finished | Sep 24 07:57:40 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329026585 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.329026585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.259751473 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 44938112 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 07:57:37 PM UTC 24 |
| Finished | Sep 24 07:57:41 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259751473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.259751473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.480242421 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 111306365 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 07:57:33 PM UTC 24 |
| Finished | Sep 24 07:57:37 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480242421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.480242421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.3357571241 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 14031817083 ps |
| CPU time | 84.76 seconds |
| Started | Sep 24 07:57:38 PM UTC 24 |
| Finished | Sep 24 07:59:05 PM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357571241 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3357571241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.3203463940 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1124928006 ps |
| CPU time | 16.66 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:57:58 PM UTC 24 |
| Peak memory | 231752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3203463940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.3203463940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.3082434920 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 125530997 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 07:57:36 PM UTC 24 |
| Finished | Sep 24 07:57:41 PM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082434920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3082434920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.969274553 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 655034164 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 07:57:38 PM UTC 24 |
| Finished | Sep 24 07:57:44 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969274553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.969274553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.1674512957 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 20172032 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 07:57:45 PM UTC 24 |
| Finished | Sep 24 07:57:47 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674512957 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1674512957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.390022750 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 110027518 ps |
| CPU time | 6.28 seconds |
| Started | Sep 24 07:57:41 PM UTC 24 |
| Finished | Sep 24 07:57:49 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390022750 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.390022750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.2686816638 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 34302802 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 07:57:43 PM UTC 24 |
| Finished | Sep 24 07:57:47 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686816638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2686816638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.2049870920 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 116298160 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 07:57:41 PM UTC 24 |
| Finished | Sep 24 07:57:46 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049870920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2049870920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3986881134 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 622060712 ps |
| CPU time | 4.64 seconds |
| Started | Sep 24 07:57:42 PM UTC 24 |
| Finished | Sep 24 07:57:47 PM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986881134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3986881134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.3462507071 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 437070498 ps |
| CPU time | 4.85 seconds |
| Started | Sep 24 07:57:43 PM UTC 24 |
| Finished | Sep 24 07:57:49 PM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462507071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3462507071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.2089619006 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 184827167 ps |
| CPU time | 5.2 seconds |
| Started | Sep 24 07:57:41 PM UTC 24 |
| Finished | Sep 24 07:57:48 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089619006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2089619006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_random.1124528967 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 200356608 ps |
| CPU time | 5.17 seconds |
| Started | Sep 24 07:57:41 PM UTC 24 |
| Finished | Sep 24 07:57:48 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124528967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1124528967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.2211277966 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1750113238 ps |
| CPU time | 50.21 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:58:32 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211277966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2211277966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.60420272 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 38288557 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:57:44 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60420272 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.60420272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.426744279 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 53070286 ps |
| CPU time | 4.34 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:57:45 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426744279 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.426744279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.831802645 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 394648596 ps |
| CPU time | 9.12 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:57:50 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831802645 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.831802645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.2082866856 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 456795272 ps |
| CPU time | 6.23 seconds |
| Started | Sep 24 07:57:43 PM UTC 24 |
| Finished | Sep 24 07:57:50 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082866856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2082866856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.2250702054 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1660165695 ps |
| CPU time | 16.49 seconds |
| Started | Sep 24 07:57:40 PM UTC 24 |
| Finished | Sep 24 07:57:58 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250702054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2250702054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.1758608885 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1095767948 ps |
| CPU time | 16.79 seconds |
| Started | Sep 24 07:57:45 PM UTC 24 |
| Finished | Sep 24 07:58:03 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758608885 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1758608885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.4013131147 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 584979239 ps |
| CPU time | 8.71 seconds |
| Started | Sep 24 07:57:41 PM UTC 24 |
| Finished | Sep 24 07:57:51 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013131147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4013131147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.1356627168 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 588882874 ps |
| CPU time | 5.66 seconds |
| Started | Sep 24 07:57:43 PM UTC 24 |
| Finished | Sep 24 07:57:50 PM UTC 24 |
| Peak memory | 219636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356627168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1356627168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2306956854 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 30644584 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 07:57:51 PM UTC 24 |
| Finished | Sep 24 07:57:54 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306956854 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2306956854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.1478009204 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 67040747 ps |
| CPU time | 7.03 seconds |
| Started | Sep 24 07:57:49 PM UTC 24 |
| Finished | Sep 24 07:57:57 PM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478009204 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1478009204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.221729997 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 950665785 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 07:57:50 PM UTC 24 |
| Finished | Sep 24 07:57:56 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221729997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.221729997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.2267532046 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 790407441 ps |
| CPU time | 6.98 seconds |
| Started | Sep 24 07:57:49 PM UTC 24 |
| Finished | Sep 24 07:57:57 PM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267532046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2267532046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.627686233 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 410751840 ps |
| CPU time | 6.04 seconds |
| Started | Sep 24 07:57:50 PM UTC 24 |
| Finished | Sep 24 07:57:57 PM UTC 24 |
| Peak memory | 229924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627686233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.627686233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.3469181445 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 55621659 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 07:57:50 PM UTC 24 |
| Finished | Sep 24 07:57:55 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469181445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3469181445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.1759583355 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1134831745 ps |
| CPU time | 5.04 seconds |
| Started | Sep 24 07:57:49 PM UTC 24 |
| Finished | Sep 24 07:57:55 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759583355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1759583355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_random.1284477991 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 149619440 ps |
| CPU time | 8.04 seconds |
| Started | Sep 24 07:57:49 PM UTC 24 |
| Finished | Sep 24 07:57:58 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284477991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1284477991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.616209792 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 233454434 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 07:57:46 PM UTC 24 |
| Finished | Sep 24 07:57:51 PM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616209792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.616209792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.1278007120 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3317361770 ps |
| CPU time | 25.8 seconds |
| Started | Sep 24 07:57:47 PM UTC 24 |
| Finished | Sep 24 07:58:14 PM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278007120 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1278007120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.308667834 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 21200061 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 07:57:46 PM UTC 24 |
| Finished | Sep 24 07:57:49 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308667834 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.308667834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.4076075829 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 246350520 ps |
| CPU time | 3.61 seconds |
| Started | Sep 24 07:57:47 PM UTC 24 |
| Finished | Sep 24 07:57:52 PM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076075829 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4076075829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.482858953 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 2133882971 ps |
| CPU time | 17.35 seconds |
| Started | Sep 24 07:57:51 PM UTC 24 |
| Finished | Sep 24 07:58:10 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482858953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.482858953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.1136815543 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 46937581 ps |
| CPU time | 3.27 seconds |
| Started | Sep 24 07:57:46 PM UTC 24 |
| Finished | Sep 24 07:57:51 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136815543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1136815543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.3666439390 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 934107082 ps |
| CPU time | 9.11 seconds |
| Started | Sep 24 07:57:51 PM UTC 24 |
| Finished | Sep 24 07:58:01 PM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666439390 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3666439390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.3339111411 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3394826454 ps |
| CPU time | 20.51 seconds |
| Started | Sep 24 07:57:50 PM UTC 24 |
| Finished | Sep 24 07:58:12 PM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339111411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3339111411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.2834904552 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 39041791 ps |
| CPU time | 3.11 seconds |
| Started | Sep 24 07:57:51 PM UTC 24 |
| Finished | Sep 24 07:57:55 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834904552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2834904552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.447837881 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 11081450 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 07:58:01 PM UTC 24 |
| Finished | Sep 24 07:58:03 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447837881 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.447837881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.61944756 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 275445149 ps |
| CPU time | 6.27 seconds |
| Started | Sep 24 07:57:58 PM UTC 24 |
| Finished | Sep 24 07:58:06 PM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61944756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.61944756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.4075459138 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 32776824 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 07:57:57 PM UTC 24 |
| Finished | Sep 24 07:58:00 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075459138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4075459138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.975436477 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 643511992 ps |
| CPU time | 15.19 seconds |
| Started | Sep 24 07:57:58 PM UTC 24 |
| Finished | Sep 24 07:58:15 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975436477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.975436477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.2441150900 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 241886421 ps |
| CPU time | 3.79 seconds |
| Started | Sep 24 07:57:58 PM UTC 24 |
| Finished | Sep 24 07:58:03 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441150900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2441150900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.2745410636 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 527102350 ps |
| CPU time | 4.83 seconds |
| Started | Sep 24 07:57:58 PM UTC 24 |
| Finished | Sep 24 07:58:04 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745410636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2745410636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_random.3276374482 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 472507505 ps |
| CPU time | 4.24 seconds |
| Started | Sep 24 07:57:56 PM UTC 24 |
| Finished | Sep 24 07:58:01 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276374482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3276374482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2790700315 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 145606734 ps |
| CPU time | 6.49 seconds |
| Started | Sep 24 07:57:53 PM UTC 24 |
| Finished | Sep 24 07:58:00 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790700315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2790700315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.1522626600 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 631924745 ps |
| CPU time | 5.57 seconds |
| Started | Sep 24 07:57:55 PM UTC 24 |
| Finished | Sep 24 07:58:01 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522626600 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1522626600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.3180517313 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 55638433 ps |
| CPU time | 3.65 seconds |
| Started | Sep 24 07:57:53 PM UTC 24 |
| Finished | Sep 24 07:57:57 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180517313 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3180517313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.962172478 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 675234940 ps |
| CPU time | 9.55 seconds |
| Started | Sep 24 07:57:56 PM UTC 24 |
| Finished | Sep 24 07:58:07 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962172478 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.962172478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1631557863 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 166352167 ps |
| CPU time | 4.12 seconds |
| Started | Sep 24 07:57:59 PM UTC 24 |
| Finished | Sep 24 07:58:05 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631557863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1631557863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.3609827032 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 27324094977 ps |
| CPU time | 36.04 seconds |
| Started | Sep 24 07:57:52 PM UTC 24 |
| Finished | Sep 24 07:58:30 PM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609827032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3609827032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.210991611 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 33462905841 ps |
| CPU time | 136.02 seconds |
| Started | Sep 24 07:58:00 PM UTC 24 |
| Finished | Sep 24 08:00:18 PM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210991611 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.210991611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.3790297817 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 196903703 ps |
| CPU time | 18.02 seconds |
| Started | Sep 24 07:58:00 PM UTC 24 |
| Finished | Sep 24 07:58:19 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3790297817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg r_stress_all_with_rand_reset.3790297817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.1183554821 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 353797679 ps |
| CPU time | 8.99 seconds |
| Started | Sep 24 07:57:58 PM UTC 24 |
| Finished | Sep 24 07:58:08 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183554821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1183554821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.2303159750 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 53669481 ps |
| CPU time | 3.36 seconds |
| Started | Sep 24 07:58:00 PM UTC 24 |
| Finished | Sep 24 07:58:04 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303159750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2303159750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.3354445056 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 61948356 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 07:58:10 PM UTC 24 |
| Finished | Sep 24 07:58:13 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354445056 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3354445056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.3481541197 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 118361879 ps |
| CPU time | 5.55 seconds |
| Started | Sep 24 07:58:04 PM UTC 24 |
| Finished | Sep 24 07:58:11 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481541197 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3481541197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.1682369485 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 75058453 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 07:58:05 PM UTC 24 |
| Finished | Sep 24 07:58:10 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682369485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1682369485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.4000938934 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 121070202 ps |
| CPU time | 4.77 seconds |
| Started | Sep 24 07:58:07 PM UTC 24 |
| Finished | Sep 24 07:58:12 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000938934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4000938934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.2417188932 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 54515816 ps |
| CPU time | 3.3 seconds |
| Started | Sep 24 07:58:08 PM UTC 24 |
| Finished | Sep 24 07:58:12 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417188932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2417188932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.2533873707 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 300194403 ps |
| CPU time | 4.79 seconds |
| Started | Sep 24 07:58:05 PM UTC 24 |
| Finished | Sep 24 07:58:11 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533873707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2533873707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_random.3048764636 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1917456288 ps |
| CPU time | 50.46 seconds |
| Started | Sep 24 07:58:04 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048764636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3048764636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.64157785 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 161776519 ps |
| CPU time | 4.6 seconds |
| Started | Sep 24 07:58:02 PM UTC 24 |
| Finished | Sep 24 07:58:08 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64157785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.64157785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.3005652179 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 79150802 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 07:58:02 PM UTC 24 |
| Finished | Sep 24 07:58:08 PM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005652179 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3005652179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.2758728888 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 156620842 ps |
| CPU time | 4.6 seconds |
| Started | Sep 24 07:58:02 PM UTC 24 |
| Finished | Sep 24 07:58:08 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758728888 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2758728888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.783402599 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 235116145 ps |
| CPU time | 6.47 seconds |
| Started | Sep 24 07:58:04 PM UTC 24 |
| Finished | Sep 24 07:58:12 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783402599 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.783402599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.2214512043 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 136395817 ps |
| CPU time | 5.85 seconds |
| Started | Sep 24 07:58:09 PM UTC 24 |
| Finished | Sep 24 07:58:16 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214512043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2214512043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.4083033055 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 2843012570 ps |
| CPU time | 7.72 seconds |
| Started | Sep 24 07:58:01 PM UTC 24 |
| Finished | Sep 24 07:58:10 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083033055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4083033055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.2184743647 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 803055535 ps |
| CPU time | 8.59 seconds |
| Started | Sep 24 07:58:10 PM UTC 24 |
| Finished | Sep 24 07:58:20 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2184743647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.2184743647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.554194547 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 269531179 ps |
| CPU time | 6.06 seconds |
| Started | Sep 24 07:58:05 PM UTC 24 |
| Finished | Sep 24 07:58:13 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554194547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.554194547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.3499535372 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2410947103 ps |
| CPU time | 20.13 seconds |
| Started | Sep 24 07:58:09 PM UTC 24 |
| Finished | Sep 24 07:58:30 PM UTC 24 |
| Peak memory | 219372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499535372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3499535372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.3012228200 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 37968630 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 07:58:19 PM UTC 24 |
| Finished | Sep 24 07:58:21 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012228200 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3012228200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.3424433234 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 447249037 ps |
| CPU time | 5.48 seconds |
| Started | Sep 24 07:58:15 PM UTC 24 |
| Finished | Sep 24 07:58:22 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424433234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3424433234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1968723993 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1805769447 ps |
| CPU time | 12.62 seconds |
| Started | Sep 24 07:58:14 PM UTC 24 |
| Finished | Sep 24 07:58:28 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968723993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1968723993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.1145174473 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 451173399 ps |
| CPU time | 7.57 seconds |
| Started | Sep 24 07:58:14 PM UTC 24 |
| Finished | Sep 24 07:58:23 PM UTC 24 |
| Peak memory | 230196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145174473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1145174473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.2912497233 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 113956320 ps |
| CPU time | 6.66 seconds |
| Started | Sep 24 07:58:15 PM UTC 24 |
| Finished | Sep 24 07:58:23 PM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912497233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2912497233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.2859978735 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 491160911 ps |
| CPU time | 4.59 seconds |
| Started | Sep 24 07:58:14 PM UTC 24 |
| Finished | Sep 24 07:58:19 PM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859978735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2859978735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_random.2740102370 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1084756701 ps |
| CPU time | 14.39 seconds |
| Started | Sep 24 07:58:13 PM UTC 24 |
| Finished | Sep 24 07:58:28 PM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740102370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2740102370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.1012569112 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 233620803 ps |
| CPU time | 4.59 seconds |
| Started | Sep 24 07:58:11 PM UTC 24 |
| Finished | Sep 24 07:58:17 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012569112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1012569112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.3595866748 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 263073904 ps |
| CPU time | 4.97 seconds |
| Started | Sep 24 07:58:12 PM UTC 24 |
| Finished | Sep 24 07:58:18 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595866748 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3595866748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.2374929275 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 24891458975 ps |
| CPU time | 49.1 seconds |
| Started | Sep 24 07:58:11 PM UTC 24 |
| Finished | Sep 24 07:59:02 PM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374929275 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2374929275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.1281839204 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 784589231 ps |
| CPU time | 10.61 seconds |
| Started | Sep 24 07:58:13 PM UTC 24 |
| Finished | Sep 24 07:58:24 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281839204 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1281839204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.300664861 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 177491174 ps |
| CPU time | 4.14 seconds |
| Started | Sep 24 07:58:15 PM UTC 24 |
| Finished | Sep 24 07:58:20 PM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300664861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.300664861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.189225889 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 55340601 ps |
| CPU time | 3.12 seconds |
| Started | Sep 24 07:58:11 PM UTC 24 |
| Finished | Sep 24 07:58:15 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189225889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.189225889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.650847890 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 215665511 ps |
| CPU time | 7.38 seconds |
| Started | Sep 24 07:58:14 PM UTC 24 |
| Finished | Sep 24 07:58:22 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650847890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.650847890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.3897511595 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1772724209 ps |
| CPU time | 6.46 seconds |
| Started | Sep 24 07:58:16 PM UTC 24 |
| Finished | Sep 24 07:58:24 PM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897511595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3897511595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.952940803 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 13287002 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:52:02 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952940803 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.952940803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.599776657 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 81296989 ps |
| CPU time | 2.45 seconds |
| Started | Sep 24 07:51:57 PM UTC 24 |
| Finished | Sep 24 07:52:01 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599776657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.599776657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.121872747 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 377370462 ps |
| CPU time | 12.51 seconds |
| Started | Sep 24 07:51:45 PM UTC 24 |
| Finished | Sep 24 07:51:58 PM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121872747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.121872747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.1240743567 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 32636334 ps |
| CPU time | 3.37 seconds |
| Started | Sep 24 07:51:49 PM UTC 24 |
| Finished | Sep 24 07:51:53 PM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240743567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1240743567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.2238409802 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 327056671 ps |
| CPU time | 5.09 seconds |
| Started | Sep 24 07:51:57 PM UTC 24 |
| Finished | Sep 24 07:52:04 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238409802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2238409802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.3541621260 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 302683355 ps |
| CPU time | 5.9 seconds |
| Started | Sep 24 07:51:46 PM UTC 24 |
| Finished | Sep 24 07:51:53 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541621260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3541621260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_random.893489078 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 439460762 ps |
| CPU time | 6.55 seconds |
| Started | Sep 24 07:51:40 PM UTC 24 |
| Finished | Sep 24 07:51:48 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893489078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.893489078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.1249183153 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 280277103 ps |
| CPU time | 10.72 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:52:11 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249183153 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1249183153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.933203813 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 201754295 ps |
| CPU time | 9.11 seconds |
| Started | Sep 24 07:51:34 PM UTC 24 |
| Finished | Sep 24 07:51:44 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933203813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.933203813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.2492746654 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 201954234 ps |
| CPU time | 5.53 seconds |
| Started | Sep 24 07:51:37 PM UTC 24 |
| Finished | Sep 24 07:51:44 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492746654 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2492746654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.939696831 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 479979077 ps |
| CPU time | 4.52 seconds |
| Started | Sep 24 07:51:36 PM UTC 24 |
| Finished | Sep 24 07:51:42 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939696831 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.939696831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.120460482 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 133394516 ps |
| CPU time | 4.77 seconds |
| Started | Sep 24 07:51:40 PM UTC 24 |
| Finished | Sep 24 07:51:46 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120460482 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.120460482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.1874799736 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 248213186 ps |
| CPU time | 3.94 seconds |
| Started | Sep 24 07:51:34 PM UTC 24 |
| Finished | Sep 24 07:51:39 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874799736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1874799736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.1976264508 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1010995154 ps |
| CPU time | 14.99 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:52:15 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1976264508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr _stress_all_with_rand_reset.1976264508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.1397441742 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 242005679 ps |
| CPU time | 7.51 seconds |
| Started | Sep 24 07:51:47 PM UTC 24 |
| Finished | Sep 24 07:51:55 PM UTC 24 |
| Peak memory | 219568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397441742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1397441742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.1094361576 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 154533719 ps |
| CPU time | 4 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:52:04 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094361576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1094361576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.829488456 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 37669451 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 07:58:27 PM UTC 24 |
| Finished | Sep 24 07:58:29 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829488456 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.829488456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.1847961052 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 92672361 ps |
| CPU time | 4.98 seconds |
| Started | Sep 24 07:58:22 PM UTC 24 |
| Finished | Sep 24 07:58:28 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847961052 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1847961052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.1217926698 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 85086368 ps |
| CPU time | 5.99 seconds |
| Started | Sep 24 07:58:24 PM UTC 24 |
| Finished | Sep 24 07:58:31 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217926698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1217926698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.4173834154 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 204290865 ps |
| CPU time | 3.9 seconds |
| Started | Sep 24 07:58:22 PM UTC 24 |
| Finished | Sep 24 07:58:27 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173834154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4173834154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.1036088764 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 320967877 ps |
| CPU time | 6.49 seconds |
| Started | Sep 24 07:58:23 PM UTC 24 |
| Finished | Sep 24 07:58:31 PM UTC 24 |
| Peak memory | 231328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036088764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1036088764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.4205680487 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 63088428 ps |
| CPU time | 2.95 seconds |
| Started | Sep 24 07:58:23 PM UTC 24 |
| Finished | Sep 24 07:58:28 PM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205680487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4205680487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.2774459342 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 702961568 ps |
| CPU time | 6.16 seconds |
| Started | Sep 24 07:58:22 PM UTC 24 |
| Finished | Sep 24 07:58:29 PM UTC 24 |
| Peak memory | 223344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774459342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2774459342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_random.3998950422 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 227435570 ps |
| CPU time | 7.88 seconds |
| Started | Sep 24 07:58:21 PM UTC 24 |
| Finished | Sep 24 07:58:30 PM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998950422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3998950422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.1921762773 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 391735592 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 07:58:20 PM UTC 24 |
| Finished | Sep 24 07:58:26 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921762773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1921762773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.694808736 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 55117171 ps |
| CPU time | 3.06 seconds |
| Started | Sep 24 07:58:21 PM UTC 24 |
| Finished | Sep 24 07:58:25 PM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694808736 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.694808736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.1055920165 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 550630778 ps |
| CPU time | 11.57 seconds |
| Started | Sep 24 07:58:20 PM UTC 24 |
| Finished | Sep 24 07:58:32 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055920165 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1055920165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.34377097 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 172920034 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 07:58:21 PM UTC 24 |
| Finished | Sep 24 07:58:27 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34377097 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.34377097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.1827968122 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 30811650 ps |
| CPU time | 3.27 seconds |
| Started | Sep 24 07:58:25 PM UTC 24 |
| Finished | Sep 24 07:58:29 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827968122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1827968122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.1036233696 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 27355816 ps |
| CPU time | 3.29 seconds |
| Started | Sep 24 07:58:19 PM UTC 24 |
| Finished | Sep 24 07:58:23 PM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036233696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1036233696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.42593971 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1112598737 ps |
| CPU time | 44.13 seconds |
| Started | Sep 24 07:58:26 PM UTC 24 |
| Finished | Sep 24 07:59:11 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42593971 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.42593971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.2605781727 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 199473361 ps |
| CPU time | 13.43 seconds |
| Started | Sep 24 07:58:26 PM UTC 24 |
| Finished | Sep 24 07:58:41 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2605781727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.2605781727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.3348252564 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 353813888 ps |
| CPU time | 5.14 seconds |
| Started | Sep 24 07:58:23 PM UTC 24 |
| Finished | Sep 24 07:58:30 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348252564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3348252564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.468061576 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 348512040 ps |
| CPU time | 4.61 seconds |
| Started | Sep 24 07:58:25 PM UTC 24 |
| Finished | Sep 24 07:58:30 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468061576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.468061576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.915507208 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 12172209 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 07:58:33 PM UTC 24 |
| Finished | Sep 24 07:58:36 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915507208 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.915507208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.2891151559 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 123116904 ps |
| CPU time | 4.65 seconds |
| Started | Sep 24 07:58:32 PM UTC 24 |
| Finished | Sep 24 07:58:38 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891151559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2891151559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.1461912830 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 443914547 ps |
| CPU time | 5.32 seconds |
| Started | Sep 24 07:58:30 PM UTC 24 |
| Finished | Sep 24 07:58:37 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461912830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1461912830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.3265109156 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 114531661 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 07:58:31 PM UTC 24 |
| Finished | Sep 24 07:58:37 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265109156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3265109156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.1092160072 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 140092845 ps |
| CPU time | 5.53 seconds |
| Started | Sep 24 07:58:31 PM UTC 24 |
| Finished | Sep 24 07:58:37 PM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092160072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1092160072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_random.1222492959 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 119864036 ps |
| CPU time | 6.89 seconds |
| Started | Sep 24 07:58:29 PM UTC 24 |
| Finished | Sep 24 07:58:38 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222492959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1222492959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.1863000576 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 36170649 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 07:58:28 PM UTC 24 |
| Finished | Sep 24 07:58:33 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863000576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1863000576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.2042617880 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 112741049 ps |
| CPU time | 3.26 seconds |
| Started | Sep 24 07:58:28 PM UTC 24 |
| Finished | Sep 24 07:58:33 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042617880 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2042617880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.2095420636 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 187211342 ps |
| CPU time | 8.84 seconds |
| Started | Sep 24 07:58:28 PM UTC 24 |
| Finished | Sep 24 07:58:38 PM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095420636 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2095420636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.1560087575 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 125251580 ps |
| CPU time | 4.87 seconds |
| Started | Sep 24 07:58:29 PM UTC 24 |
| Finished | Sep 24 07:58:36 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560087575 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1560087575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.90246052 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 103336827 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 07:58:32 PM UTC 24 |
| Finished | Sep 24 07:58:37 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90246052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.90246052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.1433963379 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 74212068 ps |
| CPU time | 3.01 seconds |
| Started | Sep 24 07:58:28 PM UTC 24 |
| Finished | Sep 24 07:58:32 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433963379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1433963379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.3396245849 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 630547392 ps |
| CPU time | 25.13 seconds |
| Started | Sep 24 07:58:33 PM UTC 24 |
| Finished | Sep 24 07:59:00 PM UTC 24 |
| Peak memory | 230772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3396245849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymg r_stress_all_with_rand_reset.3396245849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.3273295218 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 218926531 ps |
| CPU time | 7.39 seconds |
| Started | Sep 24 07:58:31 PM UTC 24 |
| Finished | Sep 24 07:58:39 PM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273295218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3273295218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.729625574 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 405726715 ps |
| CPU time | 3.98 seconds |
| Started | Sep 24 07:58:32 PM UTC 24 |
| Finished | Sep 24 07:58:37 PM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729625574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.729625574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.4191817310 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 11616438 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 07:58:41 PM UTC 24 |
| Finished | Sep 24 07:58:44 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191817310 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4191817310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.1749028956 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 46207028 ps |
| CPU time | 3.57 seconds |
| Started | Sep 24 07:58:38 PM UTC 24 |
| Finished | Sep 24 07:58:42 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749028956 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1749028956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.3589135717 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 120321387 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 07:58:39 PM UTC 24 |
| Finished | Sep 24 07:58:45 PM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589135717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3589135717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.621048865 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2268987427 ps |
| CPU time | 17.22 seconds |
| Started | Sep 24 07:58:38 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 217388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621048865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.621048865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.1868615445 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 958665484 ps |
| CPU time | 4.74 seconds |
| Started | Sep 24 07:58:39 PM UTC 24 |
| Finished | Sep 24 07:58:45 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868615445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1868615445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.965123270 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 35586022 ps |
| CPU time | 2.92 seconds |
| Started | Sep 24 07:58:39 PM UTC 24 |
| Finished | Sep 24 07:58:43 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965123270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.965123270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.1617497522 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 58070567 ps |
| CPU time | 3.84 seconds |
| Started | Sep 24 07:58:38 PM UTC 24 |
| Finished | Sep 24 07:58:43 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617497522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1617497522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_random.2308329834 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 315664727 ps |
| CPU time | 12.08 seconds |
| Started | Sep 24 07:58:37 PM UTC 24 |
| Finished | Sep 24 07:58:50 PM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308329834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2308329834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.3322652611 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 48984658 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 07:58:33 PM UTC 24 |
| Finished | Sep 24 07:58:37 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322652611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3322652611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.1586434528 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 382621753 ps |
| CPU time | 8.85 seconds |
| Started | Sep 24 07:58:34 PM UTC 24 |
| Finished | Sep 24 07:58:45 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586434528 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1586434528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.1921318648 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 622788358 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 07:58:33 PM UTC 24 |
| Finished | Sep 24 07:58:39 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921318648 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1921318648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.2739485547 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 158281081 ps |
| CPU time | 4.62 seconds |
| Started | Sep 24 07:58:36 PM UTC 24 |
| Finished | Sep 24 07:58:42 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739485547 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2739485547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.3418711950 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 54088029 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 07:58:39 PM UTC 24 |
| Finished | Sep 24 07:58:44 PM UTC 24 |
| Peak memory | 217472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418711950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3418711950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.1004625724 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 521289135 ps |
| CPU time | 5.92 seconds |
| Started | Sep 24 07:58:33 PM UTC 24 |
| Finished | Sep 24 07:58:40 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004625724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1004625724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.1066299885 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3402523085 ps |
| CPU time | 26.33 seconds |
| Started | Sep 24 07:58:40 PM UTC 24 |
| Finished | Sep 24 07:59:08 PM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066299885 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1066299885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.1227626674 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 110794520 ps |
| CPU time | 8.71 seconds |
| Started | Sep 24 07:58:40 PM UTC 24 |
| Finished | Sep 24 07:58:50 PM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1227626674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg r_stress_all_with_rand_reset.1227626674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.2306493241 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 444499335 ps |
| CPU time | 8.1 seconds |
| Started | Sep 24 07:58:38 PM UTC 24 |
| Finished | Sep 24 07:58:47 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306493241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2306493241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.790568578 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 115841634 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 07:58:39 PM UTC 24 |
| Finished | Sep 24 07:58:43 PM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790568578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.790568578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.4075531729 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 15940528 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 07:58:51 PM UTC 24 |
| Finished | Sep 24 07:58:53 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075531729 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4075531729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.2019039190 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 297207738 ps |
| CPU time | 10.61 seconds |
| Started | Sep 24 07:58:44 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019039190 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2019039190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.4236987934 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 98071338 ps |
| CPU time | 6.2 seconds |
| Started | Sep 24 07:58:48 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236987934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4236987934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.3237228654 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 54036759 ps |
| CPU time | 4.08 seconds |
| Started | Sep 24 07:58:45 PM UTC 24 |
| Finished | Sep 24 07:58:50 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237228654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3237228654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.2912331668 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 57200055 ps |
| CPU time | 3.17 seconds |
| Started | Sep 24 07:58:46 PM UTC 24 |
| Finished | Sep 24 07:58:51 PM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912331668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2912331668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.823497322 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 51768493 ps |
| CPU time | 4.1 seconds |
| Started | Sep 24 07:58:46 PM UTC 24 |
| Finished | Sep 24 07:58:51 PM UTC 24 |
| Peak memory | 230816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823497322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.823497322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.120549876 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 332369550 ps |
| CPU time | 4.78 seconds |
| Started | Sep 24 07:58:45 PM UTC 24 |
| Finished | Sep 24 07:58:51 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120549876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.120549876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_random.1720603877 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 287085429 ps |
| CPU time | 5.63 seconds |
| Started | Sep 24 07:58:44 PM UTC 24 |
| Finished | Sep 24 07:58:51 PM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720603877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1720603877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.2386330313 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 63480403 ps |
| CPU time | 4.75 seconds |
| Started | Sep 24 07:58:43 PM UTC 24 |
| Finished | Sep 24 07:58:49 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386330313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2386330313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.3439398031 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 147735870 ps |
| CPU time | 6.12 seconds |
| Started | Sep 24 07:58:44 PM UTC 24 |
| Finished | Sep 24 07:58:51 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439398031 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3439398031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.704437060 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 218686150 ps |
| CPU time | 4.35 seconds |
| Started | Sep 24 07:58:43 PM UTC 24 |
| Finished | Sep 24 07:58:48 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704437060 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.704437060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.2931918676 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 307598046 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 07:58:44 PM UTC 24 |
| Finished | Sep 24 07:58:49 PM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931918676 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2931918676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.3270933305 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 77661080 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 07:58:48 PM UTC 24 |
| Finished | Sep 24 07:58:52 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270933305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3270933305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.2614695452 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 639028794 ps |
| CPU time | 4.69 seconds |
| Started | Sep 24 07:58:41 PM UTC 24 |
| Finished | Sep 24 07:58:48 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614695452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2614695452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.3734219243 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 519056400 ps |
| CPU time | 22.38 seconds |
| Started | Sep 24 07:58:50 PM UTC 24 |
| Finished | Sep 24 07:59:13 PM UTC 24 |
| Peak memory | 231536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734219243 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3734219243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.2812205040 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1527609961 ps |
| CPU time | 17.57 seconds |
| Started | Sep 24 07:58:50 PM UTC 24 |
| Finished | Sep 24 07:59:09 PM UTC 24 |
| Peak memory | 230212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2812205040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymg r_stress_all_with_rand_reset.2812205040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.443287225 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 265877989 ps |
| CPU time | 10.49 seconds |
| Started | Sep 24 07:58:46 PM UTC 24 |
| Finished | Sep 24 07:58:58 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443287225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.443287225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.687200362 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 317788476 ps |
| CPU time | 5.1 seconds |
| Started | Sep 24 07:58:50 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687200362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.687200362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.1159289123 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 14169665 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 07:58:58 PM UTC 24 |
| Finished | Sep 24 07:59:01 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159289123 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1159289123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.4138559479 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4220813877 ps |
| CPU time | 29.32 seconds |
| Started | Sep 24 07:58:52 PM UTC 24 |
| Finished | Sep 24 07:59:23 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138559479 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4138559479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.549235749 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 57344838 ps |
| CPU time | 4.25 seconds |
| Started | Sep 24 07:58:57 PM UTC 24 |
| Finished | Sep 24 07:59:02 PM UTC 24 |
| Peak memory | 217864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549235749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.549235749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.717896647 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 135778357 ps |
| CPU time | 3.06 seconds |
| Started | Sep 24 07:58:52 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717896647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.717896647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.4013601007 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 992885212 ps |
| CPU time | 5.28 seconds |
| Started | Sep 24 07:58:54 PM UTC 24 |
| Finished | Sep 24 07:59:00 PM UTC 24 |
| Peak memory | 217220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013601007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4013601007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.2354063488 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 134233241 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 07:58:57 PM UTC 24 |
| Finished | Sep 24 07:59:03 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354063488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2354063488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.520759055 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 111496264 ps |
| CPU time | 7.03 seconds |
| Started | Sep 24 07:58:52 PM UTC 24 |
| Finished | Sep 24 07:59:01 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520759055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.520759055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_random.1291468080 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 7417860766 ps |
| CPU time | 24.6 seconds |
| Started | Sep 24 07:58:52 PM UTC 24 |
| Finished | Sep 24 07:59:18 PM UTC 24 |
| Peak memory | 223748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291468080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1291468080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.617999668 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 171512088 ps |
| CPU time | 3.38 seconds |
| Started | Sep 24 07:58:51 PM UTC 24 |
| Finished | Sep 24 07:58:55 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617999668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.617999668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.422041422 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 674927011 ps |
| CPU time | 9.36 seconds |
| Started | Sep 24 07:58:52 PM UTC 24 |
| Finished | Sep 24 07:59:03 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422041422 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.422041422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.316516302 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 260937761 ps |
| CPU time | 4.93 seconds |
| Started | Sep 24 07:58:51 PM UTC 24 |
| Finished | Sep 24 07:58:57 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316516302 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.316516302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.2211941319 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2246187676 ps |
| CPU time | 20.32 seconds |
| Started | Sep 24 07:58:52 PM UTC 24 |
| Finished | Sep 24 07:59:14 PM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211941319 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2211941319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1610909105 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 35510668 ps |
| CPU time | 2.76 seconds |
| Started | Sep 24 07:58:57 PM UTC 24 |
| Finished | Sep 24 07:59:01 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610909105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1610909105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.1274282829 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 92771756 ps |
| CPU time | 3.81 seconds |
| Started | Sep 24 07:58:51 PM UTC 24 |
| Finished | Sep 24 07:58:56 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274282829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1274282829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.3073551959 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 5933455741 ps |
| CPU time | 156.2 seconds |
| Started | Sep 24 07:58:57 PM UTC 24 |
| Finished | Sep 24 08:01:36 PM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073551959 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3073551959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.2177698890 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 254930023 ps |
| CPU time | 8.43 seconds |
| Started | Sep 24 07:58:53 PM UTC 24 |
| Finished | Sep 24 07:59:03 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177698890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2177698890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.2176716159 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 93070321 ps |
| CPU time | 2.72 seconds |
| Started | Sep 24 07:58:57 PM UTC 24 |
| Finished | Sep 24 07:59:01 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176716159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2176716159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.2996107327 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 13958199 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 07:59:06 PM UTC 24 |
| Finished | Sep 24 07:59:08 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996107327 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2996107327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.2522325861 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 37724161 ps |
| CPU time | 4.5 seconds |
| Started | Sep 24 07:59:02 PM UTC 24 |
| Finished | Sep 24 07:59:07 PM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522325861 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2522325861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.1005213151 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 147071287 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 07:59:03 PM UTC 24 |
| Finished | Sep 24 07:59:09 PM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005213151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1005213151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.2861842333 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 735836471 ps |
| CPU time | 4.66 seconds |
| Started | Sep 24 07:59:02 PM UTC 24 |
| Finished | Sep 24 07:59:08 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861842333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2861842333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.2673619569 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 57901386 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 07:59:03 PM UTC 24 |
| Finished | Sep 24 07:59:06 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673619569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2673619569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.3133275751 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 231863068 ps |
| CPU time | 2.93 seconds |
| Started | Sep 24 07:59:03 PM UTC 24 |
| Finished | Sep 24 07:59:07 PM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133275751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3133275751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.1177951557 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 182102651 ps |
| CPU time | 4.38 seconds |
| Started | Sep 24 07:59:02 PM UTC 24 |
| Finished | Sep 24 07:59:07 PM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177951557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1177951557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_random.3254022373 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 91629132 ps |
| CPU time | 6.41 seconds |
| Started | Sep 24 07:59:02 PM UTC 24 |
| Finished | Sep 24 07:59:09 PM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254022373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3254022373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.2994082038 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 135789583 ps |
| CPU time | 7.51 seconds |
| Started | Sep 24 07:58:58 PM UTC 24 |
| Finished | Sep 24 07:59:07 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994082038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2994082038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.1137373154 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 47480917 ps |
| CPU time | 3.01 seconds |
| Started | Sep 24 07:59:00 PM UTC 24 |
| Finished | Sep 24 07:59:05 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137373154 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1137373154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.2144079045 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 25457796 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 07:58:59 PM UTC 24 |
| Finished | Sep 24 07:59:03 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144079045 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2144079045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.2078543208 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 71332869 ps |
| CPU time | 3.4 seconds |
| Started | Sep 24 07:59:01 PM UTC 24 |
| Finished | Sep 24 07:59:05 PM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078543208 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2078543208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.658155744 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 118371549 ps |
| CPU time | 3.99 seconds |
| Started | Sep 24 07:59:04 PM UTC 24 |
| Finished | Sep 24 07:59:09 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658155744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.658155744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.1783471836 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 458238806 ps |
| CPU time | 5.6 seconds |
| Started | Sep 24 07:58:58 PM UTC 24 |
| Finished | Sep 24 07:59:05 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783471836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1783471836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.1714430962 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 634984228 ps |
| CPU time | 21.74 seconds |
| Started | Sep 24 07:59:04 PM UTC 24 |
| Finished | Sep 24 07:59:27 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714430962 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1714430962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.1570928931 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 190780769 ps |
| CPU time | 6.23 seconds |
| Started | Sep 24 07:59:03 PM UTC 24 |
| Finished | Sep 24 07:59:10 PM UTC 24 |
| Peak memory | 219304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570928931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1570928931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.88829549 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 104420135 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 07:59:04 PM UTC 24 |
| Finished | Sep 24 07:59:09 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88829549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.88829549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.400532786 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 79444991 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 07:59:12 PM UTC 24 |
| Finished | Sep 24 07:59:14 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400532786 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.400532786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.1197096609 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 171925426 ps |
| CPU time | 5.07 seconds |
| Started | Sep 24 07:59:08 PM UTC 24 |
| Finished | Sep 24 07:59:14 PM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197096609 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1197096609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.2214622864 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 49036854 ps |
| CPU time | 1.95 seconds |
| Started | Sep 24 07:59:10 PM UTC 24 |
| Finished | Sep 24 07:59:13 PM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214622864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2214622864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.2514073384 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 27907807 ps |
| CPU time | 2.1 seconds |
| Started | Sep 24 07:59:09 PM UTC 24 |
| Finished | Sep 24 07:59:12 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514073384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2514073384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.3194926659 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 241660391 ps |
| CPU time | 9.07 seconds |
| Started | Sep 24 07:59:09 PM UTC 24 |
| Finished | Sep 24 07:59:19 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194926659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3194926659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.1564291587 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 283620049 ps |
| CPU time | 4.58 seconds |
| Started | Sep 24 07:59:10 PM UTC 24 |
| Finished | Sep 24 07:59:16 PM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564291587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1564291587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.1084068080 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 65226254 ps |
| CPU time | 3.73 seconds |
| Started | Sep 24 07:59:09 PM UTC 24 |
| Finished | Sep 24 07:59:14 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084068080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1084068080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_random.3196520036 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 494566389 ps |
| CPU time | 5.75 seconds |
| Started | Sep 24 07:59:08 PM UTC 24 |
| Finished | Sep 24 07:59:15 PM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196520036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3196520036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.928199223 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 460718902 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 07:59:07 PM UTC 24 |
| Finished | Sep 24 07:59:12 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928199223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.928199223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.1987377657 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 978782485 ps |
| CPU time | 19.76 seconds |
| Started | Sep 24 07:59:08 PM UTC 24 |
| Finished | Sep 24 07:59:29 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987377657 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1987377657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.2242704719 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 34553920 ps |
| CPU time | 2.68 seconds |
| Started | Sep 24 07:59:07 PM UTC 24 |
| Finished | Sep 24 07:59:10 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242704719 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2242704719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.1325644875 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3356093925 ps |
| CPU time | 47.2 seconds |
| Started | Sep 24 07:59:08 PM UTC 24 |
| Finished | Sep 24 07:59:57 PM UTC 24 |
| Peak memory | 217388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325644875 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1325644875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.2285379191 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 22445129 ps |
| CPU time | 2.48 seconds |
| Started | Sep 24 07:59:11 PM UTC 24 |
| Finished | Sep 24 07:59:14 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285379191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2285379191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.623947400 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 73677410 ps |
| CPU time | 3.46 seconds |
| Started | Sep 24 07:59:06 PM UTC 24 |
| Finished | Sep 24 07:59:10 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623947400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.623947400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.1467057761 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1138723652 ps |
| CPU time | 14.27 seconds |
| Started | Sep 24 07:59:11 PM UTC 24 |
| Finished | Sep 24 07:59:26 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467057761 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1467057761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.1573828098 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 173623411 ps |
| CPU time | 5.93 seconds |
| Started | Sep 24 07:59:09 PM UTC 24 |
| Finished | Sep 24 07:59:16 PM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573828098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1573828098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.1631183438 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 175640349 ps |
| CPU time | 3.85 seconds |
| Started | Sep 24 07:59:11 PM UTC 24 |
| Finished | Sep 24 07:59:15 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631183438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1631183438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.1716792197 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 19450778 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 07:59:17 PM UTC 24 |
| Finished | Sep 24 07:59:19 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716792197 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1716792197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.1853792671 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 126964856 ps |
| CPU time | 2.98 seconds |
| Started | Sep 24 07:59:14 PM UTC 24 |
| Finished | Sep 24 07:59:18 PM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853792671 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1853792671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.4104955700 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 81118964 ps |
| CPU time | 2.98 seconds |
| Started | Sep 24 07:59:16 PM UTC 24 |
| Finished | Sep 24 07:59:20 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104955700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4104955700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.1548974865 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 241240767 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 07:59:14 PM UTC 24 |
| Finished | Sep 24 07:59:19 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548974865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1548974865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.3251298860 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 667872241 ps |
| CPU time | 6.11 seconds |
| Started | Sep 24 07:59:16 PM UTC 24 |
| Finished | Sep 24 07:59:23 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251298860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3251298860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.3060430175 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 96470851 ps |
| CPU time | 6.15 seconds |
| Started | Sep 24 07:59:15 PM UTC 24 |
| Finished | Sep 24 07:59:22 PM UTC 24 |
| Peak memory | 217484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060430175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3060430175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_random.638163161 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 312410135 ps |
| CPU time | 4.95 seconds |
| Started | Sep 24 07:59:14 PM UTC 24 |
| Finished | Sep 24 07:59:20 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638163161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.638163161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.226988343 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 56581388 ps |
| CPU time | 3.56 seconds |
| Started | Sep 24 07:59:12 PM UTC 24 |
| Finished | Sep 24 07:59:17 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226988343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.226988343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.3619709635 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 152858729 ps |
| CPU time | 4.8 seconds |
| Started | Sep 24 07:59:13 PM UTC 24 |
| Finished | Sep 24 07:59:19 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619709635 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3619709635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.27386160 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 830112700 ps |
| CPU time | 9.52 seconds |
| Started | Sep 24 07:59:13 PM UTC 24 |
| Finished | Sep 24 07:59:24 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27386160 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.27386160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.2145869863 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 905085200 ps |
| CPU time | 5.17 seconds |
| Started | Sep 24 07:59:13 PM UTC 24 |
| Finished | Sep 24 07:59:19 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145869863 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2145869863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.1466246569 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 47715707 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 07:59:17 PM UTC 24 |
| Finished | Sep 24 07:59:21 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466246569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1466246569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.647478359 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 148391706 ps |
| CPU time | 4.75 seconds |
| Started | Sep 24 07:59:12 PM UTC 24 |
| Finished | Sep 24 07:59:18 PM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647478359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.647478359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.2499800092 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 254369283 ps |
| CPU time | 7.12 seconds |
| Started | Sep 24 07:59:16 PM UTC 24 |
| Finished | Sep 24 07:59:24 PM UTC 24 |
| Peak memory | 217416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499800092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2499800092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.167493726 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 85864205 ps |
| CPU time | 2.3 seconds |
| Started | Sep 24 07:59:17 PM UTC 24 |
| Finished | Sep 24 07:59:20 PM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167493726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.167493726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.3871420666 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 10546001 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 07:59:25 PM UTC 24 |
| Finished | Sep 24 07:59:27 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871420666 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3871420666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.3699268523 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 120585357 ps |
| CPU time | 9.09 seconds |
| Started | Sep 24 07:59:22 PM UTC 24 |
| Finished | Sep 24 07:59:33 PM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699268523 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3699268523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.1635339283 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 272572901 ps |
| CPU time | 7.8 seconds |
| Started | Sep 24 07:59:23 PM UTC 24 |
| Finished | Sep 24 07:59:32 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635339283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1635339283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.3544818208 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2515284680 ps |
| CPU time | 16.6 seconds |
| Started | Sep 24 07:59:22 PM UTC 24 |
| Finished | Sep 24 07:59:40 PM UTC 24 |
| Peak memory | 223816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544818208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3544818208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.3899456810 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 493165909 ps |
| CPU time | 11.48 seconds |
| Started | Sep 24 07:59:23 PM UTC 24 |
| Finished | Sep 24 07:59:35 PM UTC 24 |
| Peak memory | 223348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899456810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3899456810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.4226025652 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 345798198 ps |
| CPU time | 5.19 seconds |
| Started | Sep 24 07:59:23 PM UTC 24 |
| Finished | Sep 24 07:59:29 PM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226025652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4226025652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_random.138911131 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 150687511 ps |
| CPU time | 4.02 seconds |
| Started | Sep 24 07:59:22 PM UTC 24 |
| Finished | Sep 24 07:59:27 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138911131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.138911131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.3892946081 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 75225924 ps |
| CPU time | 4.58 seconds |
| Started | Sep 24 07:59:19 PM UTC 24 |
| Finished | Sep 24 07:59:25 PM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892946081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3892946081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.1338719586 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 226080864 ps |
| CPU time | 4.31 seconds |
| Started | Sep 24 07:59:19 PM UTC 24 |
| Finished | Sep 24 07:59:25 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338719586 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1338719586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.2783354092 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 266013332 ps |
| CPU time | 6.74 seconds |
| Started | Sep 24 07:59:19 PM UTC 24 |
| Finished | Sep 24 07:59:27 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783354092 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2783354092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.2605070211 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 691916765 ps |
| CPU time | 4.82 seconds |
| Started | Sep 24 07:59:22 PM UTC 24 |
| Finished | Sep 24 07:59:28 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605070211 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2605070211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.1671367140 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 176253976 ps |
| CPU time | 6.62 seconds |
| Started | Sep 24 07:59:23 PM UTC 24 |
| Finished | Sep 24 07:59:31 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671367140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1671367140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.1203248268 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 155100409 ps |
| CPU time | 6.8 seconds |
| Started | Sep 24 07:59:18 PM UTC 24 |
| Finished | Sep 24 07:59:26 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203248268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1203248268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1395370312 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 733970831 ps |
| CPU time | 22.19 seconds |
| Started | Sep 24 07:59:24 PM UTC 24 |
| Finished | Sep 24 07:59:47 PM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395370312 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1395370312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.2547817318 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 170758645 ps |
| CPU time | 11.16 seconds |
| Started | Sep 24 07:59:24 PM UTC 24 |
| Finished | Sep 24 07:59:36 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2547817318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg r_stress_all_with_rand_reset.2547817318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.2763845473 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 1280077538 ps |
| CPU time | 12.61 seconds |
| Started | Sep 24 07:59:23 PM UTC 24 |
| Finished | Sep 24 07:59:36 PM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763845473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2763845473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.1015793373 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 38831355 ps |
| CPU time | 2.02 seconds |
| Started | Sep 24 07:59:23 PM UTC 24 |
| Finished | Sep 24 07:59:26 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015793373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1015793373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.1759327033 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 10559668 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 07:59:31 PM UTC 24 |
| Finished | Sep 24 07:59:33 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759327033 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1759327033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.2317032910 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 119930229 ps |
| CPU time | 7.3 seconds |
| Started | Sep 24 07:59:30 PM UTC 24 |
| Finished | Sep 24 07:59:39 PM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317032910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2317032910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.2653917199 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 77547120 ps |
| CPU time | 3.76 seconds |
| Started | Sep 24 07:59:29 PM UTC 24 |
| Finished | Sep 24 07:59:34 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653917199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2653917199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.3494208534 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 127179513 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 07:59:29 PM UTC 24 |
| Finished | Sep 24 07:59:32 PM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494208534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3494208534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_random.930604761 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 721447921 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 07:59:28 PM UTC 24 |
| Finished | Sep 24 07:59:34 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930604761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.930604761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.485027241 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 64593386 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 07:59:26 PM UTC 24 |
| Finished | Sep 24 07:59:30 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485027241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.485027241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.4252137454 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 36663842 ps |
| CPU time | 3.01 seconds |
| Started | Sep 24 07:59:27 PM UTC 24 |
| Finished | Sep 24 07:59:31 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252137454 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4252137454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.1361138096 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 122579788 ps |
| CPU time | 2.99 seconds |
| Started | Sep 24 07:59:26 PM UTC 24 |
| Finished | Sep 24 07:59:30 PM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361138096 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1361138096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.2599593449 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 211209648 ps |
| CPU time | 4.03 seconds |
| Started | Sep 24 07:59:27 PM UTC 24 |
| Finished | Sep 24 07:59:33 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599593449 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2599593449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.2499355111 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 60315759 ps |
| CPU time | 2.72 seconds |
| Started | Sep 24 07:59:30 PM UTC 24 |
| Finished | Sep 24 07:59:34 PM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499355111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2499355111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.2927372483 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 48631350 ps |
| CPU time | 2.86 seconds |
| Started | Sep 24 07:59:25 PM UTC 24 |
| Finished | Sep 24 07:59:29 PM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927372483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2927372483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.261407504 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 3455862825 ps |
| CPU time | 31.09 seconds |
| Started | Sep 24 07:59:31 PM UTC 24 |
| Finished | Sep 24 08:00:04 PM UTC 24 |
| Peak memory | 227772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261407504 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.261407504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.861036113 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1362070706 ps |
| CPU time | 18.16 seconds |
| Started | Sep 24 07:59:31 PM UTC 24 |
| Finished | Sep 24 07:59:51 PM UTC 24 |
| Peak memory | 231752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=861036113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr _stress_all_with_rand_reset.861036113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.2929026548 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 185183384 ps |
| CPU time | 3.56 seconds |
| Started | Sep 24 07:59:29 PM UTC 24 |
| Finished | Sep 24 07:59:33 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929026548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2929026548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.3931410441 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 125840214 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 07:59:30 PM UTC 24 |
| Finished | Sep 24 07:59:34 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931410441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3931410441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.3557427744 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 8568974 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 07:52:17 PM UTC 24 |
| Finished | Sep 24 07:52:19 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557427744 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3557427744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.3672413002 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 45108413 ps |
| CPU time | 3.03 seconds |
| Started | Sep 24 07:52:07 PM UTC 24 |
| Finished | Sep 24 07:52:11 PM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672413002 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3672413002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.4017176944 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 989788550 ps |
| CPU time | 3.24 seconds |
| Started | Sep 24 07:52:13 PM UTC 24 |
| Finished | Sep 24 07:52:18 PM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017176944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4017176944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.3541902728 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 275240601 ps |
| CPU time | 3.79 seconds |
| Started | Sep 24 07:52:07 PM UTC 24 |
| Finished | Sep 24 07:52:12 PM UTC 24 |
| Peak memory | 217284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541902728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3541902728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_random.353674355 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 896140020 ps |
| CPU time | 9.11 seconds |
| Started | Sep 24 07:52:04 PM UTC 24 |
| Finished | Sep 24 07:52:15 PM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353674355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.353674355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.1718664328 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 93199819 ps |
| CPU time | 6.13 seconds |
| Started | Sep 24 07:52:02 PM UTC 24 |
| Finished | Sep 24 07:52:09 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718664328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1718664328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.3719690575 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 643407739 ps |
| CPU time | 9.82 seconds |
| Started | Sep 24 07:52:04 PM UTC 24 |
| Finished | Sep 24 07:52:15 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719690575 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3719690575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.1122544717 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 129968092 ps |
| CPU time | 3.08 seconds |
| Started | Sep 24 07:52:02 PM UTC 24 |
| Finished | Sep 24 07:52:06 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122544717 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1122544717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.816099554 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2794949788 ps |
| CPU time | 11.16 seconds |
| Started | Sep 24 07:52:04 PM UTC 24 |
| Finished | Sep 24 07:52:17 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816099554 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.816099554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.4029436973 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3922634326 ps |
| CPU time | 39.69 seconds |
| Started | Sep 24 07:52:13 PM UTC 24 |
| Finished | Sep 24 07:52:55 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029436973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4029436973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.761732558 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 362558036 ps |
| CPU time | 4.2 seconds |
| Started | Sep 24 07:51:59 PM UTC 24 |
| Finished | Sep 24 07:52:05 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761732558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.761732558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.1907677869 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 338162037 ps |
| CPU time | 5.96 seconds |
| Started | Sep 24 07:52:10 PM UTC 24 |
| Finished | Sep 24 07:52:18 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907677869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1907677869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.3151684502 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 129637732 ps |
| CPU time | 4.18 seconds |
| Started | Sep 24 07:52:13 PM UTC 24 |
| Finished | Sep 24 07:52:19 PM UTC 24 |
| Peak memory | 219384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151684502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3151684502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.3863274605 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 13026749 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 07:52:31 PM UTC 24 |
| Finished | Sep 24 07:52:34 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863274605 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3863274605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.1344580793 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 52858481 ps |
| CPU time | 5.25 seconds |
| Started | Sep 24 07:52:20 PM UTC 24 |
| Finished | Sep 24 07:52:27 PM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344580793 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1344580793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.2726127736 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 427735965 ps |
| CPU time | 10.81 seconds |
| Started | Sep 24 07:52:25 PM UTC 24 |
| Finished | Sep 24 07:52:37 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726127736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2726127736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.98537058 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 79844770 ps |
| CPU time | 2.85 seconds |
| Started | Sep 24 07:52:20 PM UTC 24 |
| Finished | Sep 24 07:52:24 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98537058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.98537058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.3498220744 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 69492483 ps |
| CPU time | 2.37 seconds |
| Started | Sep 24 07:52:25 PM UTC 24 |
| Finished | Sep 24 07:52:29 PM UTC 24 |
| Peak memory | 230216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498220744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3498220744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.3873926870 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 78942209 ps |
| CPU time | 2.68 seconds |
| Started | Sep 24 07:52:24 PM UTC 24 |
| Finished | Sep 24 07:52:28 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873926870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3873926870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_random.972398217 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 315892569 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 07:52:19 PM UTC 24 |
| Finished | Sep 24 07:52:25 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972398217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.972398217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.3408474026 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 283080028 ps |
| CPU time | 5.19 seconds |
| Started | Sep 24 07:52:18 PM UTC 24 |
| Finished | Sep 24 07:52:24 PM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408474026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3408474026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.1534021083 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 237499381 ps |
| CPU time | 10.46 seconds |
| Started | Sep 24 07:52:19 PM UTC 24 |
| Finished | Sep 24 07:52:31 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534021083 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1534021083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.3375854037 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 99854130 ps |
| CPU time | 3.93 seconds |
| Started | Sep 24 07:52:18 PM UTC 24 |
| Finished | Sep 24 07:52:23 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375854037 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3375854037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.439961626 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 10358409819 ps |
| CPU time | 73.25 seconds |
| Started | Sep 24 07:52:19 PM UTC 24 |
| Finished | Sep 24 07:53:34 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439961626 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.439961626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.4063487918 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 32347105 ps |
| CPU time | 2.86 seconds |
| Started | Sep 24 07:52:25 PM UTC 24 |
| Finished | Sep 24 07:52:29 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063487918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4063487918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.475401665 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 161832980 ps |
| CPU time | 6.1 seconds |
| Started | Sep 24 07:52:17 PM UTC 24 |
| Finished | Sep 24 07:52:24 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475401665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.475401665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.1422092331 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 26723535201 ps |
| CPU time | 339.1 seconds |
| Started | Sep 24 07:52:29 PM UTC 24 |
| Finished | Sep 24 07:58:13 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422092331 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1422092331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.2341848353 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 98617193 ps |
| CPU time | 7.36 seconds |
| Started | Sep 24 07:52:24 PM UTC 24 |
| Finished | Sep 24 07:52:33 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341848353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2341848353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.2616636456 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1575583162 ps |
| CPU time | 17.54 seconds |
| Started | Sep 24 07:52:28 PM UTC 24 |
| Finished | Sep 24 07:52:46 PM UTC 24 |
| Peak memory | 219576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616636456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2616636456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.2245451158 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 16856789 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 07:52:51 PM UTC 24 |
| Finished | Sep 24 07:52:53 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245451158 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2245451158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.2081429651 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 71368471 ps |
| CPU time | 5.04 seconds |
| Started | Sep 24 07:52:38 PM UTC 24 |
| Finished | Sep 24 07:52:44 PM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081429651 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2081429651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.2076062484 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 65530260 ps |
| CPU time | 4.06 seconds |
| Started | Sep 24 07:52:39 PM UTC 24 |
| Finished | Sep 24 07:52:45 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076062484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2076062484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.2709417684 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 33091913 ps |
| CPU time | 3.65 seconds |
| Started | Sep 24 07:52:46 PM UTC 24 |
| Finished | Sep 24 07:52:50 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709417684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2709417684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.1467790805 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 55316365 ps |
| CPU time | 4.36 seconds |
| Started | Sep 24 07:52:46 PM UTC 24 |
| Finished | Sep 24 07:52:51 PM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467790805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1467790805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.2445860715 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 155321416 ps |
| CPU time | 5.58 seconds |
| Started | Sep 24 07:52:41 PM UTC 24 |
| Finished | Sep 24 07:52:47 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445860715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2445860715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_random.1836330799 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 624552796 ps |
| CPU time | 9.21 seconds |
| Started | Sep 24 07:52:38 PM UTC 24 |
| Finished | Sep 24 07:52:49 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836330799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1836330799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.2398465046 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 54215723 ps |
| CPU time | 3.64 seconds |
| Started | Sep 24 07:52:32 PM UTC 24 |
| Finished | Sep 24 07:52:37 PM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398465046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2398465046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.303258394 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 311123391 ps |
| CPU time | 10.13 seconds |
| Started | Sep 24 07:52:33 PM UTC 24 |
| Finished | Sep 24 07:52:45 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303258394 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.303258394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.1118112850 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 702144462 ps |
| CPU time | 33.45 seconds |
| Started | Sep 24 07:52:33 PM UTC 24 |
| Finished | Sep 24 07:53:08 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118112850 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1118112850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.1841947918 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 305461288 ps |
| CPU time | 5.97 seconds |
| Started | Sep 24 07:52:34 PM UTC 24 |
| Finished | Sep 24 07:52:41 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841947918 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1841947918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.1886183053 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 26162442 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 07:52:47 PM UTC 24 |
| Finished | Sep 24 07:52:51 PM UTC 24 |
| Peak memory | 223424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886183053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1886183053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.266958166 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 655377883 ps |
| CPU time | 5.01 seconds |
| Started | Sep 24 07:52:32 PM UTC 24 |
| Finished | Sep 24 07:52:39 PM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266958166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.266958166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.3524979336 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 84797291 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 07:52:49 PM UTC 24 |
| Finished | Sep 24 07:52:53 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524979336 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3524979336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2790898777 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 359666608 ps |
| CPU time | 6.39 seconds |
| Started | Sep 24 07:52:43 PM UTC 24 |
| Finished | Sep 24 07:52:50 PM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790898777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2790898777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.1242034349 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 26344799 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 07:53:07 PM UTC 24 |
| Finished | Sep 24 07:53:09 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242034349 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1242034349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.2533721852 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 378465651 ps |
| CPU time | 3.89 seconds |
| Started | Sep 24 07:53:02 PM UTC 24 |
| Finished | Sep 24 07:53:07 PM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533721852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2533721852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.713663831 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 42452170 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 07:52:57 PM UTC 24 |
| Finished | Sep 24 07:53:01 PM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713663831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.713663831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.2218339805 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 144372880 ps |
| CPU time | 4.26 seconds |
| Started | Sep 24 07:53:01 PM UTC 24 |
| Finished | Sep 24 07:53:06 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218339805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2218339805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1435227525 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 334124969 ps |
| CPU time | 3.8 seconds |
| Started | Sep 24 07:53:02 PM UTC 24 |
| Finished | Sep 24 07:53:07 PM UTC 24 |
| Peak memory | 230432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435227525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1435227525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.3698956569 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 222036872 ps |
| CPU time | 5.59 seconds |
| Started | Sep 24 07:52:58 PM UTC 24 |
| Finished | Sep 24 07:53:05 PM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698956569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3698956569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_random.3572673831 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 371204106 ps |
| CPU time | 7.08 seconds |
| Started | Sep 24 07:52:55 PM UTC 24 |
| Finished | Sep 24 07:53:03 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572673831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3572673831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.1824208911 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 135846445 ps |
| CPU time | 5.54 seconds |
| Started | Sep 24 07:52:52 PM UTC 24 |
| Finished | Sep 24 07:52:59 PM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824208911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1824208911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.1875771178 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 344322089 ps |
| CPU time | 5.64 seconds |
| Started | Sep 24 07:52:54 PM UTC 24 |
| Finished | Sep 24 07:53:00 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875771178 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1875771178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.2617010552 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 151407046 ps |
| CPU time | 8.22 seconds |
| Started | Sep 24 07:52:52 PM UTC 24 |
| Finished | Sep 24 07:53:02 PM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617010552 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2617010552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.3569049750 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 152517878 ps |
| CPU time | 6.82 seconds |
| Started | Sep 24 07:52:55 PM UTC 24 |
| Finished | Sep 24 07:53:03 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569049750 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3569049750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3259806487 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 88063743 ps |
| CPU time | 2.89 seconds |
| Started | Sep 24 07:53:03 PM UTC 24 |
| Finished | Sep 24 07:53:07 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259806487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3259806487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1011346058 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 165881204 ps |
| CPU time | 3.34 seconds |
| Started | Sep 24 07:52:52 PM UTC 24 |
| Finished | Sep 24 07:52:57 PM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011346058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1011346058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.2484220161 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4075268532 ps |
| CPU time | 8.89 seconds |
| Started | Sep 24 07:53:06 PM UTC 24 |
| Finished | Sep 24 07:53:16 PM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484220161 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2484220161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.338274413 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1373813218 ps |
| CPU time | 10.03 seconds |
| Started | Sep 24 07:53:06 PM UTC 24 |
| Finished | Sep 24 07:53:17 PM UTC 24 |
| Peak memory | 231676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=338274413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_ stress_all_with_rand_reset.338274413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.169434565 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 527425461 ps |
| CPU time | 22.44 seconds |
| Started | Sep 24 07:53:00 PM UTC 24 |
| Finished | Sep 24 07:53:24 PM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169434565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.169434565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3497001252 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 260043487 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 07:53:03 PM UTC 24 |
| Finished | Sep 24 07:53:10 PM UTC 24 |
| Peak memory | 219384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497001252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3497001252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2830539364 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 81562512 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:31 PM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830539364 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2830539364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.2664495532 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 122208711 ps |
| CPU time | 3.87 seconds |
| Started | Sep 24 07:53:10 PM UTC 24 |
| Finished | Sep 24 07:53:15 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664495532 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2664495532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.2779077477 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 106476101 ps |
| CPU time | 6.69 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:36 PM UTC 24 |
| Peak memory | 223764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779077477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2779077477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.1319674114 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 43599488 ps |
| CPU time | 2.23 seconds |
| Started | Sep 24 07:53:20 PM UTC 24 |
| Finished | Sep 24 07:53:23 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319674114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1319674114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.3582885090 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 102804194 ps |
| CPU time | 5.13 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:34 PM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582885090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3582885090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.3547234250 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 45767106 ps |
| CPU time | 4.44 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:34 PM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547234250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3547234250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.1819037209 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 514533943 ps |
| CPU time | 5.77 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:35 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819037209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1819037209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_random.522932391 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 76750551 ps |
| CPU time | 5.84 seconds |
| Started | Sep 24 07:53:10 PM UTC 24 |
| Finished | Sep 24 07:53:17 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522932391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.522932391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.1020045692 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 796694171 ps |
| CPU time | 5.6 seconds |
| Started | Sep 24 07:53:08 PM UTC 24 |
| Finished | Sep 24 07:53:15 PM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020045692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1020045692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.1570185641 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4673310239 ps |
| CPU time | 47.78 seconds |
| Started | Sep 24 07:53:08 PM UTC 24 |
| Finished | Sep 24 07:53:58 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570185641 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1570185641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.699967704 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 299086427 ps |
| CPU time | 5.01 seconds |
| Started | Sep 24 07:53:08 PM UTC 24 |
| Finished | Sep 24 07:53:14 PM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699967704 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.699967704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.3968239767 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 389379603 ps |
| CPU time | 8.34 seconds |
| Started | Sep 24 07:53:09 PM UTC 24 |
| Finished | Sep 24 07:53:19 PM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968239767 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3968239767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.1447410750 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 102111031 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:32 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447410750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1447410750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.4199377292 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 88546760 ps |
| CPU time | 5.23 seconds |
| Started | Sep 24 07:53:07 PM UTC 24 |
| Finished | Sep 24 07:53:13 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199377292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.4199377292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.1947999646 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 350628599 ps |
| CPU time | 6.43 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:36 PM UTC 24 |
| Peak memory | 217340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947999646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1947999646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1050610180 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 275628173 ps |
| CPU time | 3.51 seconds |
| Started | Sep 24 07:53:28 PM UTC 24 |
| Finished | Sep 24 07:53:33 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050610180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1050610180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
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