Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3723957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601814

1

T1

148

T2

231

T3

259

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3916446	1			T1	469		T2	1062		T3	610
values[0x0]	203747	1			T1	43		T2	54		T3	118
values[0x1]	205578	1			T1	42		T2	51		T3	116

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2539690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1786081

1

T1

258

T2

516

T3

440

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15026	1			T3	6		T4	2		T14	4
valid_sources[0x01]	12334	1			T1	3		T4	9		T14	2
valid_sources[0x02]	18329	1			T1	1		T14	7		T15	8
valid_sources[0x03]	15577	1			T3	2		T14	5		T15	7
valid_sources[0x04]	18436	1			T1	1		T3	9		T14	4
valid_sources[0x05]	14117	1			T1	2		T14	2		T15	5
valid_sources[0x06]	14543	1			T1	3		T4	3		T14	3
valid_sources[0x07]	15677	1			T1	5		T3	13		T4	2
valid_sources[0x08]	13254	1			T4	1		T14	4		T15	12
valid_sources[0x09]	13332	1			T1	3		T4	3		T14	4
valid_sources[0x0a]	13227	1			T1	4		T14	5		T15	8
valid_sources[0x0b]	12751	1			T1	2		T4	2		T14	1
valid_sources[0x0c]	13746	1			T1	3		T14	5		T15	10
valid_sources[0x0d]	12609	1			T1	1		T3	7		T4	4
valid_sources[0x0e]	14594	1			T1	3		T15	8		T31	1
valid_sources[0x0f]	12883	1			T1	2		T3	3		T14	3
valid_sources[0x10]	15504	1			T3	16		T4	2		T14	8
valid_sources[0x11]	23492	1			T1	3		T14	5		T15	7
valid_sources[0x12]	14363	1			T3	4		T14	5		T15	8
valid_sources[0x13]	14337	1			T1	1		T3	9		T14	8
valid_sources[0x14]	13653	1			T1	1		T14	5		T15	10
valid_sources[0x15]	15933	1			T1	3		T3	10		T14	6
valid_sources[0x16]	13651	1			T1	1		T14	3		T15	6
valid_sources[0x17]	109981	1			T1	5		T14	4		T15	6
valid_sources[0x18]	13136	1			T4	4		T14	9		T15	5
valid_sources[0x19]	13390	1			T1	3		T14	2		T15	4
valid_sources[0x1a]	20425	1			T1	2		T4	2		T13	1026
valid_sources[0x1b]	14017	1			T1	3		T4	3		T14	2
valid_sources[0x1c]	12873	1			T1	4		T3	1		T14	5
valid_sources[0x1d]	14029	1			T1	1		T3	3		T4	1
valid_sources[0x1e]	14358	1			T1	4		T3	9		T4	3
valid_sources[0x1f]	13737	1			T1	3		T4	3		T14	2
valid_sources[0x20]	12751	1			T1	3		T14	3		T15	8
valid_sources[0x21]	14762	1			T1	2		T4	6		T14	3
valid_sources[0x22]	20990	1			T1	5		T4	5		T14	7
valid_sources[0x23]	13768	1			T1	2		T4	5		T14	2
valid_sources[0x24]	13440	1			T1	5		T3	2		T4	4
valid_sources[0x25]	13569	1			T1	4		T3	2		T4	1
valid_sources[0x26]	14272	1			T1	1		T4	10		T14	7
valid_sources[0x27]	15187	1			T3	1		T14	9		T15	7
valid_sources[0x28]	15200	1			T1	1		T4	2		T14	4
valid_sources[0x29]	28513	1			T1	4		T3	4		T4	1
valid_sources[0x2a]	12937	1			T1	2		T3	7		T14	4
valid_sources[0x2b]	16150	1			T1	1		T3	1		T14	6
valid_sources[0x2c]	13297	1			T1	3		T4	3		T14	4
valid_sources[0x2d]	155598	1			T3	2		T4	1		T14	8
valid_sources[0x2e]	19220	1			T1	4		T4	1		T14	5
valid_sources[0x2f]	12856	1			T1	3		T4	1		T14	4
valid_sources[0x30]	14959	1			T1	1		T3	15		T4	3
valid_sources[0x31]	13485	1			T1	2		T3	1		T4	2
valid_sources[0x32]	16983	1			T1	4		T4	1		T14	7
valid_sources[0x33]	13086	1			T1	2		T3	3		T4	5
valid_sources[0x34]	13467	1			T1	5		T4	5		T14	6
valid_sources[0x35]	15737	1			T1	4		T4	2		T14	5
valid_sources[0x36]	12779	1			T1	1		T3	1		T14	4
valid_sources[0x37]	12979	1			T1	3		T14	4		T15	5
valid_sources[0x38]	14228	1			T3	8		T4	4		T14	8
valid_sources[0x39]	15366	1			T1	7		T4	1		T14	10
valid_sources[0x3a]	16303	1			T4	3		T14	2		T15	4
valid_sources[0x3b]	17976	1			T1	2		T3	10		T4	1
valid_sources[0x3c]	17614	1			T1	1		T3	39		T4	3
valid_sources[0x3d]	13790	1			T4	15		T14	8		T15	7
valid_sources[0x3e]	22149	1			T1	1		T3	9		T14	4
valid_sources[0x3f]	26879	1			T1	1		T14	3		T15	7
valid_sources[0x40]	13212	1			T1	2		T3	2		T4	1
valid_sources[0x41]	14374	1			T1	1		T4	1		T14	7
valid_sources[0x42]	15059	1			T1	3		T3	2		T4	5
valid_sources[0x43]	12605	1			T1	2		T4	1		T14	3
valid_sources[0x44]	20637	1			T14	5		T15	4		T18	12
valid_sources[0x45]	22252	1			T1	2		T14	4		T15	8
valid_sources[0x46]	13488	1			T1	2		T14	5		T15	3
valid_sources[0x47]	16538	1			T3	3		T14	5		T15	4
valid_sources[0x48]	13506	1			T1	3		T14	9		T15	8
valid_sources[0x49]	14716	1			T3	4		T4	3		T14	5
valid_sources[0x4a]	14418	1			T1	3		T14	1		T15	3
valid_sources[0x4b]	13244	1			T1	3		T14	6		T15	8
valid_sources[0x4c]	12836	1			T1	2		T3	2		T14	2
valid_sources[0x4d]	15379	1			T1	6		T14	6		T15	9
valid_sources[0x4e]	13551	1			T1	2		T3	20		T14	8
valid_sources[0x4f]	13032	1			T1	1		T14	5		T15	14
valid_sources[0x50]	60857	1			T1	1		T3	9		T14	4
valid_sources[0x51]	14613	1			T1	1		T3	2		T14	5
valid_sources[0x52]	13514	1			T1	1		T3	3		T14	3
valid_sources[0x53]	14150	1			T3	2		T4	1		T14	3
valid_sources[0x54]	15322	1			T1	2		T14	2		T15	3
valid_sources[0x55]	13418	1			T1	4		T3	5		T14	4
valid_sources[0x56]	14476	1			T1	1		T4	1		T14	6
valid_sources[0x57]	13700	1			T1	3		T14	9		T15	8
valid_sources[0x58]	13697	1			T1	2		T3	19		T14	6
valid_sources[0x59]	13273	1			T1	1		T4	1		T14	5
valid_sources[0x5a]	12446	1			T1	3		T3	2		T14	11
valid_sources[0x5b]	13105	1			T1	1		T3	1		T14	4
valid_sources[0x5c]	12623	1			T1	2		T3	9		T14	10
valid_sources[0x5d]	12705	1			T1	1		T4	3		T14	5
valid_sources[0x5e]	13071	1			T1	3		T4	5		T14	6
valid_sources[0x5f]	12957	1			T1	4		T14	6		T15	9
valid_sources[0x60]	18915	1			T1	2		T14	2		T15	7
valid_sources[0x61]	12651	1			T1	3		T14	12		T15	8
valid_sources[0x62]	16072	1			T1	2		T3	2		T14	5
valid_sources[0x63]	14052	1			T1	1		T3	9		T4	2
valid_sources[0x64]	13889	1			T1	2		T4	3		T14	8
valid_sources[0x65]	16697	1			T1	4		T4	2		T14	3
valid_sources[0x66]	21808	1			T1	1		T4	4		T14	7
valid_sources[0x67]	14383	1			T1	2		T4	1		T14	6
valid_sources[0x68]	14804	1			T1	1		T3	8		T4	5
valid_sources[0x69]	13627	1			T1	3		T14	3		T15	7
valid_sources[0x6a]	13310	1			T1	2		T3	1		T14	4
valid_sources[0x6b]	14135	1			T1	3		T4	2		T15	8
valid_sources[0x6c]	15099	1			T3	1		T14	2		T15	3
valid_sources[0x6d]	13382	1			T1	4		T3	16		T14	6
valid_sources[0x6e]	14215	1			T1	1		T14	4		T15	5
valid_sources[0x6f]	16939	1			T1	3		T4	1		T14	4
valid_sources[0x70]	12579	1			T1	2		T4	6		T14	1
valid_sources[0x71]	13660	1			T1	1		T4	1		T14	3
valid_sources[0x72]	13718	1			T1	2		T14	2		T15	5
valid_sources[0x73]	16650	1			T1	1		T4	8		T14	5
valid_sources[0x74]	23563	1			T3	5		T4	3		T14	4
valid_sources[0x75]	12207	1			T1	2		T3	14		T4	1
valid_sources[0x76]	14099	1			T1	1		T3	14		T14	3
valid_sources[0x77]	12889	1			T3	8		T4	9		T14	3
valid_sources[0x78]	13363	1			T1	3		T3	3		T4	4
valid_sources[0x79]	12908	1			T1	3		T3	20		T4	1
valid_sources[0x7a]	13379	1			T1	2		T14	5		T15	7
valid_sources[0x7b]	13893	1			T1	2		T4	3		T14	4
valid_sources[0x7c]	14842	1			T1	2		T4	2		T14	3
valid_sources[0x7d]	14119	1			T3	5		T14	2		T15	4
valid_sources[0x7e]	14240	1			T1	6		T3	3		T4	3
valid_sources[0x7f]	13777	1			T1	2		T14	7		T15	9
valid_sources[0x80]	13968	1			T1	1		T3	5		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

323251

1

T1

123

T2

196

T3

94

values[0x0]

all_enables

biggest_size

146627

1

T1

18

T2

21

T3

94

values[0x1]

all_enables

biggest_size

131936

1

T1

7

T2

14

T3

71