Module Definition
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Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 3/3 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 7857 7857 0 0
OutputsKnown_A 221662008 220121991 0 0
gen_no_flops.OutputDelay_A 221662008 220121991 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7857 7857 0 0
T1 9 9 0 0
T2 9 9 0 0
T3 9 9 0 0
T4 9 9 0 0
T13 9 9 0 0
T14 9 9 0 0
T15 9 9 0 0
T16 9 9 0 0
T17 9 9 0 0
T18 9 9 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 221662008 220121991 0 0
T1 29358 28512 0 0
T2 125037 124452 0 0
T3 34137 33435 0 0
T4 32913 32022 0 0
T13 100134 99486 0 0
T14 61947 60849 0 0
T15 118647 117441 0 0
T16 116973 116397 0 0
T17 9792 8928 0 0
T18 208359 207567 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 221662008 220121991 0 0
T1 29358 28512 0 0
T2 125037 124452 0 0
T3 34137 33435 0 0
T4 32913 32022 0 0
T13 100134 99486 0 0
T14 61947 60849 0 0
T15 118647 117441 0 0
T16 116973 116397 0 0
T17 9792 8928 0 0
T18 208359 207567 0 0

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 3/3 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 873 873 0 0
OutputsKnown_A 24629112 24457999 0 0
gen_no_flops.OutputDelay_A 24629112 24457999 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 873 873 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 24629112 24457999 0 0
T1 3262 3168 0 0
T2 13893 13828 0 0
T3 3793 3715 0 0
T4 3657 3558 0 0
T13 11126 11054 0 0
T14 6883 6761 0 0
T15 13183 13049 0 0
T16 12997 12933 0 0
T17 1088 992 0 0
T18 23151 23063 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%