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Module Instance : tb.dut.u_reg.u_sw_share0_output_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share0_output_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_sw_share1_output_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_working_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.59 77.78 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_op_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_err_code_invalid_op

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 91.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 95.00 100.00 90.00


Module Instance : tb.dut.u_reg.u_fault_status_cmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_fault_status_kmac_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_fault_status_kmac_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_fault_status_kmac_op

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_fault_status_kmac_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.24 85.71 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.59 77.78 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_fault_status_regfile_intg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.35 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00

Go back
Module Instances:
tb.dut.u_reg.u_sw_share0_output_0
tb.dut.u_reg.u_sw_share0_output_1
tb.dut.u_reg.u_sw_share0_output_2
tb.dut.u_reg.u_sw_share0_output_3
tb.dut.u_reg.u_sw_share0_output_4
tb.dut.u_reg.u_sw_share0_output_5
tb.dut.u_reg.u_sw_share0_output_6
tb.dut.u_reg.u_sw_share0_output_7
tb.dut.u_reg.u_sw_share1_output_0
tb.dut.u_reg.u_sw_share1_output_1
tb.dut.u_reg.u_sw_share1_output_2
tb.dut.u_reg.u_sw_share1_output_3
tb.dut.u_reg.u_sw_share1_output_4
tb.dut.u_reg.u_sw_share1_output_5
tb.dut.u_reg.u_sw_share1_output_6
tb.dut.u_reg.u_sw_share1_output_7
tb.dut.u_reg.u_working_state
tb.dut.u_reg.u_op_status
tb.dut.u_reg.u_err_code_invalid_op
tb.dut.u_reg.u_err_code_invalid_kmac_input
tb.dut.u_reg.u_err_code_invalid_shadow_update
tb.dut.u_reg.u_fault_status_cmd
tb.dut.u_reg.u_fault_status_kmac_fsm
tb.dut.u_reg.u_fault_status_kmac_done
tb.dut.u_reg.u_fault_status_kmac_op
tb.dut.u_reg.u_fault_status_kmac_out
tb.dut.u_reg.u_fault_status_regfile_intg
Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_0
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_0
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_1
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_1
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_2
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_2
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_3
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_3
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_4
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_4
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_4
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_5
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_5
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_5
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_6
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_6
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_6
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_7
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_7
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share0_output_7
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_0
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_0
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_1
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_1
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_2
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_2
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_7
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_7
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_7
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_working_state
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end ==> MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 0/1 ==> assign qe = wr_en; 66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_working_state
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_working_state
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_op_status
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_op_status
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_op_status
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_op
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_op
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_op
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_cmd
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T8 T21 T9  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_cmd
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T21,T9

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_cmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T8,T21,T9
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T21,T9
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_fsm
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T10 T11 T12  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_fsm
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_fsm
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T11,T12
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_done
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T15 T27 T28  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_done
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_done
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T15,T27,T28
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T27,T28
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_op
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T14 T33 T34  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_op
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T33,T34

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_op
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T14,T33,T34
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T14,T33,T34
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_out
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS564375.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 0/1 ==> q <= wr_data; 60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_out
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_out
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_regfile_intg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T33 T10 T38  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_regfile_intg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T10,T38

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_regfile_intg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T33,T10,T38
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T33,T10,T38
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%