Module Definition
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Module : prim_secded_inv_72_64_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 93.15 93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 95.89 95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 96.58 96.58
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 97.95 97.95
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 100.00 100.00



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.15 93.15


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 95.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 96.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.95 97.95


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.95 97.95


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 292 292 100.00
Total Bits 0->1 146 146 100.00
Total Bits 1->0 146 146 100.00

Ports 4 4 100.00
Port Bits 292 292 100.00
Port Bits 0->1 146 146 100.00
Port Bits 1->0 146 146 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
err_o[1:0] Yes Yes T178,T179,T180 Yes T178,T179,T180 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 272 93.15
Total Bits 0->1 146 136 93.15
Total Bits 1->0 146 136 93.15

Ports 4 2 50.00
Port Bits 292 272 93.15
Port Bits 0->1 146 136 93.15
Port Bits 1->0 146 136 93.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] No No No OUTPUT
err_o[1:0] No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[1:0] Yes Yes T180 Yes T180 OUTPUT
syndrome_o[2] No No No OUTPUT
syndrome_o[3] Yes Yes *T180 Yes T180 OUTPUT
syndrome_o[7:4] No No No OUTPUT
err_o[0] Yes Yes *T180 Yes T180 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T179 Yes T179 OUTPUT
syndrome_o[3:1] No No No OUTPUT
syndrome_o[4] Yes Yes *T179 Yes T179 OUTPUT
syndrome_o[6:5] No No No OUTPUT
syndrome_o[7] Yes Yes T179 Yes T179 OUTPUT
err_o[0] Yes Yes *T179 Yes T179 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] No No No OUTPUT
syndrome_o[2:1] Yes Yes T182 Yes T182 OUTPUT
syndrome_o[4:3] No No No OUTPUT
syndrome_o[5] Yes Yes *T182 Yes T182 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T182 Yes T182 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T183 Yes T183 OUTPUT
syndrome_o[3:1] No No No OUTPUT
syndrome_o[5:4] Yes Yes T183 Yes T183 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T183 Yes T183 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] Yes Yes *T184 Yes T184 OUTPUT
syndrome_o[1] No No No OUTPUT
syndrome_o[2] Yes Yes *T184 Yes T184 OUTPUT
syndrome_o[4:3] No No No OUTPUT
syndrome_o[5] Yes Yes *T184 Yes T184 OUTPUT
syndrome_o[7:6] No No No OUTPUT
err_o[0] Yes Yes *T184 Yes T184 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[1:0] No No No OUTPUT
syndrome_o[2] Yes Yes *T183 Yes T183 OUTPUT
syndrome_o[3] No No No OUTPUT
syndrome_o[4] Yes Yes *T183 Yes T183 OUTPUT
syndrome_o[6:5] No No No OUTPUT
syndrome_o[7] Yes Yes T183 Yes T183 OUTPUT
err_o[0] Yes Yes *T183 Yes T183 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 280 95.89
Total Bits 0->1 146 140 95.89
Total Bits 1->0 146 140 95.89

Ports 4 2 50.00
Port Bits 292 280 95.89
Port Bits 0->1 146 140 95.89
Port Bits 1->0 146 140 95.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] No No No OUTPUT
syndrome_o[1] Yes Yes *T185 Yes T185 OUTPUT
syndrome_o[2] No No No OUTPUT
syndrome_o[3] Yes Yes *T185 Yes T185 OUTPUT
syndrome_o[5:4] No No No OUTPUT
syndrome_o[6] Yes Yes *T185 Yes T185 OUTPUT
syndrome_o[7] No No No OUTPUT
err_o[0] Yes Yes *T185 Yes T185 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 282 96.58
Total Bits 0->1 146 141 96.58
Total Bits 1->0 146 141 96.58

Ports 4 2 50.00
Port Bits 292 282 96.58
Port Bits 0->1 146 141 96.58
Port Bits 1->0 146 141 96.58

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[2:0] Yes Yes T179,*T185 Yes T179,T185 OUTPUT
syndrome_o[3] No No No OUTPUT
syndrome_o[4] Yes Yes *T185 Yes T185 OUTPUT
syndrome_o[7:5] No No No OUTPUT
err_o[0] Yes Yes *T179,*T185 Yes T179,T185 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 292 286 97.95
Total Bits 0->1 146 143 97.95
Total Bits 1->0 146 143 97.95

Ports 4 2 50.00
Port Bits 292 286 97.95
Port Bits 0->1 146 143 97.95
Port Bits 1->0 146 143 97.95

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[1:0] Yes Yes T181 Yes T181 OUTPUT
syndrome_o[2] No No No OUTPUT
syndrome_o[3] Yes Yes *T178 Yes T178 OUTPUT
syndrome_o[4] No No No OUTPUT
syndrome_o[7:5] Yes Yes T181,T178 Yes T181,T178 OUTPUT
err_o[0] Yes Yes *T178,*T181 Yes T178,T181 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 292 292 100.00
Total Bits 0->1 146 146 100.00
Total Bits 1->0 146 146 100.00

Ports 4 4 100.00
Port Bits 292 292 100.00
Port Bits 0->1 146 146 100.00
Port Bits 1->0 146 146 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[71:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[7:0] Yes Yes T186,T187,T184 Yes T186,T187,T184 OUTPUT
err_o[1:0] Yes Yes T186,T184,T187 Yes T186,T184,T187 OUTPUT

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