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Module Instance : tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 shadow_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 committed_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sealing_sw_binding_7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_attest_sw_binding_7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_salt_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_salt_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb
tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb
tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb
tb.dut.u_reg.u_salt_0.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T14  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T14

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T14
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T14  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T14

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T14
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T14  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T14

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T14
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T14  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T14

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T14
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T15  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T15

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T15

Branch Coverage for Instance : tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_salt_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T4 T14  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_salt_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T4,T14

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_salt_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T4,T14
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%