dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_key_ecc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_creator_seed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_owner_seed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_dev_id


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_health_state


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_key_version


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_key


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_digest


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT20,T24,T25
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T24,T25
11CoveredT20,T24,T25

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T24,T25

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT101,T104
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT101,T104
11CoveredT101,T104

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT101,T104

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT103,T105,T107
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT103,T105,T107
11CoveredT103,T105,T107

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT103,T105,T107

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T103
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T25,T103
11CoveredT24,T25,T103

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T25,T103

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T20,T5
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT19,T20,T5
11CoveredT19,T20,T5

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T22,T23
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30
11CoveredT21,T22,T23

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T23

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT20,T24,T25
10CoveredT19,T20,T5

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T24,T25
11CoveredT20,T24,T25

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T24,T25

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T5
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%