Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26413998	15347	0	0
attest_sw_binding_0_rd_A	26413998	3737	0	0
attest_sw_binding_1_rd_A	26413998	3637	0	0
attest_sw_binding_2_rd_A	26413998	3745	0	0
attest_sw_binding_3_rd_A	26413998	3777	0	0
attest_sw_binding_4_rd_A	26413998	3802	0	0
attest_sw_binding_5_rd_A	26413998	3824	0	0
attest_sw_binding_6_rd_A	26413998	3986	0	0
attest_sw_binding_7_rd_A	26413998	3623	0	0
intr_enable_rd_A	26413998	4346	0	0
key_version_rd_A	26413998	3648	0	0
max_creator_key_ver_regwen_rd_A	26413998	3748	0	0
max_owner_int_key_ver_regwen_rd_A	26413998	3674	0	0
max_owner_key_ver_regwen_rd_A	26413998	3665	0	0
reseed_interval_regwen_rd_A	26413998	3699	0	0
salt_0_rd_A	26413998	3718	0	0
salt_1_rd_A	26413998	3729	0	0
salt_2_rd_A	26413998	3715	0	0
salt_3_rd_A	26413998	3677	0	0
salt_4_rd_A	26413998	3685	0	0
salt_5_rd_A	26413998	3639	0	0
salt_6_rd_A	26413998	3754	0	0
salt_7_rd_A	26413998	3726	0	0
sealing_sw_binding_0_rd_A	26413998	3740	0	0
sealing_sw_binding_1_rd_A	26413998	3666	0	0
sealing_sw_binding_2_rd_A	26413998	3643	0	0
sealing_sw_binding_3_rd_A	26413998	3782	0	0
sealing_sw_binding_4_rd_A	26413998	3755	0	0
sealing_sw_binding_5_rd_A	26413998	3571	0	0
sealing_sw_binding_6_rd_A	26413998	3649	0	0
sealing_sw_binding_7_rd_A	26413998	3698	0	0
sideload_clear_rd_A	26413998	3689	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	15347	0	0
T44	20525	827	0	0
T45	0	730	0	0
T46	0	433	0	0
T47	0	204	0	0
T48	0	60	0	0
T49	0	767	0	0
T50	0	186	0	0
T51	0	648	0	0
T52	0	845	0	0
T53	0	497	0	0
T54	6931	0	0	0
T55	1032	0	0	0
T56	8499	0	0	0
T57	13718	0	0	0
T58	17668	0	0	0
T59	8201	0	0	0
T60	6645	0	0	0
T61	2117	0	0	0
T62	47582	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3737	0	0
T47	53556	48	0	0
T75	148065	0	0	0
T118	0	65	0	0
T121	1873	0	0	0
T156	0	1	0	0
T157	0	20	0	0
T188	0	70	0	0
T189	0	27	0	0
T190	0	30	0	0
T191	0	54	0	0
T192	0	5	0	0
T193	0	10	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3637	0	0
T47	53556	31	0	0
T75	148065	0	0	0
T118	0	31	0	0
T121	1873	0	0	0
T156	0	8	0	0
T157	0	8	0	0
T188	0	66	0	0
T189	0	34	0	0
T190	0	39	0	0
T191	0	53	0	0
T192	0	17	0	0
T193	0	1	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3745	0	0
T47	53556	55	0	0
T75	148065	0	0	0
T118	0	52	0	0
T121	1873	0	0	0
T156	0	7	0	0
T157	0	20	0	0
T158	0	5	0	0
T188	0	86	0	0
T189	0	23	0	0
T190	0	23	0	0
T191	0	75	0	0
T192	0	6	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3777	0	0
T47	53556	48	0	0
T75	148065	0	0	0
T118	0	66	0	0
T121	1873	0	0	0
T156	0	2	0	0
T157	0	14	0	0
T188	0	46	0	0
T189	0	55	0	0
T190	0	37	0	0
T191	0	76	0	0
T192	0	8	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	9	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3802	0	0
T47	53556	51	0	0
T75	148065	0	0	0
T118	0	46	0	0
T121	1873	0	0	0
T156	0	8	0	0
T157	0	22	0	0
T188	0	53	0	0
T189	0	37	0	0
T190	0	29	0	0
T191	0	71	0	0
T192	0	9	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	12	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3824	0	0
T47	53556	43	0	0
T75	148065	0	0	0
T118	0	74	0	0
T121	1873	0	0	0
T156	0	5	0	0
T157	0	25	0	0
T158	0	7	0	0
T188	0	85	0	0
T189	0	24	0	0
T190	0	35	0	0
T191	0	82	0	0
T192	0	25	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3986	0	0
T47	53556	62	0	0
T75	148065	0	0	0
T118	0	67	0	0
T121	1873	0	0	0
T156	0	7	0	0
T157	0	14	0	0
T158	0	2	0	0
T188	0	50	0	0
T189	0	10	0	0
T190	0	47	0	0
T191	0	100	0	0
T192	0	13	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3623	0	0
T47	53556	38	0	0
T75	148065	0	0	0
T118	0	60	0	0
T121	1873	0	0	0
T157	0	17	0	0
T158	0	9	0	0
T188	0	54	0	0
T189	0	30	0	0
T190	0	38	0	0
T191	0	39	0	0
T192	0	20	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	4346	0	0
T47	0	108	0	0
T75	0	71	0	0
T111	6322	0	0	0
T125	51306	29	0	0
T133	0	15	0	0
T148	10533	0	0	0
T149	20275	0	0	0
T150	81389	0	0	0
T151	6538	0	0	0
T152	3233	0	0	0
T153	1056	0	0	0
T154	9932	0	0	0
T155	10271	0	0	0
T188	0	75	0	0
T189	0	20	0	0
T190	0	15	0	0
T202	0	16	0	0
T203	0	27	0	0
T204	0	25	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3648	0	0
T47	53556	54	0	0
T75	148065	0	0	0
T118	0	62	0	0
T121	1873	0	0	0
T156	0	9	0	0
T157	0	19	0	0
T188	0	58	0	0
T189	0	23	0	0
T190	0	30	0	0
T191	0	52	0	0
T192	0	16	0	0
T193	0	27	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3748	0	0
T47	53556	50	0	0
T75	148065	0	0	0
T118	0	38	0	0
T121	1873	0	0	0
T156	0	10	0	0
T157	0	24	0	0
T188	0	64	0	0
T189	0	24	0	0
T190	0	24	0	0
T191	0	76	0	0
T192	0	17	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	10	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3674	0	0
T47	53556	72	0	0
T75	148065	0	0	0
T118	0	44	0	0
T121	1873	0	0	0
T156	0	7	0	0
T157	0	12	0	0
T158	0	6	0	0
T188	0	75	0	0
T189	0	36	0	0
T190	0	30	0	0
T191	0	61	0	0
T192	0	23	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3665	0	0
T47	53556	66	0	0
T75	148065	0	0	0
T118	0	38	0	0
T121	1873	0	0	0
T156	0	9	0	0
T157	0	14	0	0
T188	0	54	0	0
T189	0	30	0	0
T190	0	16	0	0
T191	0	61	0	0
T192	0	17	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3699	0	0
T47	53556	59	0	0
T75	148065	0	0	0
T118	0	63	0	0
T121	1873	0	0	0
T156	0	2	0	0
T157	0	18	0	0
T188	0	69	0	0
T189	0	33	0	0
T190	0	14	0	0
T191	0	67	0	0
T192	0	40	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	1	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3718	0	0
T47	53556	81	0	0
T75	148065	0	0	0
T118	0	51	0	0
T121	1873	0	0	0
T156	0	14	0	0
T157	0	17	0	0
T158	0	1	0	0
T188	0	44	0	0
T189	0	31	0	0
T190	0	46	0	0
T191	0	81	0	0
T192	0	2	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3729	0	0
T47	53556	55	0	0
T75	148065	0	0	0
T118	0	37	0	0
T121	1873	0	0	0
T156	0	15	0	0
T157	0	12	0	0
T188	0	56	0	0
T189	0	30	0	0
T190	0	34	0	0
T191	0	92	0	0
T192	0	28	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3715	0	0
T47	53556	72	0	0
T75	148065	0	0	0
T118	0	56	0	0
T121	1873	0	0	0
T156	0	6	0	0
T157	0	15	0	0
T188	0	42	0	0
T189	0	20	0	0
T190	0	21	0	0
T191	0	66	0	0
T192	0	9	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	1	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3677	0	0
T47	53556	60	0	0
T75	148065	0	0	0
T118	0	48	0	0
T121	1873	0	0	0
T156	0	4	0	0
T157	0	7	0	0
T188	0	61	0	0
T189	0	50	0	0
T190	0	22	0	0
T191	0	56	0	0
T192	0	6	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	2	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3685	0	0
T47	53556	45	0	0
T75	148065	0	0	0
T118	0	45	0	0
T121	1873	0	0	0
T156	0	8	0	0
T157	0	13	0	0
T188	0	92	0	0
T189	0	25	0	0
T190	0	13	0	0
T191	0	73	0	0
T192	0	5	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	6	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3639	0	0
T47	53556	57	0	0
T75	148065	0	0	0
T118	0	60	0	0
T121	1873	0	0	0
T156	0	7	0	0
T157	0	12	0	0
T188	0	61	0	0
T189	0	35	0	0
T190	0	15	0	0
T191	0	64	0	0
T192	0	10	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	6	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3754	0	0
T47	53556	75	0	0
T75	148065	0	0	0
T118	0	62	0	0
T121	1873	0	0	0
T156	0	12	0	0
T157	0	18	0	0
T158	0	6	0	0
T188	0	62	0	0
T189	0	36	0	0
T190	0	13	0	0
T191	0	70	0	0
T192	0	22	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3726	0	0
T47	53556	72	0	0
T75	148065	0	0	0
T118	0	79	0	0
T121	1873	0	0	0
T156	0	6	0	0
T157	0	22	0	0
T158	0	5	0	0
T188	0	62	0	0
T189	0	43	0	0
T190	0	21	0	0
T191	0	115	0	0
T192	0	27	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3740	0	0
T47	53556	82	0	0
T75	148065	0	0	0
T118	0	55	0	0
T121	1873	0	0	0
T156	0	9	0	0
T157	0	12	0	0
T158	0	4	0	0
T188	0	54	0	0
T189	0	38	0	0
T190	0	35	0	0
T191	0	48	0	0
T192	0	6	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3666	0	0
T47	53556	58	0	0
T75	148065	0	0	0
T118	0	39	0	0
T121	1873	0	0	0
T156	0	8	0	0
T157	0	8	0	0
T158	0	4	0	0
T188	0	55	0	0
T189	0	34	0	0
T190	0	26	0	0
T191	0	41	0	0
T192	0	3	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3643	0	0
T47	53556	66	0	0
T75	148065	0	0	0
T118	0	51	0	0
T121	1873	0	0	0
T156	0	12	0	0
T157	0	16	0	0
T188	0	50	0	0
T189	0	28	0	0
T190	0	35	0	0
T191	0	46	0	0
T192	0	26	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T205	0	6	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3782	0	0
T47	53556	71	0	0
T75	148065	0	0	0
T118	0	54	0	0
T121	1873	0	0	0
T156	0	9	0	0
T157	0	7	0	0
T188	0	63	0	0
T189	0	42	0	0
T190	0	20	0	0
T191	0	32	0	0
T192	0	25	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	2	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3755	0	0
T47	53556	65	0	0
T75	148065	0	0	0
T118	0	45	0	0
T121	1873	0	0	0
T156	0	5	0	0
T157	0	14	0	0
T188	0	55	0	0
T189	0	40	0	0
T190	0	28	0	0
T191	0	46	0	0
T192	0	27	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3571	0	0
T47	53556	51	0	0
T75	148065	0	0	0
T118	0	35	0	0
T121	1873	0	0	0
T156	0	13	0	0
T157	0	18	0	0
T188	0	46	0	0
T189	0	31	0	0
T190	0	16	0	0
T191	0	66	0	0
T192	0	14	0	0
T193	0	26	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3649	0	0
T47	53556	32	0	0
T75	148065	0	0	0
T118	0	48	0	0
T121	1873	0	0	0
T156	0	6	0	0
T157	0	20	0	0
T158	0	3	0	0
T188	0	55	0	0
T189	0	17	0	0
T190	0	42	0	0
T191	0	58	0	0
T192	0	45	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3698	0	0
T47	53556	57	0	0
T75	148065	0	0	0
T118	0	60	0	0
T121	1873	0	0	0
T156	0	8	0	0
T157	0	9	0	0
T188	0	65	0	0
T189	0	28	0	0
T190	0	35	0	0
T191	0	77	0	0
T192	0	20	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	6	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413998	3689	0	0
T47	53556	57	0	0
T75	148065	0	0	0
T118	0	43	0	0
T121	1873	0	0	0
T156	0	10	0	0
T157	0	23	0	0
T188	0	50	0	0
T189	0	24	0	0
T190	0	34	0	0
T191	0	108	0	0
T192	0	11	0	0
T194	4675	0	0	0
T195	3369	0	0	0
T196	26303	0	0	0
T197	3660	0	0	0
T198	1513	0	0	0
T199	2346	0	0	0
T200	7344	0	0	0
T201	0	1	0	0