| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.78 | 99.03 | 98.03 | 98.57 | 100.00 | 99.01 | 98.63 | 91.17 |
| T1006 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.826976191 | Oct 03 02:03:29 AM UTC 24 | Oct 03 02:03:34 AM UTC 24 | 349173211 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.2714299338 | Oct 03 02:03:26 AM UTC 24 | Oct 03 02:03:34 AM UTC 24 | 212486663 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.3036783335 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:35 AM UTC 24 | 7705289 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3456112402 | Oct 03 02:03:30 AM UTC 24 | Oct 03 02:03:35 AM UTC 24 | 244560210 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.421859592 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:35 AM UTC 24 | 55085953 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3123580852 | Oct 03 02:03:31 AM UTC 24 | Oct 03 02:03:35 AM UTC 24 | 241078723 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2311049013 | Oct 03 02:03:29 AM UTC 24 | Oct 03 02:03:35 AM UTC 24 | 461985891 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4184026590 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:35 AM UTC 24 | 224210363 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3625978382 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:36 AM UTC 24 | 206327557 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.998257917 | Oct 03 02:03:31 AM UTC 24 | Oct 03 02:03:36 AM UTC 24 | 127521985 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3114730695 | Oct 03 02:03:34 AM UTC 24 | Oct 03 02:03:36 AM UTC 24 | 22145759 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.2631092576 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:36 AM UTC 24 | 92708777 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.497723512 | Oct 03 02:03:27 AM UTC 24 | Oct 03 02:03:36 AM UTC 24 | 279396368 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.417012997 | Oct 03 02:03:34 AM UTC 24 | Oct 03 02:03:36 AM UTC 24 | 51374050 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.2157853830 | Oct 03 02:03:34 AM UTC 24 | Oct 03 02:03:37 AM UTC 24 | 24708652 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2418949242 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:37 AM UTC 24 | 123997817 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.852226107 | Oct 03 02:03:32 AM UTC 24 | Oct 03 02:03:37 AM UTC 24 | 223535312 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.318527704 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:40 AM UTC 24 | 168442459 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1643961284 | Oct 03 02:03:34 AM UTC 24 | Oct 03 02:03:37 AM UTC 24 | 31449432 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.2812975541 | Oct 03 02:03:31 AM UTC 24 | Oct 03 02:03:37 AM UTC 24 | 176347022 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.689646887 | Oct 03 02:03:31 AM UTC 24 | Oct 03 02:03:38 AM UTC 24 | 118982033 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3857348332 | Oct 03 02:03:36 AM UTC 24 | Oct 03 02:03:38 AM UTC 24 | 10408757 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1580445790 | Oct 03 02:03:36 AM UTC 24 | Oct 03 02:03:38 AM UTC 24 | 19347740 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3115383809 | Oct 03 02:03:36 AM UTC 24 | Oct 03 02:03:39 AM UTC 24 | 32221158 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2190653101 | Oct 03 02:03:31 AM UTC 24 | Oct 03 02:03:39 AM UTC 24 | 800438717 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1795906400 | Oct 03 02:03:26 AM UTC 24 | Oct 03 02:03:40 AM UTC 24 | 1313235570 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1126963854 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:40 AM UTC 24 | 11101729 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2064390374 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:41 AM UTC 24 | 84623925 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.737736081 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:41 AM UTC 24 | 35642204 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2769815850 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:41 AM UTC 24 | 45576065 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3726446381 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:41 AM UTC 24 | 9202850 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.658750580 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:41 AM UTC 24 | 17397402 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3002836302 | Oct 03 02:03:38 AM UTC 24 | Oct 03 02:03:41 AM UTC 24 | 38435614 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3877925499 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:42 AM UTC 24 | 75533805 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1272547578 | Oct 03 02:03:08 AM UTC 24 | Oct 03 02:03:42 AM UTC 24 | 852476618 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.659583188 | Oct 03 02:03:36 AM UTC 24 | Oct 03 02:03:42 AM UTC 24 | 997631772 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.416321582 | Oct 03 02:03:34 AM UTC 24 | Oct 03 02:03:42 AM UTC 24 | 628017890 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.1048817595 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 50648208 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2903927270 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 26120903 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.87224716 | Oct 03 02:03:41 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 33798321 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.858997974 | Oct 03 02:03:41 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 35377101 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.146777823 | Oct 03 02:03:41 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 15264712 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.193676841 | Oct 03 02:03:40 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 46810239 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2648408403 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 344485030 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2502750743 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 481165179 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.1672791197 | Oct 03 02:03:41 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 12062921 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3476710365 | Oct 03 02:03:41 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 13976120 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.424539027 | Oct 03 02:03:41 AM UTC 24 | Oct 03 02:03:43 AM UTC 24 | 39674767 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3829530500 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:44 AM UTC 24 | 2116194147 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4013910560 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:44 AM UTC 24 | 738681709 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.355188860 | Oct 03 02:03:34 AM UTC 24 | Oct 03 02:03:44 AM UTC 24 | 1169483247 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.1990825901 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 32555383 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.736404123 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 46562291 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3703102161 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 15217108 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.251343932 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 79872234 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2608345823 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 21741766 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1978185346 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 20306323 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1270154482 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 9324542 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3384042719 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 8497675 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1369548041 | Oct 03 02:03:31 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 3917952694 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1704243211 | Oct 03 02:03:42 AM UTC 24 | Oct 03 02:03:45 AM UTC 24 | 15096096 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.175251298 | Oct 03 02:03:39 AM UTC 24 | Oct 03 02:03:46 AM UTC 24 | 485421052 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2163517982 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 23770091 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2104507135 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 41169952 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2041097308 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 16232368 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.1755350675 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 15868701 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2292788271 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 14504366 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2299877041 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 31045605 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3589382572 | Oct 03 02:03:45 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 16891441 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2132162766 | Oct 03 02:03:44 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 11814089 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.3847333260 | Oct 03 02:03:45 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 9916207 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.2694688042 | Oct 03 02:03:45 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 142001398 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1941673167 | Oct 03 02:03:45 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 22819145 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.1193201611 | Oct 03 02:03:45 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 11011555 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2432140788 | Oct 03 02:03:45 AM UTC 24 | Oct 03 02:03:47 AM UTC 24 | 12715437 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.89742860 | Oct 03 02:03:38 AM UTC 24 | Oct 03 02:03:49 AM UTC 24 | 394019912 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3029819758 | Oct 03 02:03:37 AM UTC 24 | Oct 03 02:03:49 AM UTC 24 | 1830800586 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2675100995 | Oct 03 02:03:35 AM UTC 24 | Oct 03 02:03:51 AM UTC 24 | 1604980525 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.2760294594 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 564677479 ps |
| CPU time | 6.1 seconds |
| Started | Oct 03 01:58:08 AM UTC 24 |
| Finished | Oct 03 01:58:15 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760294594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2760294594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.2151954897 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 560732773 ps |
| CPU time | 27.02 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:49 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151954897 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2151954897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.704456872 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 578886781 ps |
| CPU time | 6.18 seconds |
| Started | Oct 03 01:58:08 AM UTC 24 |
| Finished | Oct 03 01:58:15 AM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704456872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.704456872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.1512489772 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1071166077 ps |
| CPU time | 19.94 seconds |
| Started | Oct 03 01:59:07 AM UTC 24 |
| Finished | Oct 03 01:59:28 AM UTC 24 |
| Peak memory | 231668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1512489772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr _stress_all_with_rand_reset.1512489772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.1514560154 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 478603425 ps |
| CPU time | 15.09 seconds |
| Started | Oct 03 01:58:12 AM UTC 24 |
| Finished | Oct 03 01:58:29 AM UTC 24 |
| Peak memory | 257964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514560154 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1514560154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.21577022 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1525080529 ps |
| CPU time | 30.66 seconds |
| Started | Oct 03 01:58:31 AM UTC 24 |
| Finished | Oct 03 01:59:03 AM UTC 24 |
| Peak memory | 231440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=21577022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_s tress_all_with_rand_reset.21577022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.2324879997 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1059186844 ps |
| CPU time | 8.89 seconds |
| Started | Oct 03 01:58:11 AM UTC 24 |
| Finished | Oct 03 01:58:21 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324879997 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2324879997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.3532877906 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 292726736 ps |
| CPU time | 6.46 seconds |
| Started | Oct 03 01:58:43 AM UTC 24 |
| Finished | Oct 03 01:58:50 AM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532877906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3532877906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.198112932 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1480676878 ps |
| CPU time | 35.76 seconds |
| Started | Oct 03 01:58:52 AM UTC 24 |
| Finished | Oct 03 01:59:29 AM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198112932 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.198112932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.3159716752 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 34798748 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 01:58:22 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159716752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3159716752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3251412993 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3884632936 ps |
| CPU time | 19.63 seconds |
| Started | Oct 03 01:58:07 AM UTC 24 |
| Finished | Oct 03 01:58:28 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251412993 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3251412993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.1041823969 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 104095156 ps |
| CPU time | 3.56 seconds |
| Started | Oct 03 01:58:18 AM UTC 24 |
| Finished | Oct 03 01:58:23 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041823969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1041823969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.2428982928 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 278383935 ps |
| CPU time | 8.92 seconds |
| Started | Oct 03 01:58:08 AM UTC 24 |
| Finished | Oct 03 01:58:18 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428982928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2428982928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.493402176 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 802963199 ps |
| CPU time | 14.68 seconds |
| Started | Oct 03 01:59:10 AM UTC 24 |
| Finished | Oct 03 01:59:26 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493402176 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.493402176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3747687809 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 285371875 ps |
| CPU time | 4.42 seconds |
| Started | Oct 03 02:03:01 AM UTC 24 |
| Finished | Oct 03 02:03:06 AM UTC 24 |
| Peak memory | 225972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747687809 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.3747687809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.3727593578 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 70345769 ps |
| CPU time | 6.03 seconds |
| Started | Oct 03 01:58:35 AM UTC 24 |
| Finished | Oct 03 01:58:42 AM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727593578 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3727593578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.227750796 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 191048876 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 02:03:01 AM UTC 24 |
| Finished | Oct 03 02:03:07 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227750796 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.227750796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.2561479390 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 212390287 ps |
| CPU time | 10.36 seconds |
| Started | Oct 03 02:01:36 AM UTC 24 |
| Finished | Oct 03 02:01:47 AM UTC 24 |
| Peak memory | 223424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561479390 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2561479390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.2807550444 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3951787251 ps |
| CPU time | 39.05 seconds |
| Started | Oct 03 01:58:25 AM UTC 24 |
| Finished | Oct 03 01:59:05 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807550444 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2807550444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.949040109 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 58870792 ps |
| CPU time | 5.22 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 01:59:10 AM UTC 24 |
| Peak memory | 231468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949040109 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.949040109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.2623075124 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 50851920 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:53 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623075124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2623075124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.526988297 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 232386023 ps |
| CPU time | 9.34 seconds |
| Started | Oct 03 01:58:31 AM UTC 24 |
| Finished | Oct 03 01:58:42 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526988297 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.526988297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.33337589 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 410830438 ps |
| CPU time | 8.15 seconds |
| Started | Oct 03 02:02:19 AM UTC 24 |
| Finished | Oct 03 02:02:29 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33337589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.33337589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.2491914752 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 102304153 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 01:59:32 AM UTC 24 |
| Finished | Oct 03 01:59:36 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491914752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2491914752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.2588127710 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 137357338 ps |
| CPU time | 4.56 seconds |
| Started | Oct 03 01:58:08 AM UTC 24 |
| Finished | Oct 03 01:58:13 AM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588127710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2588127710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.4013723912 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 282148809 ps |
| CPU time | 7.55 seconds |
| Started | Oct 03 02:00:23 AM UTC 24 |
| Finished | Oct 03 02:00:31 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013723912 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4013723912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.2458473158 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 148862727 ps |
| CPU time | 4.59 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:42 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458473158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2458473158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.571333965 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1457453221 ps |
| CPU time | 30.93 seconds |
| Started | Oct 03 01:59:01 AM UTC 24 |
| Finished | Oct 03 01:59:33 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571333965 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.571333965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2450079778 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 531018561 ps |
| CPU time | 4.43 seconds |
| Started | Oct 03 02:02:21 AM UTC 24 |
| Finished | Oct 03 02:02:26 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450079778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2450079778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.1155441594 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 440853251 ps |
| CPU time | 11.92 seconds |
| Started | Oct 03 01:58:18 AM UTC 24 |
| Finished | Oct 03 01:58:31 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155441594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1155441594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3927623480 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 850102213 ps |
| CPU time | 8.92 seconds |
| Started | Oct 03 02:03:01 AM UTC 24 |
| Finished | Oct 03 02:03:11 AM UTC 24 |
| Peak memory | 232104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927623480 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.3927623480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.190077369 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 238102587 ps |
| CPU time | 13 seconds |
| Started | Oct 03 02:01:49 AM UTC 24 |
| Finished | Oct 03 02:02:03 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190077369 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.190077369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.1821083598 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 160280280 ps |
| CPU time | 4.08 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 231496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821083598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1821083598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.2261137374 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2428539016 ps |
| CPU time | 41.63 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:51 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261137374 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2261137374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.909845140 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1226514997 ps |
| CPU time | 41.28 seconds |
| Started | Oct 03 01:58:44 AM UTC 24 |
| Finished | Oct 03 01:59:27 AM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909845140 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.909845140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.2694747397 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 126328213 ps |
| CPU time | 8.01 seconds |
| Started | Oct 03 01:58:43 AM UTC 24 |
| Finished | Oct 03 01:58:52 AM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694747397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2694747397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.3556114121 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 644526741 ps |
| CPU time | 7.3 seconds |
| Started | Oct 03 02:03:10 AM UTC 24 |
| Finished | Oct 03 02:03:19 AM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556114121 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.3556114121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.3808326716 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 142793779 ps |
| CPU time | 6.06 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:36 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808326716 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3808326716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.1214471052 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 82699298 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:25 AM UTC 24 |
| Peak memory | 219164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214471052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1214471052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.3311990422 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 43626706 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 01:58:12 AM UTC 24 |
| Finished | Oct 03 01:58:15 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311990422 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3311990422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.918148293 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 205277966 ps |
| CPU time | 12.55 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:34 AM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=918148293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_ stress_all_with_rand_reset.918148293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.1769281860 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 9766702541 ps |
| CPU time | 36.83 seconds |
| Started | Oct 03 01:59:20 AM UTC 24 |
| Finished | Oct 03 01:59:59 AM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769281860 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1769281860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.1536929006 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 12529046473 ps |
| CPU time | 47.84 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536929006 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1536929006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.3360694417 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3080395593 ps |
| CPU time | 24.64 seconds |
| Started | Oct 03 01:59:06 AM UTC 24 |
| Finished | Oct 03 01:59:32 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360694417 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3360694417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.936774399 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 148179811 ps |
| CPU time | 7.27 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:46 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936774399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.936774399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.1446047343 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 157758178 ps |
| CPU time | 4.56 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446047343 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1446047343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.3338490617 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 166496873 ps |
| CPU time | 5.85 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:20 AM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338490617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3338490617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2411710783 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1962296662 ps |
| CPU time | 14.83 seconds |
| Started | Oct 03 02:00:44 AM UTC 24 |
| Finished | Oct 03 02:01:00 AM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411710783 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2411710783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.448100334 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 76270819 ps |
| CPU time | 4.56 seconds |
| Started | Oct 03 01:58:18 AM UTC 24 |
| Finished | Oct 03 01:58:24 AM UTC 24 |
| Peak memory | 230980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448100334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.448100334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.2099343428 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 506851995 ps |
| CPU time | 5.07 seconds |
| Started | Oct 03 02:03:20 AM UTC 24 |
| Finished | Oct 03 02:03:26 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099343428 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.2099343428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.449502370 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 108591545 ps |
| CPU time | 3.73 seconds |
| Started | Oct 03 01:59:53 AM UTC 24 |
| Finished | Oct 03 01:59:58 AM UTC 24 |
| Peak memory | 227792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449502370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.449502370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.3580641320 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 99429504 ps |
| CPU time | 4.19 seconds |
| Started | Oct 03 02:02:46 AM UTC 24 |
| Finished | Oct 03 02:02:51 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580641320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3580641320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.2959746489 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 565490357 ps |
| CPU time | 5.41 seconds |
| Started | Oct 03 02:01:25 AM UTC 24 |
| Finished | Oct 03 02:01:31 AM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959746489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2959746489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.4242902682 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 303011630 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 01:59:48 AM UTC 24 |
| Finished | Oct 03 01:59:53 AM UTC 24 |
| Peak memory | 223492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242902682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4242902682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.1861484566 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1299214618 ps |
| CPU time | 5.37 seconds |
| Started | Oct 03 01:59:59 AM UTC 24 |
| Finished | Oct 03 02:00:05 AM UTC 24 |
| Peak memory | 231452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861484566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1861484566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.2092134923 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 243997013 ps |
| CPU time | 13.83 seconds |
| Started | Oct 03 02:00:37 AM UTC 24 |
| Finished | Oct 03 02:00:52 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092134923 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2092134923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.3168626129 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 141223751 ps |
| CPU time | 9.3 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168626129 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3168626129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.355188860 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1169483247 ps |
| CPU time | 9.32 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:44 AM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355188860 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.355188860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.2802502346 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 31867031 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 02:00:13 AM UTC 24 |
| Finished | Oct 03 02:00:17 AM UTC 24 |
| Peak memory | 225936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802502346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2802502346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.4052518813 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3434248167 ps |
| CPU time | 16.97 seconds |
| Started | Oct 03 01:58:11 AM UTC 24 |
| Finished | Oct 03 01:58:29 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052518813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4052518813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.2717223867 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 60903443 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 01:58:16 AM UTC 24 |
| Finished | Oct 03 01:58:20 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717223867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2717223867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_random.2545908746 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 669049142 ps |
| CPU time | 9.78 seconds |
| Started | Oct 03 01:59:09 AM UTC 24 |
| Finished | Oct 03 01:59:20 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545908746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2545908746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.2382177825 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 43060594 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 01:59:09 AM UTC 24 |
| Finished | Oct 03 01:59:13 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382177825 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2382177825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.911035921 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4987051120 ps |
| CPU time | 45.85 seconds |
| Started | Oct 03 02:00:48 AM UTC 24 |
| Finished | Oct 03 02:01:36 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911035921 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.911035921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.4039771114 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4089374791 ps |
| CPU time | 55.08 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:01:50 AM UTC 24 |
| Peak memory | 223464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039771114 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4039771114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.3612881267 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 59687332 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:08 AM UTC 24 |
| Peak memory | 223628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612881267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3612881267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.3579075856 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5065999391 ps |
| CPU time | 67.75 seconds |
| Started | Oct 03 02:01:12 AM UTC 24 |
| Finished | Oct 03 02:02:21 AM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579075856 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3579075856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.3148700877 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 134306315 ps |
| CPU time | 3.04 seconds |
| Started | Oct 03 02:01:45 AM UTC 24 |
| Finished | Oct 03 02:01:49 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148700877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3148700877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.1508247871 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 100636851 ps |
| CPU time | 3.93 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:01:55 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508247871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1508247871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.2884339988 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 332321643 ps |
| CPU time | 4.62 seconds |
| Started | Oct 03 02:00:39 AM UTC 24 |
| Finished | Oct 03 02:00:45 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884339988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2884339988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.2564661792 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 126084284 ps |
| CPU time | 3.84 seconds |
| Started | Oct 03 02:01:37 AM UTC 24 |
| Finished | Oct 03 02:01:42 AM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564661792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2564661792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.1184186551 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 224358763 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 02:02:37 AM UTC 24 |
| Finished | Oct 03 02:02:42 AM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184186551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1184186551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.756473147 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 71730797 ps |
| CPU time | 3.7 seconds |
| Started | Oct 03 01:58:08 AM UTC 24 |
| Finished | Oct 03 01:58:12 AM UTC 24 |
| Peak memory | 231676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756473147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.756473147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.3274261556 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 134005452 ps |
| CPU time | 5.27 seconds |
| Started | Oct 03 01:58:07 AM UTC 24 |
| Finished | Oct 03 01:58:14 AM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274261556 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3274261556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.2155895630 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5851279863 ps |
| CPU time | 136.36 seconds |
| Started | Oct 03 01:59:28 AM UTC 24 |
| Finished | Oct 03 02:01:46 AM UTC 24 |
| Peak memory | 229604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155895630 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2155895630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.1911556933 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 29404075 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:41 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911556933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1911556933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.3501877666 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2467480433 ps |
| CPU time | 46.47 seconds |
| Started | Oct 03 02:00:40 AM UTC 24 |
| Finished | Oct 03 02:01:28 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501877666 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3501877666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.4286571153 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1020830673 ps |
| CPU time | 17.78 seconds |
| Started | Oct 03 02:00:50 AM UTC 24 |
| Finished | Oct 03 02:01:10 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286571153 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4286571153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.2877941550 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 607951814 ps |
| CPU time | 9.75 seconds |
| Started | Oct 03 02:00:54 AM UTC 24 |
| Finished | Oct 03 02:01:05 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877941550 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2877941550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.735457706 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 368098861 ps |
| CPU time | 5.36 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735457706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.735457706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.829735065 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 189970365 ps |
| CPU time | 7.31 seconds |
| Started | Oct 03 02:01:08 AM UTC 24 |
| Finished | Oct 03 02:01:16 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829735065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.829735065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.571760956 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 589605493 ps |
| CPU time | 5.27 seconds |
| Started | Oct 03 01:58:49 AM UTC 24 |
| Finished | Oct 03 01:58:56 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571760956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.571760956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.2714299338 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 212486663 ps |
| CPU time | 7.6 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:34 AM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714299338 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.2714299338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.234068263 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 775945990 ps |
| CPU time | 8.13 seconds |
| Started | Oct 03 02:03:05 AM UTC 24 |
| Finished | Oct 03 02:03:14 AM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234068263 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.234068263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.1629025427 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1935977932 ps |
| CPU time | 4.43 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629025427 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.1629025427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.1540678977 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 848182804 ps |
| CPU time | 7.07 seconds |
| Started | Oct 03 02:03:22 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540678977 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.1540678977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.2588073379 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 306376285 ps |
| CPU time | 10.36 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:32 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588073379 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2588073379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.483665151 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2179087071 ps |
| CPU time | 16.82 seconds |
| Started | Oct 03 01:58:26 AM UTC 24 |
| Finished | Oct 03 01:58:44 AM UTC 24 |
| Peak memory | 261452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483665151 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.483665151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.1457192102 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 64517691 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 02:00:40 AM UTC 24 |
| Finished | Oct 03 02:00:44 AM UTC 24 |
| Peak memory | 217124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457192102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1457192102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.1898649257 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 141247727 ps |
| CPU time | 3.53 seconds |
| Started | Oct 03 01:59:26 AM UTC 24 |
| Finished | Oct 03 01:59:31 AM UTC 24 |
| Peak memory | 227788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898649257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1898649257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.3899634355 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 148279544 ps |
| CPU time | 3.74 seconds |
| Started | Oct 03 02:00:59 AM UTC 24 |
| Finished | Oct 03 02:01:04 AM UTC 24 |
| Peak memory | 227936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899634355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3899634355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.3877578050 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 74651730 ps |
| CPU time | 3.17 seconds |
| Started | Oct 03 01:58:07 AM UTC 24 |
| Finished | Oct 03 01:58:12 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877578050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3877578050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.2359477804 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3774209312 ps |
| CPU time | 48.1 seconds |
| Started | Oct 03 01:58:16 AM UTC 24 |
| Finished | Oct 03 01:59:06 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359477804 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2359477804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.2435454516 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 128118725 ps |
| CPU time | 3.86 seconds |
| Started | Oct 03 01:58:16 AM UTC 24 |
| Finished | Oct 03 01:58:21 AM UTC 24 |
| Peak memory | 217308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435454516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2435454516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.3267153918 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 94098439 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 01:59:20 AM UTC 24 |
| Finished | Oct 03 01:59:24 AM UTC 24 |
| Peak memory | 217484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267153918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3267153918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_random.1040053271 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1096050645 ps |
| CPU time | 11.41 seconds |
| Started | Oct 03 01:59:16 AM UTC 24 |
| Finished | Oct 03 01:59:29 AM UTC 24 |
| Peak memory | 227652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040053271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1040053271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.383968139 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 784605447 ps |
| CPU time | 8.23 seconds |
| Started | Oct 03 02:00:14 AM UTC 24 |
| Finished | Oct 03 02:00:23 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383968139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.383968139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.284327140 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 62962501 ps |
| CPU time | 2.43 seconds |
| Started | Oct 03 02:00:23 AM UTC 24 |
| Finished | Oct 03 02:00:26 AM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284327140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.284327140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.3657984718 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 221411448 ps |
| CPU time | 11.65 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657984718 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3657984718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.2883404787 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4627950509 ps |
| CPU time | 19.65 seconds |
| Started | Oct 03 01:58:30 AM UTC 24 |
| Finished | Oct 03 01:58:51 AM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883404787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2883404787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.3514751868 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 425725810 ps |
| CPU time | 4.21 seconds |
| Started | Oct 03 02:01:08 AM UTC 24 |
| Finished | Oct 03 02:01:13 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514751868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3514751868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_random.1649915173 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 13021520670 ps |
| CPU time | 69.64 seconds |
| Started | Oct 03 02:01:17 AM UTC 24 |
| Finished | Oct 03 02:02:28 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649915173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1649915173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.652482160 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 420683472 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 02:02:01 AM UTC 24 |
| Finished | Oct 03 02:02:07 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652482160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.652482160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.1423801450 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 90208336 ps |
| CPU time | 5.97 seconds |
| Started | Oct 03 02:02:08 AM UTC 24 |
| Finished | Oct 03 02:02:15 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423801450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1423801450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3679127521 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 119777913 ps |
| CPU time | 6.93 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:56 AM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679127521 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3679127521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.2767446455 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 37572243 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 01:58:49 AM UTC 24 |
| Finished | Oct 03 01:58:53 AM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767446455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2767446455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.2111017389 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 383180019 ps |
| CPU time | 5.11 seconds |
| Started | Oct 03 02:03:00 AM UTC 24 |
| Finished | Oct 03 02:03:06 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111017389 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2111017389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1101357904 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 138342065 ps |
| CPU time | 6.85 seconds |
| Started | Oct 03 02:03:00 AM UTC 24 |
| Finished | Oct 03 02:03:07 AM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101357904 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1101357904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1535526617 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 67847285 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:01 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535526617 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1535526617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3339086229 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 180616222 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 02:03:00 AM UTC 24 |
| Finished | Oct 03 02:03:03 AM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3339086229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w ith_rand_reset.3339086229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.4196005373 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 190692226 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 02:03:00 AM UTC 24 |
| Finished | Oct 03 02:03:02 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196005373 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4196005373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.1556596323 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 18773438 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:01 AM UTC 24 |
| Peak memory | 214224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556596323 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1556596323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1748991260 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 76562015 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 02:03:00 AM UTC 24 |
| Finished | Oct 03 02:03:03 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748991260 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1748991260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3081085952 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 236147713 ps |
| CPU time | 4.72 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:04 AM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081085952 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.3081085952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4010876642 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 478941523 ps |
| CPU time | 17.29 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:17 AM UTC 24 |
| Peak memory | 232108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010876642 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.4010876642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.3461981137 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 81181751 ps |
| CPU time | 4.34 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:04 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461981137 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3461981137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.3327637487 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 722349147 ps |
| CPU time | 10.26 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:10 AM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327637487 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.3327637487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.2710483759 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 3150268550 ps |
| CPU time | 10.3 seconds |
| Started | Oct 03 02:03:02 AM UTC 24 |
| Finished | Oct 03 02:03:14 AM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710483759 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2710483759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1745543114 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1036785790 ps |
| CPU time | 11.55 seconds |
| Started | Oct 03 02:03:02 AM UTC 24 |
| Finished | Oct 03 02:03:15 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745543114 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1745543114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.222664533 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 78589718 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 02:03:01 AM UTC 24 |
| Finished | Oct 03 02:03:04 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222664533 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.222664533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3353438469 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 88619524 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 02:03:04 AM UTC 24 |
| Finished | Oct 03 02:03:07 AM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3353438469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.3353438469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.1663705333 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 98327045 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 02:03:02 AM UTC 24 |
| Finished | Oct 03 02:03:05 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663705333 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1663705333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.3386687159 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 13275256 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 02:03:01 AM UTC 24 |
| Finished | Oct 03 02:03:03 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386687159 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3386687159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1753678917 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 388320239 ps |
| CPU time | 4.32 seconds |
| Started | Oct 03 02:03:03 AM UTC 24 |
| Finished | Oct 03 02:03:09 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753678917 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.1753678917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.50412358 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 329681867 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 02:03:01 AM UTC 24 |
| Finished | Oct 03 02:03:05 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50412358 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.50412358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1976017105 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 20693824 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 02:03:24 AM UTC 24 |
| Finished | Oct 03 02:03:27 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1976017105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.1976017105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.528203623 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 14739849 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:26 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528203623 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.528203623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.508277586 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 33020810 ps |
| CPU time | 0.79 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508277586 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.508277586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1718428492 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 537107937 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:27 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718428492 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.1718428492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3631689971 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 341545233 ps |
| CPU time | 2.75 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:27 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631689971 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.3631689971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2466324316 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 321148841 ps |
| CPU time | 4.53 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 231972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466324316 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.2466324316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.2874912482 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 41882640 ps |
| CPU time | 2.75 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:27 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874912482 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2874912482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.440861844 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 97029380 ps |
| CPU time | 4.99 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440861844 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.440861844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3718823568 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 50917514 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3718823568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.3718823568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3920577601 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 88784442 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920577601 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3920577601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.3829301328 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 10283716 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:28 AM UTC 24 |
| Peak memory | 212336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829301328 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3829301328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4220245220 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 33651869 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220245220 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.4220245220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1411562322 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 98948219 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 02:03:24 AM UTC 24 |
| Finished | Oct 03 02:03:28 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411562322 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.1411562322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2619076079 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 737878239 ps |
| CPU time | 5.79 seconds |
| Started | Oct 03 02:03:24 AM UTC 24 |
| Finished | Oct 03 02:03:31 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619076079 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.2619076079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2679574528 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 33279548 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679574528 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2679574528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4195684913 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 75435233 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 02:03:28 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4195684913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_ with_rand_reset.4195684913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.1690880402 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 41765390 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 02:03:27 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690880402 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1690880402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.2391955603 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 22595047 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 02:03:27 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391955603 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2391955603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3528027626 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 109830424 ps |
| CPU time | 3.4 seconds |
| Started | Oct 03 02:03:27 AM UTC 24 |
| Finished | Oct 03 02:03:32 AM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528027626 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3528027626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1415011153 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 116385092 ps |
| CPU time | 3.96 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:31 AM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415011153 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.1415011153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1795906400 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1313235570 ps |
| CPU time | 12.3 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:40 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795906400 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.1795906400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.2064646503 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 148754113 ps |
| CPU time | 4.3 seconds |
| Started | Oct 03 02:03:26 AM UTC 24 |
| Finished | Oct 03 02:03:32 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064646503 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2064646503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.497723512 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 279396368 ps |
| CPU time | 7.55 seconds |
| Started | Oct 03 02:03:27 AM UTC 24 |
| Finished | Oct 03 02:03:36 AM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497723512 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.497723512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1618810695 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 233706045 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 02:03:30 AM UTC 24 |
| Finished | Oct 03 02:03:33 AM UTC 24 |
| Peak memory | 230932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1618810695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.1618810695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.87479470 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 17917904 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 02:03:30 AM UTC 24 |
| Finished | Oct 03 02:03:33 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87479470 -assert nopostproc +UVM_TESTNAME=keymgr_ base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.87479470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.1107325810 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 32302833 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 02:03:29 AM UTC 24 |
| Finished | Oct 03 02:03:31 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107325810 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1107325810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3456112402 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 244560210 ps |
| CPU time | 3.18 seconds |
| Started | Oct 03 02:03:30 AM UTC 24 |
| Finished | Oct 03 02:03:35 AM UTC 24 |
| Peak memory | 215156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456112402 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.3456112402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4198305640 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 765582494 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 02:03:28 AM UTC 24 |
| Finished | Oct 03 02:03:32 AM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198305640 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.4198305640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2311049013 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 461985891 ps |
| CPU time | 5.37 seconds |
| Started | Oct 03 02:03:29 AM UTC 24 |
| Finished | Oct 03 02:03:35 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311049013 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.2311049013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.3186578004 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 282597632 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 02:03:29 AM UTC 24 |
| Finished | Oct 03 02:03:33 AM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186578004 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3186578004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.826976191 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 349173211 ps |
| CPU time | 4.21 seconds |
| Started | Oct 03 02:03:29 AM UTC 24 |
| Finished | Oct 03 02:03:34 AM UTC 24 |
| Peak memory | 225420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826976191 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.826976191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2969141359 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 53895550 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:33 AM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2969141359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.2969141359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.3318170746 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 19010064 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:33 AM UTC 24 |
| Peak memory | 212288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318170746 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3318170746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.3946002829 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 44354111 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:33 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946002829 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3946002829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2705983208 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 60273145 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:34 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705983208 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.2705983208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.998257917 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 127521985 ps |
| CPU time | 3.95 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:36 AM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998257917 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.998257917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2190653101 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 800438717 ps |
| CPU time | 7.29 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:39 AM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190653101 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.2190653101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.689646887 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 118982033 ps |
| CPU time | 5.89 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:38 AM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689646887 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.689646887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.2812975541 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 176347022 ps |
| CPU time | 5.52 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:37 AM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812975541 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.2812975541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3625978382 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 206327557 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:36 AM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3625978382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_ with_rand_reset.3625978382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.421859592 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 55085953 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:35 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421859592 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.421859592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.3036783335 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 7705289 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:35 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036783335 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3036783335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2418949242 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 123997817 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:37 AM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418949242 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.2418949242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3123580852 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 241078723 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:35 AM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123580852 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.3123580852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1369548041 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3917952694 ps |
| CPU time | 13.16 seconds |
| Started | Oct 03 02:03:31 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369548041 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.1369548041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.2631092576 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 92708777 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:36 AM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631092576 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2631092576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.852226107 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 223535312 ps |
| CPU time | 3.69 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:37 AM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852226107 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.852226107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.417012997 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 51374050 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:36 AM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=417012997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_w ith_rand_reset.417012997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.2157853830 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 24708652 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:37 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157853830 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2157853830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3114730695 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 22145759 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:36 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114730695 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3114730695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4285921195 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 112713852 ps |
| CPU time | 4.35 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:39 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285921195 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.4285921195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4184026590 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 224210363 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 02:03:32 AM UTC 24 |
| Finished | Oct 03 02:03:35 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184026590 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.4184026590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.416321582 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 628017890 ps |
| CPU time | 7.32 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:42 AM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416321582 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.416321582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1643961284 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 31449432 ps |
| CPU time | 2.57 seconds |
| Started | Oct 03 02:03:34 AM UTC 24 |
| Finished | Oct 03 02:03:37 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643961284 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1643961284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.737736081 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 35642204 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=737736081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_w ith_rand_reset.737736081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1580445790 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 19347740 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 02:03:36 AM UTC 24 |
| Finished | Oct 03 02:03:38 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580445790 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1580445790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3857348332 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 10408757 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 02:03:36 AM UTC 24 |
| Finished | Oct 03 02:03:38 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857348332 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3857348332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3115383809 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 32221158 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 02:03:36 AM UTC 24 |
| Finished | Oct 03 02:03:39 AM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115383809 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.3115383809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3474541389 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 95965038 ps |
| CPU time | 3.5 seconds |
| Started | Oct 03 02:03:35 AM UTC 24 |
| Finished | Oct 03 02:03:40 AM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474541389 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.3474541389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2675100995 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 1604980525 ps |
| CPU time | 14.19 seconds |
| Started | Oct 03 02:03:35 AM UTC 24 |
| Finished | Oct 03 02:03:51 AM UTC 24 |
| Peak memory | 225216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675100995 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.2675100995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.2270770963 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 201165508 ps |
| CPU time | 3.27 seconds |
| Started | Oct 03 02:03:36 AM UTC 24 |
| Finished | Oct 03 02:03:40 AM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270770963 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2270770963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.659583188 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 997631772 ps |
| CPU time | 5.39 seconds |
| Started | Oct 03 02:03:36 AM UTC 24 |
| Finished | Oct 03 02:03:42 AM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659583188 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.659583188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2769815850 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 45576065 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2769815850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.2769815850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.318527704 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 168442459 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:40 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318527704 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.318527704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1126963854 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 11101729 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:40 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126963854 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1126963854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2502750743 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 481165179 ps |
| CPU time | 4.14 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502750743 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.2502750743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2064390374 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 84623925 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064390374 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.2064390374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3029819758 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 1830800586 ps |
| CPU time | 9.97 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:49 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029819758 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.3029819758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.1048817595 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 50648208 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048817595 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1048817595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3829530500 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2116194147 ps |
| CPU time | 5.04 seconds |
| Started | Oct 03 02:03:37 AM UTC 24 |
| Finished | Oct 03 02:03:44 AM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829530500 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.3829530500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2903927270 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 26120903 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2903927270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.2903927270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3877925499 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 75533805 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:42 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877925499 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3877925499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3726446381 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 9202850 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726446381 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3726446381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4013910560 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 738681709 ps |
| CPU time | 3.93 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:44 AM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013910560 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.4013910560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3002836302 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 38435614 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 02:03:38 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002836302 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.3002836302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.89742860 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 394019912 ps |
| CPU time | 9.44 seconds |
| Started | Oct 03 02:03:38 AM UTC 24 |
| Finished | Oct 03 02:03:49 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89742860 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.89742860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.2648408403 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 344485030 ps |
| CPU time | 3.04 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 225212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648408403 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2648408403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.175251298 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 485421052 ps |
| CPU time | 6.27 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:46 AM UTC 24 |
| Peak memory | 225196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175251298 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.175251298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.2397432724 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 1928956270 ps |
| CPU time | 9.74 seconds |
| Started | Oct 03 02:03:06 AM UTC 24 |
| Finished | Oct 03 02:03:17 AM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397432724 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2397432724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2622779921 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1039355893 ps |
| CPU time | 14.58 seconds |
| Started | Oct 03 02:03:05 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622779921 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2622779921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1365871974 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 104098570 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 02:03:05 AM UTC 24 |
| Finished | Oct 03 02:03:07 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365871974 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1365871974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1495299034 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 82215571 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 02:03:06 AM UTC 24 |
| Finished | Oct 03 02:03:10 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1495299034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.1495299034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.972398591 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 11651765 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 02:03:05 AM UTC 24 |
| Finished | Oct 03 02:03:08 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972398591 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.972398591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.1726182113 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 8155143 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 02:03:05 AM UTC 24 |
| Finished | Oct 03 02:03:07 AM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726182113 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1726182113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2358709609 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 141332055 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 02:03:06 AM UTC 24 |
| Finished | Oct 03 02:03:09 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358709609 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.2358709609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3406847773 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 165098835 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 02:03:04 AM UTC 24 |
| Finished | Oct 03 02:03:08 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406847773 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.3406847773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1871120338 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 162734010 ps |
| CPU time | 9.92 seconds |
| Started | Oct 03 02:03:04 AM UTC 24 |
| Finished | Oct 03 02:03:15 AM UTC 24 |
| Peak memory | 231900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871120338 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.1871120338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3534226044 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 37770005 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 02:03:04 AM UTC 24 |
| Finished | Oct 03 02:03:07 AM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534226044 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3534226044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.658750580 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 17397402 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 02:03:39 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658750580 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.658750580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.193676841 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 46810239 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 02:03:40 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193676841 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.193676841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.858997974 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 35377101 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 02:03:41 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858997974 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.858997974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.146777823 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 15264712 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 02:03:41 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146777823 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.146777823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.87224716 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 33798321 ps |
| CPU time | 0.89 seconds |
| Started | Oct 03 02:03:41 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87224716 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.87224716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.424539027 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 39674767 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:03:41 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424539027 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.424539027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.1672791197 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 12062921 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 02:03:41 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672791197 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1672791197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3476710365 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 13976120 ps |
| CPU time | 0.89 seconds |
| Started | Oct 03 02:03:41 AM UTC 24 |
| Finished | Oct 03 02:03:43 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476710365 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3476710365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3703102161 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 15217108 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703102161 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3703102161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.1990825901 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 32555383 ps |
| CPU time | 0.93 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990825901 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1990825901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.2796353521 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4068729183 ps |
| CPU time | 14.68 seconds |
| Started | Oct 03 02:03:09 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796353521 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2796353521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1272547578 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 852476618 ps |
| CPU time | 32.59 seconds |
| Started | Oct 03 02:03:08 AM UTC 24 |
| Finished | Oct 03 02:03:42 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272547578 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1272547578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3145870749 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 81839402 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 02:03:08 AM UTC 24 |
| Finished | Oct 03 02:03:10 AM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145870749 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3145870749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.271890695 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 89329883 ps |
| CPU time | 2.24 seconds |
| Started | Oct 03 02:03:09 AM UTC 24 |
| Finished | Oct 03 02:03:12 AM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=271890695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_wi th_rand_reset.271890695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1366484211 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 102746140 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 02:03:08 AM UTC 24 |
| Finished | Oct 03 02:03:10 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366484211 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1366484211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.3844728300 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 26630393 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 02:03:08 AM UTC 24 |
| Finished | Oct 03 02:03:10 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844728300 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3844728300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1498511321 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 201565178 ps |
| CPU time | 2.75 seconds |
| Started | Oct 03 02:03:09 AM UTC 24 |
| Finished | Oct 03 02:03:13 AM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498511321 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.1498511321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2079467686 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 146353502 ps |
| CPU time | 5.8 seconds |
| Started | Oct 03 02:03:06 AM UTC 24 |
| Finished | Oct 03 02:03:13 AM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079467686 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.2079467686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.497549619 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 86304640 ps |
| CPU time | 6.15 seconds |
| Started | Oct 03 02:03:06 AM UTC 24 |
| Finished | Oct 03 02:03:14 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497549619 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.497549619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.791698075 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 30446281 ps |
| CPU time | 2.42 seconds |
| Started | Oct 03 02:03:08 AM UTC 24 |
| Finished | Oct 03 02:03:11 AM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791698075 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.791698075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.1478453385 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 101747945 ps |
| CPU time | 3.68 seconds |
| Started | Oct 03 02:03:08 AM UTC 24 |
| Finished | Oct 03 02:03:12 AM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478453385 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.1478453385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.736404123 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 46562291 ps |
| CPU time | 0.91 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736404123 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.736404123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2608345823 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 21741766 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608345823 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2608345823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1978185346 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 20306323 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978185346 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1978185346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.251343932 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 79872234 ps |
| CPU time | 0.93 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251343932 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.251343932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1270154482 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 9324542 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270154482 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1270154482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1704243211 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15096096 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704243211 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1704243211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3384042719 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 8497675 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:03:42 AM UTC 24 |
| Finished | Oct 03 02:03:45 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384042719 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3384042719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.2292788271 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 14504366 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292788271 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2292788271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2163517982 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 23770091 ps |
| CPU time | 0.76 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163517982 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2163517982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.1755350675 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 15868701 ps |
| CPU time | 0.86 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755350675 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1755350675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.3485064756 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 241769848 ps |
| CPU time | 9.46 seconds |
| Started | Oct 03 02:03:12 AM UTC 24 |
| Finished | Oct 03 02:03:22 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485064756 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3485064756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3521945558 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 134163284 ps |
| CPU time | 7.64 seconds |
| Started | Oct 03 02:03:12 AM UTC 24 |
| Finished | Oct 03 02:03:20 AM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521945558 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3521945558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.738849671 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 27555693 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 02:03:10 AM UTC 24 |
| Finished | Oct 03 02:03:13 AM UTC 24 |
| Peak memory | 212332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738849671 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.738849671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.658280899 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 59850948 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 02:03:12 AM UTC 24 |
| Finished | Oct 03 02:03:15 AM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=658280899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_wi th_rand_reset.658280899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.3962194423 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 15177230 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 02:03:12 AM UTC 24 |
| Finished | Oct 03 02:03:14 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962194423 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3962194423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.2151321826 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 24431915 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 02:03:10 AM UTC 24 |
| Finished | Oct 03 02:03:13 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151321826 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2151321826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1371503632 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 250762554 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 02:03:12 AM UTC 24 |
| Finished | Oct 03 02:03:15 AM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371503632 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.1371503632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2601416519 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1672391164 ps |
| CPU time | 6.17 seconds |
| Started | Oct 03 02:03:09 AM UTC 24 |
| Finished | Oct 03 02:03:16 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601416519 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.2601416519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1004128506 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 911797605 ps |
| CPU time | 18.61 seconds |
| Started | Oct 03 02:03:10 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004128506 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.1004128506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.828251650 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 113747870 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 02:03:10 AM UTC 24 |
| Finished | Oct 03 02:03:14 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828251650 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.828251650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2041097308 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 16232368 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041097308 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2041097308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2132162766 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 11814089 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132162766 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2132162766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2104507135 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 41169952 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104507135 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2104507135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2299877041 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 31045605 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 02:03:44 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299877041 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2299877041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3589382572 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 16891441 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589382572 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3589382572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.1193201611 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 11011555 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193201611 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1193201611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.3847333260 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 9916207 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847333260 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3847333260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.2694688042 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 142001398 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694688042 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2694688042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1941673167 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 22819145 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941673167 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1941673167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2432140788 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 12715437 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 02:03:45 AM UTC 24 |
| Finished | Oct 03 02:03:47 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432140788 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2432140788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1873422025 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 21249498 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 02:03:14 AM UTC 24 |
| Finished | Oct 03 02:03:17 AM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1873422025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.1873422025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1551517944 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 39609413 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 02:03:14 AM UTC 24 |
| Finished | Oct 03 02:03:17 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551517944 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1551517944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.711055803 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 12691218 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 02:03:14 AM UTC 24 |
| Finished | Oct 03 02:03:17 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711055803 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.711055803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1937992644 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 156408214 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 02:03:14 AM UTC 24 |
| Finished | Oct 03 02:03:18 AM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937992644 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1937992644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3499947161 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 83750022 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 02:03:13 AM UTC 24 |
| Finished | Oct 03 02:03:18 AM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499947161 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.3499947161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2048642697 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 844330268 ps |
| CPU time | 14.2 seconds |
| Started | Oct 03 02:03:13 AM UTC 24 |
| Finished | Oct 03 02:03:28 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048642697 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.2048642697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.3848935796 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 87327886 ps |
| CPU time | 2.24 seconds |
| Started | Oct 03 02:03:13 AM UTC 24 |
| Finished | Oct 03 02:03:16 AM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848935796 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3848935796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.2613380962 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 865204591 ps |
| CPU time | 9.21 seconds |
| Started | Oct 03 02:03:14 AM UTC 24 |
| Finished | Oct 03 02:03:24 AM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613380962 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.2613380962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1093124512 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 20060498 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 02:03:17 AM UTC 24 |
| Finished | Oct 03 02:03:20 AM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1093124512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w ith_rand_reset.1093124512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3055129228 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 16263573 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:18 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055129228 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3055129228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.3396930831 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 84670373 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:18 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396930831 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3396930831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.445704702 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 418021178 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:20 AM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445704702 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.445704702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3498097191 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 114578206 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:19 AM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498097191 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.3498097191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2199068061 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 175704643 ps |
| CPU time | 6.56 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:23 AM UTC 24 |
| Peak memory | 225988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199068061 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.2199068061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.3812431282 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 75686846 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 02:03:16 AM UTC 24 |
| Finished | Oct 03 02:03:20 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812431282 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3812431282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4183262149 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 98340026 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 02:03:19 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4183262149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w ith_rand_reset.4183262149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.3322690663 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 98616987 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 02:03:19 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322690663 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3322690663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.4154258315 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 12502404 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 02:03:18 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154258315 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4154258315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3859830885 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 85379293 ps |
| CPU time | 3.16 seconds |
| Started | Oct 03 02:03:19 AM UTC 24 |
| Finished | Oct 03 02:03:23 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859830885 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.3859830885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2440940384 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 260221025 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 02:03:17 AM UTC 24 |
| Finished | Oct 03 02:03:20 AM UTC 24 |
| Peak memory | 225972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440940384 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.2440940384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1396563685 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 744394078 ps |
| CPU time | 7.33 seconds |
| Started | Oct 03 02:03:17 AM UTC 24 |
| Finished | Oct 03 02:03:26 AM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396563685 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.1396563685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.3455835028 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 43541751 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 02:03:17 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455835028 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3455835028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.208364028 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 103653694 ps |
| CPU time | 2.98 seconds |
| Started | Oct 03 02:03:17 AM UTC 24 |
| Finished | Oct 03 02:03:21 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208364028 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.208364028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3923799501 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 58133020 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 02:03:21 AM UTC 24 |
| Finished | Oct 03 02:03:24 AM UTC 24 |
| Peak memory | 225944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3923799501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w ith_rand_reset.3923799501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.2557048880 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 76802388 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 02:03:20 AM UTC 24 |
| Finished | Oct 03 02:03:22 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557048880 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2557048880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.3784333387 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 49312560 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 02:03:20 AM UTC 24 |
| Finished | Oct 03 02:03:22 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784333387 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3784333387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.175054768 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 52455381 ps |
| CPU time | 2.58 seconds |
| Started | Oct 03 02:03:21 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175054768 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.175054768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3015827446 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 397934391 ps |
| CPU time | 9.7 seconds |
| Started | Oct 03 02:03:19 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 229740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015827446 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.3015827446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1195271660 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 473743270 ps |
| CPU time | 10.28 seconds |
| Started | Oct 03 02:03:19 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195271660 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.1195271660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.761353123 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 594266084 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 02:03:19 AM UTC 24 |
| Finished | Oct 03 02:03:22 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761353123 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.761353123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.78053192 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 15696315 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=78053192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_wit h_rand_reset.78053192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.3207425874 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 23934391 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 212336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207425874 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3207425874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.423680266 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 15253162 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 02:03:22 AM UTC 24 |
| Finished | Oct 03 02:03:24 AM UTC 24 |
| Peak memory | 212392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423680266 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.423680266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4071736828 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 249587937 ps |
| CPU time | 2.3 seconds |
| Started | Oct 03 02:03:23 AM UTC 24 |
| Finished | Oct 03 02:03:26 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071736828 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.4071736828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.959248656 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 255471405 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 02:03:21 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959248656 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.959248656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1492076352 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1007907208 ps |
| CPU time | 7.97 seconds |
| Started | Oct 03 02:03:21 AM UTC 24 |
| Finished | Oct 03 02:03:30 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492076352 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.1492076352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.2056842864 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 124816400 ps |
| CPU time | 2.73 seconds |
| Started | Oct 03 02:03:21 AM UTC 24 |
| Finished | Oct 03 02:03:25 AM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056842864 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2056842864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_random.2704696630 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 75909627 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 01:58:07 AM UTC 24 |
| Finished | Oct 03 01:58:12 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704696630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2704696630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.2970190354 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 702286752 ps |
| CPU time | 10.5 seconds |
| Started | Oct 03 01:58:05 AM UTC 24 |
| Finished | Oct 03 01:58:17 AM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970190354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2970190354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.3887882453 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 114720167 ps |
| CPU time | 3.66 seconds |
| Started | Oct 03 01:58:07 AM UTC 24 |
| Finished | Oct 03 01:58:12 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887882453 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3887882453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.1921597932 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 32650343 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 01:58:06 AM UTC 24 |
| Finished | Oct 03 01:58:09 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921597932 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1921597932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.3283407271 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 329184630 ps |
| CPU time | 3.83 seconds |
| Started | Oct 03 01:58:10 AM UTC 24 |
| Finished | Oct 03 01:58:15 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283407271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3283407271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.1820013846 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 479146925 ps |
| CPU time | 3.95 seconds |
| Started | Oct 03 01:58:05 AM UTC 24 |
| Finished | Oct 03 01:58:10 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820013846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1820013846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.262021122 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 16297719 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:23 AM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262021122 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.262021122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_random.3572356368 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 113149055 ps |
| CPU time | 6.55 seconds |
| Started | Oct 03 01:58:16 AM UTC 24 |
| Finished | Oct 03 01:58:24 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572356368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3572356368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.3165208916 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1136525972 ps |
| CPU time | 4.96 seconds |
| Started | Oct 03 01:58:13 AM UTC 24 |
| Finished | Oct 03 01:58:19 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165208916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3165208916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.2126719521 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 543037811 ps |
| CPU time | 5.38 seconds |
| Started | Oct 03 01:58:14 AM UTC 24 |
| Finished | Oct 03 01:58:21 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126719521 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2126719521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.1672739224 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 470351941 ps |
| CPU time | 5.83 seconds |
| Started | Oct 03 01:58:14 AM UTC 24 |
| Finished | Oct 03 01:58:21 AM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672739224 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1672739224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.3179984352 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 317849512 ps |
| CPU time | 9.5 seconds |
| Started | Oct 03 01:58:16 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 217552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179984352 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3179984352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.180684777 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 115650439 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 01:58:20 AM UTC 24 |
| Finished | Oct 03 01:58:24 AM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180684777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.180684777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3501903550 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 885368144 ps |
| CPU time | 15.78 seconds |
| Started | Oct 03 01:58:13 AM UTC 24 |
| Finished | Oct 03 01:58:31 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501903550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3501903550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.1642328946 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 102683197 ps |
| CPU time | 5.4 seconds |
| Started | Oct 03 01:58:17 AM UTC 24 |
| Finished | Oct 03 01:58:24 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642328946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1642328946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.2150428347 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 11141001 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 01:59:13 AM UTC 24 |
| Finished | Oct 03 01:59:15 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150428347 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2150428347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.1814263586 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 460349900 ps |
| CPU time | 5.71 seconds |
| Started | Oct 03 01:59:12 AM UTC 24 |
| Finished | Oct 03 01:59:18 AM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814263586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1814263586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.3056844042 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 59288076 ps |
| CPU time | 2.93 seconds |
| Started | Oct 03 01:59:10 AM UTC 24 |
| Finished | Oct 03 01:59:14 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056844042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3056844042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.3508781960 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 282636797 ps |
| CPU time | 4.41 seconds |
| Started | Oct 03 01:59:10 AM UTC 24 |
| Finished | Oct 03 01:59:16 AM UTC 24 |
| Peak memory | 231540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508781960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3508781960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.2446191620 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1112205774 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 01:59:12 AM UTC 24 |
| Finished | Oct 03 01:59:16 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446191620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2446191620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.865416490 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 161446361 ps |
| CPU time | 7.34 seconds |
| Started | Oct 03 01:59:10 AM UTC 24 |
| Finished | Oct 03 01:59:19 AM UTC 24 |
| Peak memory | 223492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865416490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.865416490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.1616289001 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 785127329 ps |
| CPU time | 6.9 seconds |
| Started | Oct 03 01:59:09 AM UTC 24 |
| Finished | Oct 03 01:59:17 AM UTC 24 |
| Peak memory | 216484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616289001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1616289001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.179205278 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1902719123 ps |
| CPU time | 16.58 seconds |
| Started | Oct 03 01:59:09 AM UTC 24 |
| Finished | Oct 03 01:59:27 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179205278 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.179205278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.1007329488 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 387313282 ps |
| CPU time | 7.51 seconds |
| Started | Oct 03 01:59:09 AM UTC 24 |
| Finished | Oct 03 01:59:17 AM UTC 24 |
| Peak memory | 214556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007329488 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1007329488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.1918939302 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 71353077 ps |
| CPU time | 4.37 seconds |
| Started | Oct 03 01:59:12 AM UTC 24 |
| Finished | Oct 03 01:59:17 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918939302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1918939302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1005282732 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5139034427 ps |
| CPU time | 13.82 seconds |
| Started | Oct 03 01:59:08 AM UTC 24 |
| Finished | Oct 03 01:59:23 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005282732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1005282732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.2787909115 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4465462600 ps |
| CPU time | 42.23 seconds |
| Started | Oct 03 01:59:12 AM UTC 24 |
| Finished | Oct 03 01:59:55 AM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787909115 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2787909115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.168330006 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 836937533 ps |
| CPU time | 22.06 seconds |
| Started | Oct 03 01:59:13 AM UTC 24 |
| Finished | Oct 03 01:59:36 AM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=168330006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr _stress_all_with_rand_reset.168330006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.1202047293 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 334758963 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 01:59:10 AM UTC 24 |
| Finished | Oct 03 01:59:16 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202047293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1202047293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.3785710108 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 115460298 ps |
| CPU time | 4.48 seconds |
| Started | Oct 03 01:59:12 AM UTC 24 |
| Finished | Oct 03 01:59:17 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785710108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3785710108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.439729098 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 11756496 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:59:21 AM UTC 24 |
| Finished | Oct 03 01:59:25 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439729098 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.439729098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.2089019110 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 204391928 ps |
| CPU time | 4.24 seconds |
| Started | Oct 03 01:59:18 AM UTC 24 |
| Finished | Oct 03 01:59:23 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089019110 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2089019110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.3821711974 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 661253332 ps |
| CPU time | 16.91 seconds |
| Started | Oct 03 01:59:18 AM UTC 24 |
| Finished | Oct 03 01:59:36 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821711974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3821711974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.3830696225 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 20430615612 ps |
| CPU time | 60.03 seconds |
| Started | Oct 03 01:59:19 AM UTC 24 |
| Finished | Oct 03 02:00:21 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830696225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3830696225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.2567915179 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 132240757 ps |
| CPU time | 3.65 seconds |
| Started | Oct 03 01:59:19 AM UTC 24 |
| Finished | Oct 03 01:59:23 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567915179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2567915179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.1585354441 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 88343839 ps |
| CPU time | 4.69 seconds |
| Started | Oct 03 01:59:18 AM UTC 24 |
| Finished | Oct 03 01:59:24 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585354441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1585354441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.1689765076 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 127277709 ps |
| CPU time | 5.75 seconds |
| Started | Oct 03 01:59:14 AM UTC 24 |
| Finished | Oct 03 01:59:21 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689765076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1689765076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.2269878376 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 41488128 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 01:59:16 AM UTC 24 |
| Finished | Oct 03 01:59:19 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269878376 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2269878376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.2654801076 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 134409792 ps |
| CPU time | 6.98 seconds |
| Started | Oct 03 01:59:15 AM UTC 24 |
| Finished | Oct 03 01:59:23 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654801076 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2654801076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.425932405 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 247970534 ps |
| CPU time | 7.72 seconds |
| Started | Oct 03 01:59:16 AM UTC 24 |
| Finished | Oct 03 01:59:25 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425932405 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.425932405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.1116083426 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 698090182 ps |
| CPU time | 4.21 seconds |
| Started | Oct 03 01:59:20 AM UTC 24 |
| Finished | Oct 03 01:59:25 AM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116083426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1116083426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.2519399628 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 303790469 ps |
| CPU time | 4.25 seconds |
| Started | Oct 03 01:59:13 AM UTC 24 |
| Finished | Oct 03 01:59:18 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519399628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2519399628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.3273189180 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1195614600 ps |
| CPU time | 12.85 seconds |
| Started | Oct 03 01:59:20 AM UTC 24 |
| Finished | Oct 03 01:59:34 AM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3273189180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg r_stress_all_with_rand_reset.3273189180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.1113921388 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 775776542 ps |
| CPU time | 7.91 seconds |
| Started | Oct 03 01:59:18 AM UTC 24 |
| Finished | Oct 03 01:59:27 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113921388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1113921388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.1162012398 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 317737539 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 01:59:20 AM UTC 24 |
| Finished | Oct 03 01:59:23 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162012398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1162012398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.209014691 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 75767983 ps |
| CPU time | 0.94 seconds |
| Started | Oct 03 01:59:28 AM UTC 24 |
| Finished | Oct 03 01:59:30 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209014691 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.209014691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.2380620069 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 183867897 ps |
| CPU time | 10.52 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:37 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380620069 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2380620069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.3300130180 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 58593295 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:28 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300130180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3300130180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.2909103940 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 23488130 ps |
| CPU time | 2.46 seconds |
| Started | Oct 03 01:59:26 AM UTC 24 |
| Finished | Oct 03 01:59:30 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909103940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2909103940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.304852948 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 61981640 ps |
| CPU time | 4.01 seconds |
| Started | Oct 03 01:59:26 AM UTC 24 |
| Finished | Oct 03 01:59:31 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304852948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.304852948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.2189548518 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 143278318 ps |
| CPU time | 4.17 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:30 AM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189548518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2189548518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_random.4011103733 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 343750257 ps |
| CPU time | 5.43 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:31 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011103733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4011103733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.3777838202 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 194899034 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 01:59:23 AM UTC 24 |
| Finished | Oct 03 01:59:28 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777838202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3777838202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.2214361310 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 140449234 ps |
| CPU time | 2.76 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:29 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214361310 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2214361310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.1829121424 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 73246937 ps |
| CPU time | 3.63 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:30 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829121424 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1829121424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.527942963 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 73457254 ps |
| CPU time | 3.78 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:30 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527942963 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.527942963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.1672486757 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2214228688 ps |
| CPU time | 15.76 seconds |
| Started | Oct 03 01:59:26 AM UTC 24 |
| Finished | Oct 03 01:59:43 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672486757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1672486757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.1580838325 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 450074626 ps |
| CPU time | 8.35 seconds |
| Started | Oct 03 01:59:21 AM UTC 24 |
| Finished | Oct 03 01:59:32 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580838325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1580838325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.2335240355 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 240123042 ps |
| CPU time | 4.21 seconds |
| Started | Oct 03 01:59:25 AM UTC 24 |
| Finished | Oct 03 01:59:30 AM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335240355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2335240355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.832460235 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 184180313 ps |
| CPU time | 2.73 seconds |
| Started | Oct 03 01:59:27 AM UTC 24 |
| Finished | Oct 03 01:59:31 AM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832460235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.832460235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.660902948 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 107680080 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:59:33 AM UTC 24 |
| Finished | Oct 03 01:59:35 AM UTC 24 |
| Peak memory | 212492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660902948 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.660902948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.1414560739 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 269539617 ps |
| CPU time | 14.67 seconds |
| Started | Oct 03 01:59:30 AM UTC 24 |
| Finished | Oct 03 01:59:46 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414560739 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1414560739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.2804131645 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 253309441 ps |
| CPU time | 4.35 seconds |
| Started | Oct 03 01:59:30 AM UTC 24 |
| Finished | Oct 03 01:59:36 AM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804131645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2804131645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.3157354617 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 68658769 ps |
| CPU time | 4.37 seconds |
| Started | Oct 03 01:59:32 AM UTC 24 |
| Finished | Oct 03 01:59:37 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157354617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3157354617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.593675631 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 93250718 ps |
| CPU time | 4.42 seconds |
| Started | Oct 03 01:59:32 AM UTC 24 |
| Finished | Oct 03 01:59:37 AM UTC 24 |
| Peak memory | 223496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593675631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.593675631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.268208486 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1296378608 ps |
| CPU time | 31.44 seconds |
| Started | Oct 03 01:59:31 AM UTC 24 |
| Finished | Oct 03 02:00:04 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268208486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.268208486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_random.1381860022 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 196356450 ps |
| CPU time | 4.42 seconds |
| Started | Oct 03 01:59:30 AM UTC 24 |
| Finished | Oct 03 01:59:36 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381860022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1381860022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.1636277765 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 271839125 ps |
| CPU time | 6.17 seconds |
| Started | Oct 03 01:59:29 AM UTC 24 |
| Finished | Oct 03 01:59:36 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636277765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1636277765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.3306743134 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 104365581 ps |
| CPU time | 3.19 seconds |
| Started | Oct 03 01:59:30 AM UTC 24 |
| Finished | Oct 03 01:59:34 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306743134 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3306743134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.3003870142 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 459429098 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 01:59:29 AM UTC 24 |
| Finished | Oct 03 01:59:33 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003870142 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3003870142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.3870648738 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 249353437 ps |
| CPU time | 3.65 seconds |
| Started | Oct 03 01:59:30 AM UTC 24 |
| Finished | Oct 03 01:59:35 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870648738 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3870648738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.2341085701 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1112272664 ps |
| CPU time | 6.48 seconds |
| Started | Oct 03 01:59:33 AM UTC 24 |
| Finished | Oct 03 01:59:41 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341085701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2341085701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.2396082361 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 211354400 ps |
| CPU time | 5.68 seconds |
| Started | Oct 03 01:59:29 AM UTC 24 |
| Finished | Oct 03 01:59:35 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396082361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2396082361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.1080069593 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 230350641 ps |
| CPU time | 9.67 seconds |
| Started | Oct 03 01:59:33 AM UTC 24 |
| Finished | Oct 03 01:59:44 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080069593 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1080069593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.341934577 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1455259618 ps |
| CPU time | 20.32 seconds |
| Started | Oct 03 01:59:33 AM UTC 24 |
| Finished | Oct 03 01:59:55 AM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=341934577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr _stress_all_with_rand_reset.341934577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.4109580420 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 218178140 ps |
| CPU time | 5.41 seconds |
| Started | Oct 03 01:59:32 AM UTC 24 |
| Finished | Oct 03 01:59:38 AM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109580420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4109580420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.185653539 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 45822165 ps |
| CPU time | 2.5 seconds |
| Started | Oct 03 01:59:33 AM UTC 24 |
| Finished | Oct 03 01:59:37 AM UTC 24 |
| Peak memory | 217052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185653539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.185653539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.4253952568 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 65888720 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 01:59:38 AM UTC 24 |
| Finished | Oct 03 01:59:41 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253952568 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4253952568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2606345319 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 9102181185 ps |
| CPU time | 62.42 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 02:00:41 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606345319 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2606345319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.2875355141 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 980494006 ps |
| CPU time | 8.29 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:47 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875355141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2875355141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.1954170053 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 79433668 ps |
| CPU time | 3.59 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:42 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954170053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1954170053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.1754568563 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 292089426 ps |
| CPU time | 4.54 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:43 AM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754568563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1754568563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_random.1454352422 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 110977756 ps |
| CPU time | 5.35 seconds |
| Started | Oct 03 01:59:36 AM UTC 24 |
| Finished | Oct 03 01:59:42 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454352422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1454352422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.888422686 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 82889919 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 01:59:34 AM UTC 24 |
| Finished | Oct 03 01:59:38 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888422686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.888422686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.603421960 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 182445622 ps |
| CPU time | 4.05 seconds |
| Started | Oct 03 01:59:35 AM UTC 24 |
| Finished | Oct 03 01:59:41 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603421960 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.603421960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.3496490396 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 168805343 ps |
| CPU time | 5.55 seconds |
| Started | Oct 03 01:59:34 AM UTC 24 |
| Finished | Oct 03 01:59:41 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496490396 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3496490396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.72494249 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 101157421 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 01:59:36 AM UTC 24 |
| Finished | Oct 03 01:59:39 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72494249 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.72494249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.3979397808 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 24339355 ps |
| CPU time | 2.78 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:41 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979397808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3979397808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.3791478087 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 172021696 ps |
| CPU time | 4.1 seconds |
| Started | Oct 03 01:59:34 AM UTC 24 |
| Finished | Oct 03 01:59:39 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791478087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3791478087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.1313096718 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 340573605 ps |
| CPU time | 11.08 seconds |
| Started | Oct 03 01:59:38 AM UTC 24 |
| Finished | Oct 03 01:59:51 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313096718 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1313096718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.3106468034 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 364858052 ps |
| CPU time | 5.25 seconds |
| Started | Oct 03 01:59:37 AM UTC 24 |
| Finished | Oct 03 01:59:43 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106468034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3106468034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.1795048166 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 312247010 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 01:59:38 AM UTC 24 |
| Finished | Oct 03 01:59:42 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795048166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1795048166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2589923923 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 87899130 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:59:45 AM UTC 24 |
| Finished | Oct 03 01:59:47 AM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589923923 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2589923923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.1509151362 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 314434956 ps |
| CPU time | 4.49 seconds |
| Started | Oct 03 01:59:42 AM UTC 24 |
| Finished | Oct 03 01:59:48 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509151362 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1509151362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1572728988 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 80531016 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 01:59:44 AM UTC 24 |
| Finished | Oct 03 01:59:49 AM UTC 24 |
| Peak memory | 227908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572728988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1572728988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.319375930 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 68928591 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 01:59:42 AM UTC 24 |
| Finished | Oct 03 01:59:48 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319375930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.319375930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.642382051 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 77864779 ps |
| CPU time | 5.29 seconds |
| Started | Oct 03 01:59:42 AM UTC 24 |
| Finished | Oct 03 01:59:49 AM UTC 24 |
| Peak memory | 217404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642382051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.642382051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3583933853 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 59198715 ps |
| CPU time | 4.73 seconds |
| Started | Oct 03 01:59:42 AM UTC 24 |
| Finished | Oct 03 01:59:48 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583933853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3583933853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.701944345 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 41440611 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 01:59:42 AM UTC 24 |
| Finished | Oct 03 01:59:47 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701944345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.701944345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_random.1687569127 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 276758487 ps |
| CPU time | 8.22 seconds |
| Started | Oct 03 01:59:41 AM UTC 24 |
| Finished | Oct 03 01:59:50 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687569127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1687569127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.3805402718 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3648012731 ps |
| CPU time | 9.57 seconds |
| Started | Oct 03 01:59:40 AM UTC 24 |
| Finished | Oct 03 01:59:51 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805402718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3805402718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.3482845129 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 253212454 ps |
| CPU time | 8.52 seconds |
| Started | Oct 03 01:59:40 AM UTC 24 |
| Finished | Oct 03 01:59:50 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482845129 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3482845129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.3230374092 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 242122219 ps |
| CPU time | 4.1 seconds |
| Started | Oct 03 01:59:40 AM UTC 24 |
| Finished | Oct 03 01:59:45 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230374092 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3230374092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.2172826656 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2288599857 ps |
| CPU time | 43.18 seconds |
| Started | Oct 03 01:59:41 AM UTC 24 |
| Finished | Oct 03 02:00:26 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172826656 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2172826656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.2346539297 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 140211780 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 01:59:44 AM UTC 24 |
| Finished | Oct 03 01:59:47 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346539297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2346539297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.4026752574 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 67785361 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 01:59:39 AM UTC 24 |
| Finished | Oct 03 01:59:44 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026752574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4026752574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.2813085471 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 64476585507 ps |
| CPU time | 430.08 seconds |
| Started | Oct 03 01:59:44 AM UTC 24 |
| Finished | Oct 03 02:07:01 AM UTC 24 |
| Peak memory | 231460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813085471 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2813085471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.1595004565 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 172664101 ps |
| CPU time | 5.99 seconds |
| Started | Oct 03 01:59:45 AM UTC 24 |
| Finished | Oct 03 01:59:52 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1595004565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg r_stress_all_with_rand_reset.1595004565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.1504605269 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 58678633 ps |
| CPU time | 2.92 seconds |
| Started | Oct 03 01:59:42 AM UTC 24 |
| Finished | Oct 03 01:59:46 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504605269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1504605269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.1194088505 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 38235039 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 01:59:44 AM UTC 24 |
| Finished | Oct 03 01:59:47 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194088505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1194088505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1075440283 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 206550585 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:59:50 AM UTC 24 |
| Finished | Oct 03 01:59:52 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075440283 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1075440283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.3973340589 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 127168176 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 01:59:47 AM UTC 24 |
| Finished | Oct 03 01:59:52 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973340589 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3973340589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1469638874 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 138633513 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 01:59:49 AM UTC 24 |
| Finished | Oct 03 01:59:52 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469638874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1469638874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.3261873536 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 50672800 ps |
| CPU time | 2.64 seconds |
| Started | Oct 03 01:59:48 AM UTC 24 |
| Finished | Oct 03 01:59:51 AM UTC 24 |
| Peak memory | 223424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261873536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3261873536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.3660643371 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 333873228 ps |
| CPU time | 4.5 seconds |
| Started | Oct 03 01:59:49 AM UTC 24 |
| Finished | Oct 03 01:59:54 AM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660643371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3660643371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.3411445818 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 229273666 ps |
| CPU time | 7.08 seconds |
| Started | Oct 03 01:59:48 AM UTC 24 |
| Finished | Oct 03 01:59:56 AM UTC 24 |
| Peak memory | 219444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411445818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3411445818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_random.438651399 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 3203645244 ps |
| CPU time | 30.08 seconds |
| Started | Oct 03 01:59:47 AM UTC 24 |
| Finished | Oct 03 02:00:19 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438651399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.438651399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.1908384635 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 306765794 ps |
| CPU time | 7.66 seconds |
| Started | Oct 03 01:59:45 AM UTC 24 |
| Finished | Oct 03 01:59:54 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908384635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1908384635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.808564679 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 30400714 ps |
| CPU time | 3.23 seconds |
| Started | Oct 03 01:59:46 AM UTC 24 |
| Finished | Oct 03 01:59:50 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808564679 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.808564679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.2457464319 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 159641584 ps |
| CPU time | 4.35 seconds |
| Started | Oct 03 01:59:46 AM UTC 24 |
| Finished | Oct 03 01:59:52 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457464319 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2457464319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.2952487333 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1381016016 ps |
| CPU time | 43.14 seconds |
| Started | Oct 03 01:59:46 AM UTC 24 |
| Finished | Oct 03 02:00:31 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952487333 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2952487333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.2906520254 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 137013696 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 01:59:49 AM UTC 24 |
| Finished | Oct 03 01:59:52 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906520254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2906520254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.3517077838 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 51182193 ps |
| CPU time | 2.71 seconds |
| Started | Oct 03 01:59:45 AM UTC 24 |
| Finished | Oct 03 01:59:49 AM UTC 24 |
| Peak memory | 217196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517077838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3517077838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2262703217 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 40166982931 ps |
| CPU time | 593.84 seconds |
| Started | Oct 03 01:59:49 AM UTC 24 |
| Finished | Oct 03 02:09:50 AM UTC 24 |
| Peak memory | 233384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262703217 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2262703217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.945508014 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 578880543 ps |
| CPU time | 18.62 seconds |
| Started | Oct 03 01:59:50 AM UTC 24 |
| Finished | Oct 03 02:00:10 AM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=945508014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr _stress_all_with_rand_reset.945508014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.2317102503 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 43269396 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 01:59:48 AM UTC 24 |
| Finished | Oct 03 01:59:53 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317102503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2317102503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.2122967403 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 79418845 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 01:59:49 AM UTC 24 |
| Finished | Oct 03 01:59:54 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122967403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2122967403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.1243294534 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 53710761 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:59:56 AM UTC 24 |
| Finished | Oct 03 01:59:58 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243294534 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1243294534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.3425605668 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 255014750 ps |
| CPU time | 4.28 seconds |
| Started | Oct 03 01:59:52 AM UTC 24 |
| Finished | Oct 03 01:59:57 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425605668 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3425605668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.1739969482 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 49538405 ps |
| CPU time | 3.08 seconds |
| Started | Oct 03 01:59:53 AM UTC 24 |
| Finished | Oct 03 01:59:57 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739969482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1739969482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.187546390 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 97194738 ps |
| CPU time | 2.93 seconds |
| Started | Oct 03 01:59:53 AM UTC 24 |
| Finished | Oct 03 01:59:57 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187546390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.187546390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.739046076 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 209048953 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 01:59:53 AM UTC 24 |
| Finished | Oct 03 01:59:57 AM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739046076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.739046076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.285405296 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 416870220 ps |
| CPU time | 5.87 seconds |
| Started | Oct 03 01:59:53 AM UTC 24 |
| Finished | Oct 03 02:00:00 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285405296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.285405296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_random.2373897409 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 266812078 ps |
| CPU time | 12.59 seconds |
| Started | Oct 03 01:59:52 AM UTC 24 |
| Finished | Oct 03 02:00:05 AM UTC 24 |
| Peak memory | 217272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373897409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2373897409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.1677912907 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 176702713 ps |
| CPU time | 3.13 seconds |
| Started | Oct 03 01:59:50 AM UTC 24 |
| Finished | Oct 03 01:59:54 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677912907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1677912907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.2425722735 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 133360893 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 01:59:52 AM UTC 24 |
| Finished | Oct 03 01:59:56 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425722735 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2425722735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.3020016596 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 269062215 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 01:59:51 AM UTC 24 |
| Finished | Oct 03 01:59:56 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020016596 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3020016596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.1652111804 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 177153351 ps |
| CPU time | 4.27 seconds |
| Started | Oct 03 01:59:52 AM UTC 24 |
| Finished | Oct 03 01:59:57 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652111804 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1652111804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.3616948670 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 307262242 ps |
| CPU time | 7.41 seconds |
| Started | Oct 03 01:59:54 AM UTC 24 |
| Finished | Oct 03 02:00:03 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616948670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3616948670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.32654846 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 242330047 ps |
| CPU time | 3.56 seconds |
| Started | Oct 03 01:59:50 AM UTC 24 |
| Finished | Oct 03 01:59:55 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32654846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.32654846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.3928418527 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 615261509 ps |
| CPU time | 8.42 seconds |
| Started | Oct 03 01:59:54 AM UTC 24 |
| Finished | Oct 03 02:00:04 AM UTC 24 |
| Peak memory | 227076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928418527 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3928418527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.2192062293 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 102383891 ps |
| CPU time | 5.25 seconds |
| Started | Oct 03 01:59:53 AM UTC 24 |
| Finished | Oct 03 01:59:59 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192062293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2192062293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.1739912273 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 110077108 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 01:59:54 AM UTC 24 |
| Finished | Oct 03 01:59:59 AM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739912273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1739912273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.2359165698 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 18549223 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 02:00:00 AM UTC 24 |
| Finished | Oct 03 02:00:02 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359165698 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2359165698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.3746682798 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 866918214 ps |
| CPU time | 5.04 seconds |
| Started | Oct 03 01:59:57 AM UTC 24 |
| Finished | Oct 03 02:00:03 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746682798 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3746682798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.2159808260 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 203584458 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 01:59:59 AM UTC 24 |
| Finished | Oct 03 02:00:04 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159808260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2159808260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.3854699412 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 28623300 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:59:57 AM UTC 24 |
| Finished | Oct 03 02:00:00 AM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854699412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3854699412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.2631414732 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 47459007 ps |
| CPU time | 3.73 seconds |
| Started | Oct 03 01:59:59 AM UTC 24 |
| Finished | Oct 03 02:00:03 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631414732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2631414732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.1881652513 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 95458963 ps |
| CPU time | 4.17 seconds |
| Started | Oct 03 01:59:58 AM UTC 24 |
| Finished | Oct 03 02:00:04 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881652513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1881652513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_random.490552361 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 787086049 ps |
| CPU time | 7 seconds |
| Started | Oct 03 01:59:57 AM UTC 24 |
| Finished | Oct 03 02:00:05 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490552361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.490552361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.4103461716 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 60036005 ps |
| CPU time | 3.31 seconds |
| Started | Oct 03 01:59:56 AM UTC 24 |
| Finished | Oct 03 02:00:00 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103461716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4103461716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.3472170262 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2965254384 ps |
| CPU time | 28.2 seconds |
| Started | Oct 03 01:59:56 AM UTC 24 |
| Finished | Oct 03 02:00:26 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472170262 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3472170262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.1842185097 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 46416546 ps |
| CPU time | 2.2 seconds |
| Started | Oct 03 01:59:56 AM UTC 24 |
| Finished | Oct 03 01:59:59 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842185097 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1842185097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.1305521498 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 356363159 ps |
| CPU time | 4.64 seconds |
| Started | Oct 03 01:59:57 AM UTC 24 |
| Finished | Oct 03 02:00:03 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305521498 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1305521498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.603512897 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1808444645 ps |
| CPU time | 19.28 seconds |
| Started | Oct 03 01:59:59 AM UTC 24 |
| Finished | Oct 03 02:00:19 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603512897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.603512897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.1129106363 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 171037362 ps |
| CPU time | 4.2 seconds |
| Started | Oct 03 01:59:56 AM UTC 24 |
| Finished | Oct 03 02:00:01 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129106363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1129106363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.2470783182 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 7799359380 ps |
| CPU time | 24.13 seconds |
| Started | Oct 03 02:00:00 AM UTC 24 |
| Finished | Oct 03 02:00:25 AM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470783182 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2470783182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.3762088883 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3680889628 ps |
| CPU time | 30.73 seconds |
| Started | Oct 03 01:59:58 AM UTC 24 |
| Finished | Oct 03 02:00:31 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762088883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3762088883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.928307614 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 129729197 ps |
| CPU time | 3.27 seconds |
| Started | Oct 03 01:59:59 AM UTC 24 |
| Finished | Oct 03 02:00:03 AM UTC 24 |
| Peak memory | 219380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928307614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.928307614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.234981899 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 17001143 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:10 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234981899 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.234981899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.147649202 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 143330689 ps |
| CPU time | 3.28 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:11 AM UTC 24 |
| Peak memory | 217272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147649202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.147649202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.777903062 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 149551516 ps |
| CPU time | 3.19 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:11 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777903062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.777903062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.2204507721 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 95272828 ps |
| CPU time | 5.31 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:13 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204507721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2204507721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_random.950076932 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 357922475 ps |
| CPU time | 6.25 seconds |
| Started | Oct 03 02:00:02 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950076932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.950076932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.2757271000 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 160424916 ps |
| CPU time | 6.45 seconds |
| Started | Oct 03 02:00:01 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757271000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2757271000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2847006721 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 72881614 ps |
| CPU time | 3.27 seconds |
| Started | Oct 03 02:00:01 AM UTC 24 |
| Finished | Oct 03 02:00:09 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847006721 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2847006721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.2621539150 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1393704427 ps |
| CPU time | 6.2 seconds |
| Started | Oct 03 02:00:01 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621539150 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2621539150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.3056559564 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 70003335 ps |
| CPU time | 4.74 seconds |
| Started | Oct 03 02:00:02 AM UTC 24 |
| Finished | Oct 03 02:00:11 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056559564 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3056559564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.1536633409 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 254798736 ps |
| CPU time | 8.53 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:17 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536633409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1536633409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.2214952581 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 85809623 ps |
| CPU time | 2.97 seconds |
| Started | Oct 03 02:00:00 AM UTC 24 |
| Finished | Oct 03 02:00:04 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214952581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2214952581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.3242884753 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 162446147 ps |
| CPU time | 10.28 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:19 AM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3242884753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymg r_stress_all_with_rand_reset.3242884753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.3595484267 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 364084921 ps |
| CPU time | 9 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:17 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595484267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3595484267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.2881818863 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 42196377 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 02:00:07 AM UTC 24 |
| Finished | Oct 03 02:00:11 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881818863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2881818863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1620212033 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 11097618 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:58:26 AM UTC 24 |
| Finished | Oct 03 01:58:28 AM UTC 24 |
| Peak memory | 212912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620212033 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1620212033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.3550453651 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 178193140 ps |
| CPU time | 5.01 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550453651 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3550453651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.3199545011 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 91989772 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 01:58:23 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 219408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199545011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3199545011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.3778473943 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 115806887 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 01:58:22 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 223284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778473943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3778473943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.2165604691 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8727009760 ps |
| CPU time | 77.8 seconds |
| Started | Oct 03 01:58:22 AM UTC 24 |
| Finished | Oct 03 01:59:42 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165604691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2165604691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.2617675340 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 56125964 ps |
| CPU time | 3.4 seconds |
| Started | Oct 03 01:58:22 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617675340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2617675340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_random.293944735 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 116372890 ps |
| CPU time | 4.55 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:27 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293944735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.293944735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.1721403750 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2117895358 ps |
| CPU time | 7.13 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:29 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721403750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1721403750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.475059926 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 379931634 ps |
| CPU time | 3.92 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:26 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475059926 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.475059926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.1030610617 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1401891914 ps |
| CPU time | 32.49 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:55 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030610617 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1030610617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.748635166 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 226543963 ps |
| CPU time | 8.41 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:30 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748635166 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.748635166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.1327437576 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 100747896 ps |
| CPU time | 3.76 seconds |
| Started | Oct 03 01:58:23 AM UTC 24 |
| Finished | Oct 03 01:58:28 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327437576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1327437576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.4174072323 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 495692813 ps |
| CPU time | 13.65 seconds |
| Started | Oct 03 01:58:21 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174072323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4174072323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.3655931026 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 7663294745 ps |
| CPU time | 54.28 seconds |
| Started | Oct 03 01:58:22 AM UTC 24 |
| Finished | Oct 03 01:59:18 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655931026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3655931026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.1549329374 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 114156521 ps |
| CPU time | 3.56 seconds |
| Started | Oct 03 01:58:25 AM UTC 24 |
| Finished | Oct 03 01:58:29 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549329374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1549329374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.1528058232 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 13119197 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 02:00:14 AM UTC 24 |
| Finished | Oct 03 02:00:16 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528058232 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1528058232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.3651855483 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 171531136 ps |
| CPU time | 8.62 seconds |
| Started | Oct 03 02:00:12 AM UTC 24 |
| Finished | Oct 03 02:00:22 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651855483 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3651855483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.4107321808 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 84457914 ps |
| CPU time | 3.27 seconds |
| Started | Oct 03 02:00:12 AM UTC 24 |
| Finished | Oct 03 02:00:16 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107321808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4107321808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.1928333 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 22617540 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 02:00:12 AM UTC 24 |
| Finished | Oct 03 02:00:15 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1928333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2765828321 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 401076496 ps |
| CPU time | 3.44 seconds |
| Started | Oct 03 02:00:12 AM UTC 24 |
| Finished | Oct 03 02:00:17 AM UTC 24 |
| Peak memory | 223352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765828321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2765828321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.2281063051 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 87550695 ps |
| CPU time | 2.93 seconds |
| Started | Oct 03 02:00:12 AM UTC 24 |
| Finished | Oct 03 02:00:16 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281063051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2281063051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_random.1854317272 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 630817756 ps |
| CPU time | 7.51 seconds |
| Started | Oct 03 02:00:11 AM UTC 24 |
| Finished | Oct 03 02:00:19 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854317272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1854317272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.3666709751 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 143109165 ps |
| CPU time | 3.65 seconds |
| Started | Oct 03 02:00:08 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666709751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3666709751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.1137500448 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 65618752 ps |
| CPU time | 3.62 seconds |
| Started | Oct 03 02:00:10 AM UTC 24 |
| Finished | Oct 03 02:00:14 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137500448 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1137500448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.354431227 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 409229706 ps |
| CPU time | 3.04 seconds |
| Started | Oct 03 02:00:08 AM UTC 24 |
| Finished | Oct 03 02:00:12 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354431227 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.354431227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.939472382 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 853782369 ps |
| CPU time | 6.79 seconds |
| Started | Oct 03 02:00:11 AM UTC 24 |
| Finished | Oct 03 02:00:19 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939472382 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.939472382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.2067578110 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 59937701 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 02:00:08 AM UTC 24 |
| Finished | Oct 03 02:00:11 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067578110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2067578110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.61862939 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4408770357 ps |
| CPU time | 90.74 seconds |
| Started | Oct 03 02:00:14 AM UTC 24 |
| Finished | Oct 03 02:01:46 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61862939 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.61862939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.3307540765 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 43379489 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 02:00:12 AM UTC 24 |
| Finished | Oct 03 02:00:17 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307540765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3307540765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.1323127772 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 101694721 ps |
| CPU time | 2.57 seconds |
| Started | Oct 03 02:00:14 AM UTC 24 |
| Finished | Oct 03 02:00:17 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323127772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1323127772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.2786230469 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13606975 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 02:00:20 AM UTC 24 |
| Finished | Oct 03 02:00:22 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786230469 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2786230469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.3102528010 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 212972306 ps |
| CPU time | 4.83 seconds |
| Started | Oct 03 02:00:17 AM UTC 24 |
| Finished | Oct 03 02:00:23 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102528010 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3102528010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.2831655862 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1490312715 ps |
| CPU time | 14.52 seconds |
| Started | Oct 03 02:00:19 AM UTC 24 |
| Finished | Oct 03 02:00:34 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831655862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2831655862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.3353349137 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 64442906 ps |
| CPU time | 2.43 seconds |
| Started | Oct 03 02:00:17 AM UTC 24 |
| Finished | Oct 03 02:00:21 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353349137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3353349137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.2735346040 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2695773328 ps |
| CPU time | 6.19 seconds |
| Started | Oct 03 02:00:18 AM UTC 24 |
| Finished | Oct 03 02:00:25 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735346040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2735346040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.958555676 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 130306593 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 02:00:19 AM UTC 24 |
| Finished | Oct 03 02:00:23 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958555676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.958555676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.2901297083 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1109764600 ps |
| CPU time | 2.77 seconds |
| Started | Oct 03 02:00:17 AM UTC 24 |
| Finished | Oct 03 02:00:21 AM UTC 24 |
| Peak memory | 223024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901297083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2901297083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_random.3080607081 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 529189696 ps |
| CPU time | 4.83 seconds |
| Started | Oct 03 02:00:17 AM UTC 24 |
| Finished | Oct 03 02:00:23 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080607081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3080607081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.3163005636 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 178449335 ps |
| CPU time | 5.88 seconds |
| Started | Oct 03 02:00:15 AM UTC 24 |
| Finished | Oct 03 02:00:22 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163005636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3163005636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.634247117 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 345499477 ps |
| CPU time | 4.04 seconds |
| Started | Oct 03 02:00:15 AM UTC 24 |
| Finished | Oct 03 02:00:20 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634247117 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.634247117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.1844149840 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 145043958 ps |
| CPU time | 5.54 seconds |
| Started | Oct 03 02:00:15 AM UTC 24 |
| Finished | Oct 03 02:00:22 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844149840 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1844149840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.214437336 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 701651842 ps |
| CPU time | 8.66 seconds |
| Started | Oct 03 02:00:16 AM UTC 24 |
| Finished | Oct 03 02:00:26 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214437336 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.214437336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.747710265 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 57762650 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 02:00:19 AM UTC 24 |
| Finished | Oct 03 02:00:23 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747710265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.747710265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.3808033660 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 257242919 ps |
| CPU time | 3.54 seconds |
| Started | Oct 03 02:00:15 AM UTC 24 |
| Finished | Oct 03 02:00:19 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808033660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3808033660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.93615580 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2355074513 ps |
| CPU time | 14.29 seconds |
| Started | Oct 03 02:00:20 AM UTC 24 |
| Finished | Oct 03 02:00:35 AM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93615580 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.93615580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.653497857 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 250632217 ps |
| CPU time | 7.62 seconds |
| Started | Oct 03 02:00:17 AM UTC 24 |
| Finished | Oct 03 02:00:26 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653497857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.653497857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.3096929033 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 143160416 ps |
| CPU time | 3.63 seconds |
| Started | Oct 03 02:00:20 AM UTC 24 |
| Finished | Oct 03 02:00:25 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096929033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3096929033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.1267538664 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 18033779 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 02:00:25 AM UTC 24 |
| Finished | Oct 03 02:00:28 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267538664 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1267538664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.2079184218 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 766877703 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 02:00:24 AM UTC 24 |
| Finished | Oct 03 02:00:29 AM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079184218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2079184218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.3600433656 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 140747314 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 02:00:23 AM UTC 24 |
| Finished | Oct 03 02:00:27 AM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600433656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3600433656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.1165823161 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 33537705 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 02:00:24 AM UTC 24 |
| Finished | Oct 03 02:00:27 AM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165823161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1165823161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.3897104048 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 941830568 ps |
| CPU time | 4.48 seconds |
| Started | Oct 03 02:00:23 AM UTC 24 |
| Finished | Oct 03 02:00:28 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897104048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3897104048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_random.3467366468 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1051157852 ps |
| CPU time | 12.41 seconds |
| Started | Oct 03 02:00:22 AM UTC 24 |
| Finished | Oct 03 02:00:35 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467366468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3467366468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.3455539666 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 109383136 ps |
| CPU time | 3.96 seconds |
| Started | Oct 03 02:00:20 AM UTC 24 |
| Finished | Oct 03 02:00:25 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455539666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3455539666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.2798827880 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1445270711 ps |
| CPU time | 7.38 seconds |
| Started | Oct 03 02:00:22 AM UTC 24 |
| Finished | Oct 03 02:00:30 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798827880 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2798827880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.311517781 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1324544078 ps |
| CPU time | 33.31 seconds |
| Started | Oct 03 02:00:21 AM UTC 24 |
| Finished | Oct 03 02:00:56 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311517781 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.311517781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3954153157 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 78702955 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 02:00:22 AM UTC 24 |
| Finished | Oct 03 02:00:26 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954153157 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3954153157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.1916386023 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 46080442 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 02:00:24 AM UTC 24 |
| Finished | Oct 03 02:00:27 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916386023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1916386023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.3618830772 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 337847392 ps |
| CPU time | 3.81 seconds |
| Started | Oct 03 02:00:20 AM UTC 24 |
| Finished | Oct 03 02:00:25 AM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618830772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3618830772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.2979386368 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 60371451903 ps |
| CPU time | 373.68 seconds |
| Started | Oct 03 02:00:24 AM UTC 24 |
| Finished | Oct 03 02:06:44 AM UTC 24 |
| Peak memory | 243884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979386368 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2979386368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1881479981 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 60618562 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 02:00:23 AM UTC 24 |
| Finished | Oct 03 02:00:27 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881479981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1881479981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.2927667204 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 790538900 ps |
| CPU time | 4.45 seconds |
| Started | Oct 03 02:00:24 AM UTC 24 |
| Finished | Oct 03 02:00:30 AM UTC 24 |
| Peak memory | 219572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927667204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2927667204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.10705299 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 68481930 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 02:00:30 AM UTC 24 |
| Finished | Oct 03 02:00:32 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10705299 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.10705299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.3586645620 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 199440574 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:32 AM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586645620 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3586645620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.4117317329 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 50750037 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 02:00:28 AM UTC 24 |
| Finished | Oct 03 02:00:33 AM UTC 24 |
| Peak memory | 230792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117317329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.4117317329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.3536131833 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 13526566428 ps |
| CPU time | 25.58 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:54 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536131833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3536131833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.4041543703 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1596712747 ps |
| CPU time | 8.62 seconds |
| Started | Oct 03 02:00:28 AM UTC 24 |
| Finished | Oct 03 02:00:38 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041543703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4041543703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.4250212918 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 373800161 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 02:00:28 AM UTC 24 |
| Finished | Oct 03 02:00:32 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250212918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4250212918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.1840610521 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 318004613 ps |
| CPU time | 4.73 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:33 AM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840610521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1840610521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_random.1481568750 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 7243503590 ps |
| CPU time | 40.73 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:01:09 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481568750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1481568750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.4108011541 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 104171986 ps |
| CPU time | 2.98 seconds |
| Started | Oct 03 02:00:26 AM UTC 24 |
| Finished | Oct 03 02:00:30 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108011541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4108011541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.3757515049 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 65693835 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:30 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757515049 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3757515049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.1209470573 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 632886000 ps |
| CPU time | 15.57 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:43 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209470573 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1209470573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.2806657172 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 157888640 ps |
| CPU time | 4.81 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:33 AM UTC 24 |
| Peak memory | 217388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806657172 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2806657172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.1565649645 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 110495282 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 02:00:28 AM UTC 24 |
| Finished | Oct 03 02:00:33 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565649645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1565649645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.951553367 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1323820126 ps |
| CPU time | 20.29 seconds |
| Started | Oct 03 02:00:26 AM UTC 24 |
| Finished | Oct 03 02:00:47 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951553367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.951553367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.161164049 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 810241132 ps |
| CPU time | 24.2 seconds |
| Started | Oct 03 02:00:29 AM UTC 24 |
| Finished | Oct 03 02:00:54 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161164049 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.161164049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.2984667010 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 130137596 ps |
| CPU time | 5.99 seconds |
| Started | Oct 03 02:00:27 AM UTC 24 |
| Finished | Oct 03 02:00:34 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984667010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2984667010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.1645281946 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 39959472 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 02:00:28 AM UTC 24 |
| Finished | Oct 03 02:00:32 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645281946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1645281946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.1569857323 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 35334230 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 02:00:35 AM UTC 24 |
| Finished | Oct 03 02:00:37 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569857323 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1569857323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.343032623 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 33155990 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 02:00:32 AM UTC 24 |
| Finished | Oct 03 02:00:36 AM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343032623 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.343032623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.979831738 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 115649441 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 02:00:34 AM UTC 24 |
| Finished | Oct 03 02:00:36 AM UTC 24 |
| Peak memory | 222900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979831738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.979831738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.4051992753 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 147045060 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 02:00:32 AM UTC 24 |
| Finished | Oct 03 02:00:36 AM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051992753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4051992753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.2525018916 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 142518722 ps |
| CPU time | 5.27 seconds |
| Started | Oct 03 02:00:32 AM UTC 24 |
| Finished | Oct 03 02:00:39 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525018916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2525018916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.1548455440 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 177662977 ps |
| CPU time | 4 seconds |
| Started | Oct 03 02:00:34 AM UTC 24 |
| Finished | Oct 03 02:00:39 AM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548455440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1548455440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.2338324418 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 80247391 ps |
| CPU time | 4.29 seconds |
| Started | Oct 03 02:00:32 AM UTC 24 |
| Finished | Oct 03 02:00:38 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338324418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2338324418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_random.2069941161 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 108605310 ps |
| CPU time | 4.01 seconds |
| Started | Oct 03 02:00:32 AM UTC 24 |
| Finished | Oct 03 02:00:37 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069941161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2069941161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.3399282957 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1022111650 ps |
| CPU time | 9.42 seconds |
| Started | Oct 03 02:00:31 AM UTC 24 |
| Finished | Oct 03 02:00:41 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399282957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3399282957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.509572556 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 526302251 ps |
| CPU time | 4.13 seconds |
| Started | Oct 03 02:00:31 AM UTC 24 |
| Finished | Oct 03 02:00:36 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509572556 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.509572556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.959044385 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 749918681 ps |
| CPU time | 22.99 seconds |
| Started | Oct 03 02:00:31 AM UTC 24 |
| Finished | Oct 03 02:00:55 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959044385 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.959044385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.3714487203 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 560494670 ps |
| CPU time | 18.09 seconds |
| Started | Oct 03 02:00:31 AM UTC 24 |
| Finished | Oct 03 02:00:50 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714487203 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3714487203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.254300755 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2714165814 ps |
| CPU time | 21.99 seconds |
| Started | Oct 03 02:00:34 AM UTC 24 |
| Finished | Oct 03 02:00:57 AM UTC 24 |
| Peak memory | 217280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254300755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.254300755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.4060150151 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 199897826 ps |
| CPU time | 3.91 seconds |
| Started | Oct 03 02:00:31 AM UTC 24 |
| Finished | Oct 03 02:00:36 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060150151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4060150151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.3874057441 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 45393794780 ps |
| CPU time | 181.34 seconds |
| Started | Oct 03 02:00:34 AM UTC 24 |
| Finished | Oct 03 02:03:38 AM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874057441 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3874057441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.3453772576 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 565873451 ps |
| CPU time | 25.11 seconds |
| Started | Oct 03 02:00:35 AM UTC 24 |
| Finished | Oct 03 02:01:01 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3453772576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymg r_stress_all_with_rand_reset.3453772576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1037596215 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 279855401 ps |
| CPU time | 5.5 seconds |
| Started | Oct 03 02:00:32 AM UTC 24 |
| Finished | Oct 03 02:00:39 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037596215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1037596215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.3295940455 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 191854434 ps |
| CPU time | 3.62 seconds |
| Started | Oct 03 02:00:34 AM UTC 24 |
| Finished | Oct 03 02:00:38 AM UTC 24 |
| Peak memory | 219636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295940455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3295940455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.3520361392 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 33828278 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 02:00:41 AM UTC 24 |
| Finished | Oct 03 02:00:44 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520361392 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3520361392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.3324441120 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 212997314 ps |
| CPU time | 3.84 seconds |
| Started | Oct 03 02:00:37 AM UTC 24 |
| Finished | Oct 03 02:00:42 AM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324441120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3324441120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.340279138 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 71167848 ps |
| CPU time | 2.71 seconds |
| Started | Oct 03 02:00:39 AM UTC 24 |
| Finished | Oct 03 02:00:43 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340279138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.340279138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.1632149681 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 143515501 ps |
| CPU time | 4.51 seconds |
| Started | Oct 03 02:00:39 AM UTC 24 |
| Finished | Oct 03 02:00:44 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632149681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1632149681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.2933881880 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 91334286 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 02:00:39 AM UTC 24 |
| Finished | Oct 03 02:00:43 AM UTC 24 |
| Peak memory | 213088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933881880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2933881880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_random.2567651022 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1484382646 ps |
| CPU time | 7.39 seconds |
| Started | Oct 03 02:00:37 AM UTC 24 |
| Finished | Oct 03 02:00:46 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567651022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2567651022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.2862200370 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 68834194 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 02:00:36 AM UTC 24 |
| Finished | Oct 03 02:00:40 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862200370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2862200370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.1752485917 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 84659308 ps |
| CPU time | 4.28 seconds |
| Started | Oct 03 02:00:37 AM UTC 24 |
| Finished | Oct 03 02:00:43 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752485917 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1752485917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.3701770698 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 203118941 ps |
| CPU time | 2.86 seconds |
| Started | Oct 03 02:00:36 AM UTC 24 |
| Finished | Oct 03 02:00:40 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701770698 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3701770698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.3206699151 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 166839058 ps |
| CPU time | 4.07 seconds |
| Started | Oct 03 02:00:37 AM UTC 24 |
| Finished | Oct 03 02:00:42 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206699151 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3206699151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.2005798685 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2080575341 ps |
| CPU time | 13.05 seconds |
| Started | Oct 03 02:00:39 AM UTC 24 |
| Finished | Oct 03 02:00:53 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005798685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2005798685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3570756101 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 514365254 ps |
| CPU time | 2.93 seconds |
| Started | Oct 03 02:00:36 AM UTC 24 |
| Finished | Oct 03 02:00:40 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570756101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3570756101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.1326199497 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2461543812 ps |
| CPU time | 11.9 seconds |
| Started | Oct 03 02:00:39 AM UTC 24 |
| Finished | Oct 03 02:00:52 AM UTC 24 |
| Peak memory | 217364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326199497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1326199497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.1475278896 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 14694017 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 02:00:48 AM UTC 24 |
| Finished | Oct 03 02:00:51 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475278896 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1475278896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.1200698632 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 208567712 ps |
| CPU time | 5.04 seconds |
| Started | Oct 03 02:00:46 AM UTC 24 |
| Finished | Oct 03 02:00:52 AM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200698632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1200698632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.1019893301 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 278474538 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 02:00:45 AM UTC 24 |
| Finished | Oct 03 02:00:49 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019893301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1019893301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.2326127348 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 361529943 ps |
| CPU time | 5.44 seconds |
| Started | Oct 03 02:00:45 AM UTC 24 |
| Finished | Oct 03 02:00:52 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326127348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2326127348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2472449191 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 205916975 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 02:00:46 AM UTC 24 |
| Finished | Oct 03 02:00:49 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472449191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2472449191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.2734260432 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 120457983 ps |
| CPU time | 5.87 seconds |
| Started | Oct 03 02:00:45 AM UTC 24 |
| Finished | Oct 03 02:00:53 AM UTC 24 |
| Peak memory | 223432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734260432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2734260432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_random.380319935 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 36334420 ps |
| CPU time | 3.39 seconds |
| Started | Oct 03 02:00:44 AM UTC 24 |
| Finished | Oct 03 02:00:49 AM UTC 24 |
| Peak memory | 217448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380319935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.380319935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.1798778003 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 77623485 ps |
| CPU time | 4.53 seconds |
| Started | Oct 03 02:00:41 AM UTC 24 |
| Finished | Oct 03 02:00:47 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798778003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1798778003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.2473852782 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 40727848 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 02:00:44 AM UTC 24 |
| Finished | Oct 03 02:00:47 AM UTC 24 |
| Peak memory | 214896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473852782 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2473852782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.3938473610 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 707305770 ps |
| CPU time | 6.94 seconds |
| Started | Oct 03 02:00:43 AM UTC 24 |
| Finished | Oct 03 02:00:51 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938473610 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3938473610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.1707350160 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 463132271 ps |
| CPU time | 10.99 seconds |
| Started | Oct 03 02:00:44 AM UTC 24 |
| Finished | Oct 03 02:00:56 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707350160 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1707350160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.2428662370 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 125725796 ps |
| CPU time | 3.48 seconds |
| Started | Oct 03 02:00:46 AM UTC 24 |
| Finished | Oct 03 02:00:50 AM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428662370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2428662370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.807711250 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 77571763 ps |
| CPU time | 2.94 seconds |
| Started | Oct 03 02:00:41 AM UTC 24 |
| Finished | Oct 03 02:00:45 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807711250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.807711250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.1931840747 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 96872202 ps |
| CPU time | 6.29 seconds |
| Started | Oct 03 02:00:45 AM UTC 24 |
| Finished | Oct 03 02:00:53 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931840747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1931840747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.301690549 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 38741362 ps |
| CPU time | 3.05 seconds |
| Started | Oct 03 02:00:46 AM UTC 24 |
| Finished | Oct 03 02:00:50 AM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301690549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.301690549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.276519302 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 63200615 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 02:00:55 AM UTC 24 |
| Finished | Oct 03 02:00:57 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276519302 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.276519302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.2329847558 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 409526808 ps |
| CPU time | 5.08 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:00:59 AM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329847558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2329847558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.3039598263 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 70059041 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:00:56 AM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039598263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3039598263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.3599101830 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 91551450 ps |
| CPU time | 3.71 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:00:58 AM UTC 24 |
| Peak memory | 223304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599101830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3599101830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.3554050399 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 143576832 ps |
| CPU time | 2.78 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:00:57 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554050399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3554050399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.373004831 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 296393847 ps |
| CPU time | 4.54 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:00:59 AM UTC 24 |
| Peak memory | 227664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373004831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.373004831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_random.3541031509 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1349510986 ps |
| CPU time | 4.51 seconds |
| Started | Oct 03 02:00:50 AM UTC 24 |
| Finished | Oct 03 02:00:56 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541031509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3541031509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.1285362103 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1347550253 ps |
| CPU time | 4.69 seconds |
| Started | Oct 03 02:00:48 AM UTC 24 |
| Finished | Oct 03 02:00:54 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285362103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1285362103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1437974426 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 648250978 ps |
| CPU time | 11.83 seconds |
| Started | Oct 03 02:00:48 AM UTC 24 |
| Finished | Oct 03 02:01:02 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437974426 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1437974426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.2402086882 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 98592769 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 02:00:50 AM UTC 24 |
| Finished | Oct 03 02:00:55 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402086882 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2402086882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.2407337068 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 542799697 ps |
| CPU time | 4.31 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:00:59 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407337068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2407337068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.2264017510 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 156536796 ps |
| CPU time | 4.34 seconds |
| Started | Oct 03 02:00:48 AM UTC 24 |
| Finished | Oct 03 02:00:54 AM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264017510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2264017510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.2323558768 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 461145987 ps |
| CPU time | 8.03 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:01:02 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323558768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2323558768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.2602424797 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 820256466 ps |
| CPU time | 15.37 seconds |
| Started | Oct 03 02:00:53 AM UTC 24 |
| Finished | Oct 03 02:01:10 AM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602424797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2602424797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.251227032 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 16671044 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 02:01:00 AM UTC 24 |
| Finished | Oct 03 02:01:02 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251227032 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.251227032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.3441320611 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 150012631 ps |
| CPU time | 7.67 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:06 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441320611 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3441320611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.3185403257 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 43946300 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:01 AM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185403257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3185403257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.944965933 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 177540405 ps |
| CPU time | 4.33 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:03 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944965933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.944965933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.309945142 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 49769405 ps |
| CPU time | 3.05 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:01 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309945142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.309945142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.308691137 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 566437731 ps |
| CPU time | 5.66 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:04 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308691137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.308691137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_random.3828631747 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 119441053 ps |
| CPU time | 5.51 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:03 AM UTC 24 |
| Peak memory | 227348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828631747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3828631747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.1218532734 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 118898804 ps |
| CPU time | 3.7 seconds |
| Started | Oct 03 02:00:55 AM UTC 24 |
| Finished | Oct 03 02:01:00 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218532734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1218532734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.2165336215 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2943841234 ps |
| CPU time | 8.29 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:06 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165336215 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2165336215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.3549779 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 273702541 ps |
| CPU time | 6.76 seconds |
| Started | Oct 03 02:00:56 AM UTC 24 |
| Finished | Oct 03 02:01:03 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549779 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3549779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.4204861970 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 159638421 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:00 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204861970 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4204861970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.2005066266 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 40881749 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 02:00:59 AM UTC 24 |
| Finished | Oct 03 02:01:03 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005066266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2005066266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.537200354 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 57368231 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 02:00:55 AM UTC 24 |
| Finished | Oct 03 02:00:59 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537200354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.537200354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.2391017058 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1923482078 ps |
| CPU time | 34.94 seconds |
| Started | Oct 03 02:00:59 AM UTC 24 |
| Finished | Oct 03 02:01:36 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391017058 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2391017058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.1612742831 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 390948815 ps |
| CPU time | 4.79 seconds |
| Started | Oct 03 02:00:57 AM UTC 24 |
| Finished | Oct 03 02:01:03 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612742831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1612742831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.201578222 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 105170216 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 02:00:59 AM UTC 24 |
| Finished | Oct 03 02:01:03 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201578222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.201578222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.2468799460 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 49153096 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:07 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468799460 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2468799460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.3166341527 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 433660900 ps |
| CPU time | 11.63 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:15 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166341527 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3166341527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.2049398340 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 109608856 ps |
| CPU time | 3.4 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:09 AM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049398340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2049398340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.3262916640 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 364880828 ps |
| CPU time | 4.77 seconds |
| Started | Oct 03 02:01:04 AM UTC 24 |
| Finished | Oct 03 02:01:10 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262916640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3262916640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.2688176640 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 172210601 ps |
| CPU time | 6.09 seconds |
| Started | Oct 03 02:01:04 AM UTC 24 |
| Finished | Oct 03 02:01:12 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688176640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2688176640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.986933131 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 67729054 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 02:01:04 AM UTC 24 |
| Finished | Oct 03 02:01:08 AM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986933131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.986933131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_random.3877771464 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 63915842 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:07 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877771464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3877771464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.614709179 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 36073421 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:05 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614709179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.614709179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.2384466220 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 107778043 ps |
| CPU time | 3.14 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:06 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384466220 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2384466220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.781427922 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 624922743 ps |
| CPU time | 4.81 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:08 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781427922 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.781427922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.1279221821 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 113904366 ps |
| CPU time | 2.42 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:06 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279221821 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1279221821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3643897907 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 564703601 ps |
| CPU time | 17.43 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:23 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643897907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3643897907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.1806799738 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 65960051 ps |
| CPU time | 2.84 seconds |
| Started | Oct 03 02:01:02 AM UTC 24 |
| Finished | Oct 03 02:01:06 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806799738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1806799738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.3133485523 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1528590373 ps |
| CPU time | 13.43 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:20 AM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3133485523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg r_stress_all_with_rand_reset.3133485523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2255135009 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1116241554 ps |
| CPU time | 8.3 seconds |
| Started | Oct 03 02:01:04 AM UTC 24 |
| Finished | Oct 03 02:01:14 AM UTC 24 |
| Peak memory | 223496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255135009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2255135009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.2977986323 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 94256447 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:08 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977986323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2977986323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.41042335 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 21520484 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 01:58:32 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41042335 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.41042335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.280680978 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 46694872 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 01:58:30 AM UTC 24 |
| Finished | Oct 03 01:58:33 AM UTC 24 |
| Peak memory | 217484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280680978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.280680978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.3055489557 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 294756692 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 01:58:30 AM UTC 24 |
| Finished | Oct 03 01:58:36 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055489557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3055489557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.2609713366 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 88569268 ps |
| CPU time | 4.05 seconds |
| Started | Oct 03 01:58:30 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609713366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2609713366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_random.2984856972 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 342558646 ps |
| CPU time | 3.7 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:33 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984856972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2984856972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.607901202 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 453010615 ps |
| CPU time | 14.8 seconds |
| Started | Oct 03 01:58:31 AM UTC 24 |
| Finished | Oct 03 01:58:47 AM UTC 24 |
| Peak memory | 258204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607901202 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.607901202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.3099989043 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 101830996 ps |
| CPU time | 4.83 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:34 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099989043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3099989043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.1155670533 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 213305010 ps |
| CPU time | 4.01 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:33 AM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155670533 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1155670533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.339944723 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 72223312 ps |
| CPU time | 5.02 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:34 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339944723 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.339944723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.2669339739 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 145953755 ps |
| CPU time | 5.49 seconds |
| Started | Oct 03 01:58:28 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 215176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669339739 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2669339739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.2037203218 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 132930673 ps |
| CPU time | 3.28 seconds |
| Started | Oct 03 01:58:31 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037203218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2037203218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.3181716854 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1339365267 ps |
| CPU time | 25.13 seconds |
| Started | Oct 03 01:58:27 AM UTC 24 |
| Finished | Oct 03 01:58:53 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181716854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3181716854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.2428053685 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 164051116 ps |
| CPU time | 4.65 seconds |
| Started | Oct 03 01:58:30 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428053685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2428053685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.127254401 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 45974912 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 01:58:31 AM UTC 24 |
| Finished | Oct 03 01:58:36 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127254401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.127254401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.3884686870 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 12755416 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:01:11 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884686870 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3884686870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.2514174110 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 105941884 ps |
| CPU time | 3.25 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:01:13 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514174110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2514174110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.1196129388 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 546588439 ps |
| CPU time | 3.02 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:12 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196129388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1196129388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.971236370 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 78435301 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:01:12 AM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971236370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.971236370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.3643561853 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 112615810 ps |
| CPU time | 2.51 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:11 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643561853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3643561853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_random.3201099921 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 477754259 ps |
| CPU time | 13.25 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:22 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201099921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3201099921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.4146795901 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 501883987 ps |
| CPU time | 5.97 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:12 AM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146795901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4146795901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.1856829796 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 134082497 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:12 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856829796 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1856829796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.3490098775 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 220127837 ps |
| CPU time | 3.09 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:11 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490098775 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3490098775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.276744094 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1592275444 ps |
| CPU time | 21.04 seconds |
| Started | Oct 03 02:01:07 AM UTC 24 |
| Finished | Oct 03 02:01:30 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276744094 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.276744094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.2816060885 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 72663250 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:01:12 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816060885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2816060885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.2367137826 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 93725198 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 02:01:05 AM UTC 24 |
| Finished | Oct 03 02:01:10 AM UTC 24 |
| Peak memory | 216920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367137826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2367137826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.278249444 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 24273719941 ps |
| CPU time | 51.82 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:02:03 AM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278249444 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.278249444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.242930909 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1187716002 ps |
| CPU time | 18.6 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:01:29 AM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=242930909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr _stress_all_with_rand_reset.242930909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.3139457817 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 73557256 ps |
| CPU time | 4.14 seconds |
| Started | Oct 03 02:01:09 AM UTC 24 |
| Finished | Oct 03 02:01:14 AM UTC 24 |
| Peak memory | 217272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139457817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3139457817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.2150817417 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 43955140 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 02:01:15 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150817417 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2150817417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.1758491014 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 470387251 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:16 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758491014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1758491014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.2884353553 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 36433908 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:17 AM UTC 24 |
| Peak memory | 223744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884353553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2884353553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.372649344 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 259204597 ps |
| CPU time | 4.05 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372649344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.372649344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.3978635350 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 164308493 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978635350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3978635350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_random.1922847499 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 50326254 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 02:01:12 AM UTC 24 |
| Finished | Oct 03 02:01:16 AM UTC 24 |
| Peak memory | 227652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922847499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1922847499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.1816268030 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1674102672 ps |
| CPU time | 19.82 seconds |
| Started | Oct 03 02:01:10 AM UTC 24 |
| Finished | Oct 03 02:01:31 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816268030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1816268030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.705780820 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 305934002 ps |
| CPU time | 3.66 seconds |
| Started | Oct 03 02:01:10 AM UTC 24 |
| Finished | Oct 03 02:01:15 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705780820 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.705780820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.2343379969 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 148708927 ps |
| CPU time | 3.87 seconds |
| Started | Oct 03 02:01:10 AM UTC 24 |
| Finished | Oct 03 02:01:15 AM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343379969 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2343379969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.4242364404 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 436033837 ps |
| CPU time | 12.68 seconds |
| Started | Oct 03 02:01:10 AM UTC 24 |
| Finished | Oct 03 02:01:24 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242364404 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4242364404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.1110902476 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 440474384 ps |
| CPU time | 3.81 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110902476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1110902476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.1492380739 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 248944545 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 02:01:10 AM UTC 24 |
| Finished | Oct 03 02:01:15 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492380739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1492380739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.524633311 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1179186511 ps |
| CPU time | 26.4 seconds |
| Started | Oct 03 02:01:14 AM UTC 24 |
| Finished | Oct 03 02:01:42 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524633311 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.524633311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.3787400458 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 219725371 ps |
| CPU time | 9.25 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:23 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787400458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3787400458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.4207349842 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 67240581 ps |
| CPU time | 3.29 seconds |
| Started | Oct 03 02:01:13 AM UTC 24 |
| Finished | Oct 03 02:01:18 AM UTC 24 |
| Peak memory | 219380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207349842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4207349842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.2276486717 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 39557347 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 02:01:21 AM UTC 24 |
| Finished | Oct 03 02:01:23 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276486717 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2276486717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.1843890339 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 6325091962 ps |
| CPU time | 33.59 seconds |
| Started | Oct 03 02:01:17 AM UTC 24 |
| Finished | Oct 03 02:01:52 AM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843890339 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1843890339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.162252879 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 160171984 ps |
| CPU time | 5.92 seconds |
| Started | Oct 03 02:01:19 AM UTC 24 |
| Finished | Oct 03 02:01:26 AM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162252879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.162252879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.2682323601 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 303672318 ps |
| CPU time | 3.84 seconds |
| Started | Oct 03 02:01:17 AM UTC 24 |
| Finished | Oct 03 02:01:22 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682323601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2682323601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1029662707 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 310759950 ps |
| CPU time | 5.78 seconds |
| Started | Oct 03 02:01:18 AM UTC 24 |
| Finished | Oct 03 02:01:25 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029662707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1029662707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.4092762505 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 133542741 ps |
| CPU time | 2.8 seconds |
| Started | Oct 03 02:01:18 AM UTC 24 |
| Finished | Oct 03 02:01:22 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092762505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4092762505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.1881910809 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 68231273 ps |
| CPU time | 4.95 seconds |
| Started | Oct 03 02:01:16 AM UTC 24 |
| Finished | Oct 03 02:01:22 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881910809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1881910809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.3684331870 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 146416107 ps |
| CPU time | 7.04 seconds |
| Started | Oct 03 02:01:16 AM UTC 24 |
| Finished | Oct 03 02:01:24 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684331870 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3684331870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.3326330737 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 611052289 ps |
| CPU time | 7.4 seconds |
| Started | Oct 03 02:01:16 AM UTC 24 |
| Finished | Oct 03 02:01:24 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326330737 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3326330737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.1352888246 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 309824449 ps |
| CPU time | 4.29 seconds |
| Started | Oct 03 02:01:17 AM UTC 24 |
| Finished | Oct 03 02:01:22 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352888246 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1352888246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.2651819211 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 89087678 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 02:01:19 AM UTC 24 |
| Finished | Oct 03 02:01:23 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651819211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2651819211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.3765100864 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 86759374 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 02:01:16 AM UTC 24 |
| Finished | Oct 03 02:01:19 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765100864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3765100864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.3713178521 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5617647613 ps |
| CPU time | 51.89 seconds |
| Started | Oct 03 02:01:20 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713178521 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3713178521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all_with_rand_reset.1922139863 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1120776326 ps |
| CPU time | 19.64 seconds |
| Started | Oct 03 02:01:20 AM UTC 24 |
| Finished | Oct 03 02:01:40 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1922139863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymg r_stress_all_with_rand_reset.1922139863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1149360345 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 525815663 ps |
| CPU time | 4.43 seconds |
| Started | Oct 03 02:01:18 AM UTC 24 |
| Finished | Oct 03 02:01:23 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149360345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1149360345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.383385883 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 129699993 ps |
| CPU time | 4.17 seconds |
| Started | Oct 03 02:01:20 AM UTC 24 |
| Finished | Oct 03 02:01:25 AM UTC 24 |
| Peak memory | 219508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383385883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.383385883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.4217554010 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 11966536 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 02:01:26 AM UTC 24 |
| Finished | Oct 03 02:01:28 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217554010 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4217554010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.2836212620 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 385067715 ps |
| CPU time | 5.31 seconds |
| Started | Oct 03 02:01:23 AM UTC 24 |
| Finished | Oct 03 02:01:30 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836212620 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2836212620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.1698721031 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 154494277 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 02:01:23 AM UTC 24 |
| Finished | Oct 03 02:01:29 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698721031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1698721031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.4251483352 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 359407823 ps |
| CPU time | 6.6 seconds |
| Started | Oct 03 02:01:25 AM UTC 24 |
| Finished | Oct 03 02:01:32 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251483352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4251483352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.70119782 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 145108483 ps |
| CPU time | 4.04 seconds |
| Started | Oct 03 02:01:25 AM UTC 24 |
| Finished | Oct 03 02:01:30 AM UTC 24 |
| Peak memory | 231568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70119782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.70119782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.2933896850 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 134364555 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 02:01:24 AM UTC 24 |
| Finished | Oct 03 02:01:29 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933896850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2933896850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_random.3268027831 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 6678031145 ps |
| CPU time | 48.42 seconds |
| Started | Oct 03 02:01:23 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268027831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3268027831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.2676928752 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 93695740 ps |
| CPU time | 4.08 seconds |
| Started | Oct 03 02:01:22 AM UTC 24 |
| Finished | Oct 03 02:01:27 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676928752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2676928752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.3564291601 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 317322797 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 02:01:23 AM UTC 24 |
| Finished | Oct 03 02:01:29 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564291601 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3564291601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.1409610840 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 438187031 ps |
| CPU time | 14.07 seconds |
| Started | Oct 03 02:01:23 AM UTC 24 |
| Finished | Oct 03 02:01:38 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409610840 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1409610840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.1957228784 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 417791974 ps |
| CPU time | 5.33 seconds |
| Started | Oct 03 02:01:23 AM UTC 24 |
| Finished | Oct 03 02:01:30 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957228784 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1957228784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.1909429142 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 100200346 ps |
| CPU time | 3.48 seconds |
| Started | Oct 03 02:01:25 AM UTC 24 |
| Finished | Oct 03 02:01:29 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909429142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1909429142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.1232945477 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 120028777 ps |
| CPU time | 2.58 seconds |
| Started | Oct 03 02:01:21 AM UTC 24 |
| Finished | Oct 03 02:01:24 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232945477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1232945477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.265742088 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 707264945 ps |
| CPU time | 37.86 seconds |
| Started | Oct 03 02:01:26 AM UTC 24 |
| Finished | Oct 03 02:02:05 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265742088 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.265742088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.3083548740 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 115768196 ps |
| CPU time | 4.88 seconds |
| Started | Oct 03 02:01:24 AM UTC 24 |
| Finished | Oct 03 02:01:30 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083548740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3083548740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.792574724 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 333140199 ps |
| CPU time | 5.48 seconds |
| Started | Oct 03 02:01:26 AM UTC 24 |
| Finished | Oct 03 02:01:32 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792574724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.792574724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.1566770849 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 46765075 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 02:01:32 AM UTC 24 |
| Finished | Oct 03 02:01:34 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566770849 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1566770849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.553252208 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 82432596 ps |
| CPU time | 3.17 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:35 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553252208 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.553252208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.3381720712 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 294771603 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:36 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381720712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3381720712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.3821020555 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 61758453 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:35 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821020555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3821020555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.2293943649 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 26919952 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:34 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293943649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2293943649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.2184397321 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 237002516 ps |
| CPU time | 3.16 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:35 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184397321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2184397321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.3671254760 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 519536873 ps |
| CPU time | 6.69 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:39 AM UTC 24 |
| Peak memory | 231620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671254760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3671254760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_random.2367788843 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2562494334 ps |
| CPU time | 16.15 seconds |
| Started | Oct 03 02:01:29 AM UTC 24 |
| Finished | Oct 03 02:01:47 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367788843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2367788843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.3266183819 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1270468382 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 02:01:27 AM UTC 24 |
| Finished | Oct 03 02:01:33 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266183819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3266183819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.506346413 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5592026002 ps |
| CPU time | 39.72 seconds |
| Started | Oct 03 02:01:29 AM UTC 24 |
| Finished | Oct 03 02:02:11 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506346413 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.506346413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.4288285654 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 667437933 ps |
| CPU time | 8.46 seconds |
| Started | Oct 03 02:01:28 AM UTC 24 |
| Finished | Oct 03 02:01:38 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288285654 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4288285654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.1855954088 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2882848756 ps |
| CPU time | 5.74 seconds |
| Started | Oct 03 02:01:29 AM UTC 24 |
| Finished | Oct 03 02:01:37 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855954088 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1855954088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.2226899432 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1466429075 ps |
| CPU time | 8.77 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:41 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226899432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2226899432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.1612304452 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 85588497 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 02:01:26 AM UTC 24 |
| Finished | Oct 03 02:01:32 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612304452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1612304452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1605376346 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 474301135 ps |
| CPU time | 26.24 seconds |
| Started | Oct 03 02:01:32 AM UTC 24 |
| Finished | Oct 03 02:02:00 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605376346 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1605376346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.3072471258 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1910408288 ps |
| CPU time | 16.34 seconds |
| Started | Oct 03 02:01:32 AM UTC 24 |
| Finished | Oct 03 02:01:50 AM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3072471258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.3072471258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.94559577 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1765526339 ps |
| CPU time | 6.29 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:38 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94559577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.94559577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.4037051140 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 107744014 ps |
| CPU time | 2.53 seconds |
| Started | Oct 03 02:01:31 AM UTC 24 |
| Finished | Oct 03 02:01:35 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037051140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4037051140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2649414132 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 9753937 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 02:01:39 AM UTC 24 |
| Finished | Oct 03 02:01:41 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649414132 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2649414132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.2230652011 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 406895227 ps |
| CPU time | 6.78 seconds |
| Started | Oct 03 02:01:36 AM UTC 24 |
| Finished | Oct 03 02:01:44 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230652011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2230652011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.1552425786 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 539681580 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 02:01:37 AM UTC 24 |
| Finished | Oct 03 02:01:44 AM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552425786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1552425786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.1500446922 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 117976695 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 02:01:37 AM UTC 24 |
| Finished | Oct 03 02:01:41 AM UTC 24 |
| Peak memory | 231484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500446922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1500446922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.1024259577 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 57920005 ps |
| CPU time | 4.04 seconds |
| Started | Oct 03 02:01:36 AM UTC 24 |
| Finished | Oct 03 02:01:41 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024259577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1024259577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_random.444712546 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 346806724 ps |
| CPU time | 7 seconds |
| Started | Oct 03 02:01:36 AM UTC 24 |
| Finished | Oct 03 02:01:44 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444712546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.444712546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.1749979122 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 70131844 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 02:01:34 AM UTC 24 |
| Finished | Oct 03 02:01:37 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749979122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1749979122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.1753624914 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 545958921 ps |
| CPU time | 5.89 seconds |
| Started | Oct 03 02:01:34 AM UTC 24 |
| Finished | Oct 03 02:01:41 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753624914 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1753624914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.918144455 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 183962925 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 02:01:34 AM UTC 24 |
| Finished | Oct 03 02:01:39 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918144455 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.918144455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.2562869059 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1001252764 ps |
| CPU time | 8.43 seconds |
| Started | Oct 03 02:01:35 AM UTC 24 |
| Finished | Oct 03 02:01:44 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562869059 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2562869059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.1134394204 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 397561920 ps |
| CPU time | 11.1 seconds |
| Started | Oct 03 02:01:37 AM UTC 24 |
| Finished | Oct 03 02:01:50 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134394204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1134394204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.55979842 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 35394000 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 02:01:33 AM UTC 24 |
| Finished | Oct 03 02:01:38 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55979842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.55979842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.261095257 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 41086646891 ps |
| CPU time | 144.78 seconds |
| Started | Oct 03 02:01:39 AM UTC 24 |
| Finished | Oct 03 02:04:06 AM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261095257 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.261095257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.2069393443 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 359275285 ps |
| CPU time | 9.49 seconds |
| Started | Oct 03 02:01:39 AM UTC 24 |
| Finished | Oct 03 02:01:49 AM UTC 24 |
| Peak memory | 231604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2069393443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymg r_stress_all_with_rand_reset.2069393443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.851201294 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 669871677 ps |
| CPU time | 15.51 seconds |
| Started | Oct 03 02:01:36 AM UTC 24 |
| Finished | Oct 03 02:01:53 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851201294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.851201294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.3914440348 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 100631390 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 02:01:38 AM UTC 24 |
| Finished | Oct 03 02:01:41 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914440348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3914440348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2219394859 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 34665493 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 02:01:46 AM UTC 24 |
| Finished | Oct 03 02:01:48 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219394859 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2219394859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3341420320 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 265180008 ps |
| CPU time | 9.94 seconds |
| Started | Oct 03 02:01:42 AM UTC 24 |
| Finished | Oct 03 02:01:53 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341420320 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3341420320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.903518813 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 75779596 ps |
| CPU time | 3.85 seconds |
| Started | Oct 03 02:01:45 AM UTC 24 |
| Finished | Oct 03 02:01:50 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903518813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.903518813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.1535664532 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 136965746 ps |
| CPU time | 3.69 seconds |
| Started | Oct 03 02:01:42 AM UTC 24 |
| Finished | Oct 03 02:01:47 AM UTC 24 |
| Peak memory | 219648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535664532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1535664532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.2213251948 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 34228899 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 02:01:43 AM UTC 24 |
| Finished | Oct 03 02:01:46 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213251948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2213251948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.1327961099 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 32259803 ps |
| CPU time | 2.8 seconds |
| Started | Oct 03 02:01:44 AM UTC 24 |
| Finished | Oct 03 02:01:48 AM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327961099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1327961099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.801657672 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 171667559 ps |
| CPU time | 4.5 seconds |
| Started | Oct 03 02:01:42 AM UTC 24 |
| Finished | Oct 03 02:01:48 AM UTC 24 |
| Peak memory | 217208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801657672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.801657672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_random.2249881762 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 247962790 ps |
| CPU time | 8.07 seconds |
| Started | Oct 03 02:01:42 AM UTC 24 |
| Finished | Oct 03 02:01:51 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249881762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2249881762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.2766713297 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 62807932 ps |
| CPU time | 3.68 seconds |
| Started | Oct 03 02:01:40 AM UTC 24 |
| Finished | Oct 03 02:01:45 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766713297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2766713297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.914837337 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1446688017 ps |
| CPU time | 6.63 seconds |
| Started | Oct 03 02:01:41 AM UTC 24 |
| Finished | Oct 03 02:01:49 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914837337 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.914837337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.761798298 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 233408568 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 02:01:40 AM UTC 24 |
| Finished | Oct 03 02:01:45 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761798298 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.761798298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.903303402 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1749271731 ps |
| CPU time | 7.13 seconds |
| Started | Oct 03 02:01:41 AM UTC 24 |
| Finished | Oct 03 02:01:49 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903303402 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.903303402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.4137117708 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 67649385 ps |
| CPU time | 3.16 seconds |
| Started | Oct 03 02:01:45 AM UTC 24 |
| Finished | Oct 03 02:01:49 AM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137117708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4137117708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.2826056737 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1867469451 ps |
| CPU time | 16.38 seconds |
| Started | Oct 03 02:01:40 AM UTC 24 |
| Finished | Oct 03 02:01:57 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826056737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2826056737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.3122645472 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 9779068797 ps |
| CPU time | 78.53 seconds |
| Started | Oct 03 02:01:45 AM UTC 24 |
| Finished | Oct 03 02:03:05 AM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122645472 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3122645472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.2057539728 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 728590946 ps |
| CPU time | 11.91 seconds |
| Started | Oct 03 02:01:46 AM UTC 24 |
| Finished | Oct 03 02:01:59 AM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2057539728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg r_stress_all_with_rand_reset.2057539728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.596337056 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1600345659 ps |
| CPU time | 8.42 seconds |
| Started | Oct 03 02:01:42 AM UTC 24 |
| Finished | Oct 03 02:01:52 AM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596337056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.596337056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.1080861907 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 12201771 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 02:01:51 AM UTC 24 |
| Finished | Oct 03 02:01:54 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080861907 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1080861907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.378701370 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 34430945 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 02:01:49 AM UTC 24 |
| Finished | Oct 03 02:01:53 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378701370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.378701370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.3113200416 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 512927981 ps |
| CPU time | 5.01 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:01:56 AM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113200416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3113200416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.3748892219 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 138998837 ps |
| CPU time | 6.71 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:01:58 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748892219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3748892219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.2121550240 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 616141801 ps |
| CPU time | 5.9 seconds |
| Started | Oct 03 02:01:49 AM UTC 24 |
| Finished | Oct 03 02:01:56 AM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121550240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2121550240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_random.4005535483 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 102652607 ps |
| CPU time | 5.74 seconds |
| Started | Oct 03 02:01:49 AM UTC 24 |
| Finished | Oct 03 02:01:55 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005535483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4005535483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.4083585347 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 152860300 ps |
| CPU time | 5.9 seconds |
| Started | Oct 03 02:01:49 AM UTC 24 |
| Finished | Oct 03 02:01:56 AM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083585347 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4083585347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.3596881348 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 48311321 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 02:01:47 AM UTC 24 |
| Finished | Oct 03 02:01:51 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596881348 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3596881348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.782465318 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4643978277 ps |
| CPU time | 30.32 seconds |
| Started | Oct 03 02:01:49 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782465318 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.782465318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.3293084541 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3719479862 ps |
| CPU time | 26.62 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:02:18 AM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293084541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3293084541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.2236693887 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 565602991 ps |
| CPU time | 5.26 seconds |
| Started | Oct 03 02:01:47 AM UTC 24 |
| Finished | Oct 03 02:01:54 AM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236693887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2236693887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.1927801896 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2326499559 ps |
| CPU time | 29.87 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:02:22 AM UTC 24 |
| Peak memory | 232000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1927801896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg r_stress_all_with_rand_reset.1927801896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.3544193362 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 199886180 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:01:54 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544193362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3544193362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.2506094195 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 53957902 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 02:01:50 AM UTC 24 |
| Finished | Oct 03 02:01:55 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506094195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2506094195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.692315279 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 37708759 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 02:01:58 AM UTC 24 |
| Finished | Oct 03 02:02:00 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692315279 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.692315279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.4024636844 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 798179395 ps |
| CPU time | 9.53 seconds |
| Started | Oct 03 02:01:54 AM UTC 24 |
| Finished | Oct 03 02:02:05 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024636844 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4024636844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.523864375 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 29536800 ps |
| CPU time | 2.95 seconds |
| Started | Oct 03 02:01:56 AM UTC 24 |
| Finished | Oct 03 02:02:00 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523864375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.523864375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.3127874417 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1107746710 ps |
| CPU time | 17.52 seconds |
| Started | Oct 03 02:01:54 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127874417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3127874417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.3434224489 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 33212786 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 02:01:55 AM UTC 24 |
| Finished | Oct 03 02:01:58 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434224489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3434224489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.71107567 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 125251995 ps |
| CPU time | 2.78 seconds |
| Started | Oct 03 02:01:56 AM UTC 24 |
| Finished | Oct 03 02:02:00 AM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71107567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.71107567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.2851613358 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 182890802 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 02:01:54 AM UTC 24 |
| Finished | Oct 03 02:01:58 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851613358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2851613358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_random.1226255445 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 487608191 ps |
| CPU time | 6.63 seconds |
| Started | Oct 03 02:01:54 AM UTC 24 |
| Finished | Oct 03 02:02:02 AM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226255445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1226255445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.4197224305 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 652855118 ps |
| CPU time | 7.55 seconds |
| Started | Oct 03 02:01:53 AM UTC 24 |
| Finished | Oct 03 02:02:01 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197224305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4197224305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.725107506 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 83819693 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 02:01:53 AM UTC 24 |
| Finished | Oct 03 02:01:58 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725107506 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.725107506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.2913029602 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 80481424 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 02:01:53 AM UTC 24 |
| Finished | Oct 03 02:01:58 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913029602 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2913029602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.3283303546 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 63694069 ps |
| CPU time | 2.64 seconds |
| Started | Oct 03 02:01:53 AM UTC 24 |
| Finished | Oct 03 02:01:56 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283303546 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3283303546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.2033219999 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 766730431 ps |
| CPU time | 17.11 seconds |
| Started | Oct 03 02:01:56 AM UTC 24 |
| Finished | Oct 03 02:02:15 AM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033219999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2033219999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.2424035851 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 2277053021 ps |
| CPU time | 16.01 seconds |
| Started | Oct 03 02:01:51 AM UTC 24 |
| Finished | Oct 03 02:02:09 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424035851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2424035851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.219874393 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1462322862 ps |
| CPU time | 27.76 seconds |
| Started | Oct 03 02:01:57 AM UTC 24 |
| Finished | Oct 03 02:02:26 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219874393 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.219874393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.2649663373 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5876266810 ps |
| CPU time | 11.85 seconds |
| Started | Oct 03 02:01:58 AM UTC 24 |
| Finished | Oct 03 02:02:11 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2649663373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.2649663373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.3235957610 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1513146850 ps |
| CPU time | 10.98 seconds |
| Started | Oct 03 02:01:55 AM UTC 24 |
| Finished | Oct 03 02:02:07 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235957610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3235957610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.3607143490 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 305360282 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 02:01:56 AM UTC 24 |
| Finished | Oct 03 02:02:01 AM UTC 24 |
| Peak memory | 217400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607143490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3607143490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.646413377 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 13364319 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 02:02:04 AM UTC 24 |
| Finished | Oct 03 02:02:06 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646413377 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.646413377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.57518490 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 128817883 ps |
| CPU time | 3.31 seconds |
| Started | Oct 03 02:02:00 AM UTC 24 |
| Finished | Oct 03 02:02:05 AM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57518490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.57518490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.3821169760 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 149709302 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 02:02:03 AM UTC 24 |
| Finished | Oct 03 02:02:07 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821169760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3821169760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.3470838336 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 60398594 ps |
| CPU time | 3.06 seconds |
| Started | Oct 03 02:02:00 AM UTC 24 |
| Finished | Oct 03 02:02:04 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470838336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3470838336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.3301016808 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 80536928 ps |
| CPU time | 4.94 seconds |
| Started | Oct 03 02:02:02 AM UTC 24 |
| Finished | Oct 03 02:02:08 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301016808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3301016808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.4202229839 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 70644705 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 02:02:03 AM UTC 24 |
| Finished | Oct 03 02:02:06 AM UTC 24 |
| Peak memory | 223352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202229839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4202229839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_random.4032167807 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 27276297576 ps |
| CPU time | 88.35 seconds |
| Started | Oct 03 02:01:59 AM UTC 24 |
| Finished | Oct 03 02:03:29 AM UTC 24 |
| Peak memory | 231680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032167807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4032167807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3482066335 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 60975317 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 02:01:59 AM UTC 24 |
| Finished | Oct 03 02:02:03 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482066335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3482066335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.1758047230 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 302523300 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 02:01:59 AM UTC 24 |
| Finished | Oct 03 02:02:04 AM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758047230 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1758047230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.3342229035 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 21340657 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 02:01:59 AM UTC 24 |
| Finished | Oct 03 02:02:02 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342229035 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3342229035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.4019984933 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 320769531 ps |
| CPU time | 5.59 seconds |
| Started | Oct 03 02:01:59 AM UTC 24 |
| Finished | Oct 03 02:02:06 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019984933 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4019984933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.961550647 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 422750176 ps |
| CPU time | 6.69 seconds |
| Started | Oct 03 02:02:03 AM UTC 24 |
| Finished | Oct 03 02:02:10 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961550647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.961550647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.3242336810 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 40753053 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 02:01:59 AM UTC 24 |
| Finished | Oct 03 02:02:03 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242336810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3242336810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.2759504099 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 881625789 ps |
| CPU time | 19.36 seconds |
| Started | Oct 03 02:02:04 AM UTC 24 |
| Finished | Oct 03 02:02:25 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759504099 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2759504099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.4197073985 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 416007772 ps |
| CPU time | 9.25 seconds |
| Started | Oct 03 02:02:01 AM UTC 24 |
| Finished | Oct 03 02:02:12 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197073985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4197073985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.4052720944 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 41282201 ps |
| CPU time | 3.48 seconds |
| Started | Oct 03 02:02:03 AM UTC 24 |
| Finished | Oct 03 02:02:07 AM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052720944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4052720944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.3864065619 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 62837109 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:40 AM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864065619 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3864065619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.1111905070 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 41270867 ps |
| CPU time | 3.3 seconds |
| Started | Oct 03 01:58:35 AM UTC 24 |
| Finished | Oct 03 01:58:39 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111905070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1111905070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.4132039304 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 122973673 ps |
| CPU time | 3.87 seconds |
| Started | Oct 03 01:58:36 AM UTC 24 |
| Finished | Oct 03 01:58:41 AM UTC 24 |
| Peak memory | 225808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132039304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4132039304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.2313942032 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 135123456 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 01:58:36 AM UTC 24 |
| Finished | Oct 03 01:58:41 AM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313942032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2313942032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2350743387 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 261189093 ps |
| CPU time | 3.64 seconds |
| Started | Oct 03 01:58:35 AM UTC 24 |
| Finished | Oct 03 01:58:40 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350743387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2350743387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_random.1331287375 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 145764409 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 01:58:34 AM UTC 24 |
| Finished | Oct 03 01:58:38 AM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331287375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1331287375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.2325763510 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1029907767 ps |
| CPU time | 16.14 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:54 AM UTC 24 |
| Peak memory | 253592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325763510 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2325763510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.2010134029 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 417042736 ps |
| CPU time | 5.02 seconds |
| Started | Oct 03 01:58:34 AM UTC 24 |
| Finished | Oct 03 01:58:40 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010134029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2010134029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.1172027530 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 106601806 ps |
| CPU time | 3 seconds |
| Started | Oct 03 01:58:34 AM UTC 24 |
| Finished | Oct 03 01:58:38 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172027530 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1172027530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.2104732013 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 813922143 ps |
| CPU time | 22.56 seconds |
| Started | Oct 03 01:58:34 AM UTC 24 |
| Finished | Oct 03 01:58:58 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104732013 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2104732013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.3361994227 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 330876087 ps |
| CPU time | 2.8 seconds |
| Started | Oct 03 01:58:34 AM UTC 24 |
| Finished | Oct 03 01:58:38 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361994227 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3361994227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.3512607277 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4437519802 ps |
| CPU time | 12.79 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:50 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512607277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3512607277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.3417271342 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 22079435 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 01:58:32 AM UTC 24 |
| Finished | Oct 03 01:58:35 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417271342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3417271342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.2397408830 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 534482606 ps |
| CPU time | 19.22 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:57 AM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397408830 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2397408830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.1288564208 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1162795432 ps |
| CPU time | 11.08 seconds |
| Started | Oct 03 01:58:35 AM UTC 24 |
| Finished | Oct 03 01:58:47 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288564208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1288564208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.161736183 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 174801291 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:40 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161736183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.161736183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.2338401434 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 40695351 ps |
| CPU time | 1 seconds |
| Started | Oct 03 02:02:12 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338401434 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2338401434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.2490246728 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 220163308 ps |
| CPU time | 12.68 seconds |
| Started | Oct 03 02:02:07 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490246728 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2490246728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.2456783540 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5088500749 ps |
| CPU time | 35.25 seconds |
| Started | Oct 03 02:02:08 AM UTC 24 |
| Finished | Oct 03 02:02:45 AM UTC 24 |
| Peak memory | 232012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456783540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2456783540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.3833689166 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 126651169 ps |
| CPU time | 3.28 seconds |
| Started | Oct 03 02:02:07 AM UTC 24 |
| Finished | Oct 03 02:02:11 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833689166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3833689166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.1473779499 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 299082571 ps |
| CPU time | 4 seconds |
| Started | Oct 03 02:02:08 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 223336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473779499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1473779499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.979652136 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 159195163 ps |
| CPU time | 4.93 seconds |
| Started | Oct 03 02:02:08 AM UTC 24 |
| Finished | Oct 03 02:02:14 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979652136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.979652136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_random.4184450780 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 277836676 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 02:02:07 AM UTC 24 |
| Finished | Oct 03 02:02:11 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184450780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4184450780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.1826218621 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 974526408 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 02:02:05 AM UTC 24 |
| Finished | Oct 03 02:02:11 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826218621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1826218621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.36881518 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 579758795 ps |
| CPU time | 7.28 seconds |
| Started | Oct 03 02:02:05 AM UTC 24 |
| Finished | Oct 03 02:02:14 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36881518 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.36881518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.3658022779 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2738038784 ps |
| CPU time | 26.6 seconds |
| Started | Oct 03 02:02:05 AM UTC 24 |
| Finished | Oct 03 02:02:33 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658022779 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3658022779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.2819524716 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 555362468 ps |
| CPU time | 6.34 seconds |
| Started | Oct 03 02:02:05 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819524716 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2819524716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.1665744950 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 62369685 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 02:02:08 AM UTC 24 |
| Finished | Oct 03 02:02:12 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665744950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1665744950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.4047989987 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 64477029 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 02:02:04 AM UTC 24 |
| Finished | Oct 03 02:02:08 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047989987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4047989987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.23863784 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 17959759771 ps |
| CPU time | 113 seconds |
| Started | Oct 03 02:02:09 AM UTC 24 |
| Finished | Oct 03 02:04:05 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23863784 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.23863784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.1153369466 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 998077773 ps |
| CPU time | 7.17 seconds |
| Started | Oct 03 02:02:11 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1153369466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.1153369466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2345674278 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 621210341 ps |
| CPU time | 10.63 seconds |
| Started | Oct 03 02:02:08 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345674278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2345674278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.2215577934 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 40812092 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 02:02:09 AM UTC 24 |
| Finished | Oct 03 02:02:13 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215577934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2215577934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.66434149 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 8831553 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 02:02:17 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66434149 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.66434149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.1486815875 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 496250259 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 02:02:13 AM UTC 24 |
| Finished | Oct 03 02:02:18 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486815875 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1486815875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.2906977318 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 137276759 ps |
| CPU time | 5.66 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:22 AM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906977318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2906977318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.1345543074 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 72964121 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:19 AM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345543074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1345543074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.2510152125 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 179500724 ps |
| CPU time | 4.18 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510152125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2510152125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.2765830889 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 129677929 ps |
| CPU time | 6.27 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:22 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765830889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2765830889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.3204998375 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 98388183 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:22 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204998375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3204998375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_random.2932640305 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 156367589 ps |
| CPU time | 3.74 seconds |
| Started | Oct 03 02:02:13 AM UTC 24 |
| Finished | Oct 03 02:02:18 AM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932640305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2932640305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.952738783 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 167943837 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 02:02:12 AM UTC 24 |
| Finished | Oct 03 02:02:17 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952738783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.952738783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.2229171561 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 67197095 ps |
| CPU time | 3.55 seconds |
| Started | Oct 03 02:02:12 AM UTC 24 |
| Finished | Oct 03 02:02:16 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229171561 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2229171561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.1776565239 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 107375275 ps |
| CPU time | 3.69 seconds |
| Started | Oct 03 02:02:12 AM UTC 24 |
| Finished | Oct 03 02:02:16 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776565239 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1776565239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.137861423 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 337342540 ps |
| CPU time | 3.83 seconds |
| Started | Oct 03 02:02:13 AM UTC 24 |
| Finished | Oct 03 02:02:18 AM UTC 24 |
| Peak memory | 217544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137861423 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.137861423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.2596229410 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 131177425 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:20 AM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596229410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2596229410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.964757968 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 66758233 ps |
| CPU time | 2.92 seconds |
| Started | Oct 03 02:02:12 AM UTC 24 |
| Finished | Oct 03 02:02:15 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964757968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.964757968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.478796715 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2487418993 ps |
| CPU time | 15.76 seconds |
| Started | Oct 03 02:02:16 AM UTC 24 |
| Finished | Oct 03 02:02:33 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478796715 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.478796715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.910444816 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1782309204 ps |
| CPU time | 17.17 seconds |
| Started | Oct 03 02:02:16 AM UTC 24 |
| Finished | Oct 03 02:02:35 AM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=910444816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr _stress_all_with_rand_reset.910444816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.3772561978 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 460552007 ps |
| CPU time | 5.56 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:22 AM UTC 24 |
| Peak memory | 217220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772561978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3772561978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.3643828506 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2277698882 ps |
| CPU time | 5.03 seconds |
| Started | Oct 03 02:02:14 AM UTC 24 |
| Finished | Oct 03 02:02:21 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643828506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3643828506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.2073314238 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 16411133 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 02:02:22 AM UTC 24 |
| Finished | Oct 03 02:02:24 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073314238 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2073314238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.2020135795 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 145436995 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 02:02:19 AM UTC 24 |
| Finished | Oct 03 02:02:23 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020135795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2020135795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.2414480866 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1641586744 ps |
| CPU time | 4.82 seconds |
| Started | Oct 03 02:02:21 AM UTC 24 |
| Finished | Oct 03 02:02:26 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414480866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2414480866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.346631675 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 30214328 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 02:02:21 AM UTC 24 |
| Finished | Oct 03 02:02:25 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346631675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.346631675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.4274661298 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1453193374 ps |
| CPU time | 4.12 seconds |
| Started | Oct 03 02:02:20 AM UTC 24 |
| Finished | Oct 03 02:02:26 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274661298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4274661298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_random.1485039353 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 117433075 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 02:02:19 AM UTC 24 |
| Finished | Oct 03 02:02:24 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485039353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1485039353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.2764807803 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 130256915 ps |
| CPU time | 5.55 seconds |
| Started | Oct 03 02:02:17 AM UTC 24 |
| Finished | Oct 03 02:02:24 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764807803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2764807803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.132586537 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 104254255 ps |
| CPU time | 3.56 seconds |
| Started | Oct 03 02:02:18 AM UTC 24 |
| Finished | Oct 03 02:02:23 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132586537 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.132586537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.2840338061 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 33557245 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 02:02:17 AM UTC 24 |
| Finished | Oct 03 02:02:21 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840338061 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2840338061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.19774545 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 838843232 ps |
| CPU time | 14.41 seconds |
| Started | Oct 03 02:02:19 AM UTC 24 |
| Finished | Oct 03 02:02:35 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19774545 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.19774545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.1461020634 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1288574382 ps |
| CPU time | 7.27 seconds |
| Started | Oct 03 02:02:22 AM UTC 24 |
| Finished | Oct 03 02:02:30 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461020634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1461020634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.4269184823 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 67385774 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 02:02:17 AM UTC 24 |
| Finished | Oct 03 02:02:21 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269184823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4269184823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.1074112516 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 104295013 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 02:02:21 AM UTC 24 |
| Finished | Oct 03 02:02:25 AM UTC 24 |
| Peak memory | 215276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074112516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1074112516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.849519942 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 323247393 ps |
| CPU time | 9.61 seconds |
| Started | Oct 03 02:02:22 AM UTC 24 |
| Finished | Oct 03 02:02:33 AM UTC 24 |
| Peak memory | 219560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849519942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.849519942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.1702549249 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 22750444 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 02:02:27 AM UTC 24 |
| Finished | Oct 03 02:02:30 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702549249 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1702549249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.3196235046 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 62639071 ps |
| CPU time | 4.12 seconds |
| Started | Oct 03 02:02:24 AM UTC 24 |
| Finished | Oct 03 02:02:29 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196235046 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3196235046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.2104988192 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 70133999 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 02:02:26 AM UTC 24 |
| Finished | Oct 03 02:02:29 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104988192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2104988192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.3270957421 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 63891026 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 02:02:24 AM UTC 24 |
| Finished | Oct 03 02:02:27 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270957421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3270957421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.1228688131 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 212932649 ps |
| CPU time | 6.04 seconds |
| Started | Oct 03 02:02:25 AM UTC 24 |
| Finished | Oct 03 02:02:32 AM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228688131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1228688131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1434703476 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 146361113 ps |
| CPU time | 6.11 seconds |
| Started | Oct 03 02:02:25 AM UTC 24 |
| Finished | Oct 03 02:02:32 AM UTC 24 |
| Peak memory | 231436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434703476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1434703476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.1867187037 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 94110547 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 02:02:24 AM UTC 24 |
| Finished | Oct 03 02:02:29 AM UTC 24 |
| Peak memory | 231548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867187037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1867187037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_random.125721137 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 352462386 ps |
| CPU time | 5.82 seconds |
| Started | Oct 03 02:02:24 AM UTC 24 |
| Finished | Oct 03 02:02:31 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125721137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.125721137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.3254183729 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 98700888 ps |
| CPU time | 4.69 seconds |
| Started | Oct 03 02:02:22 AM UTC 24 |
| Finished | Oct 03 02:02:28 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254183729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3254183729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.3514538879 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 138791346 ps |
| CPU time | 5.28 seconds |
| Started | Oct 03 02:02:23 AM UTC 24 |
| Finished | Oct 03 02:02:30 AM UTC 24 |
| Peak memory | 215348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514538879 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3514538879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.3205382376 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 125955483 ps |
| CPU time | 3.21 seconds |
| Started | Oct 03 02:02:23 AM UTC 24 |
| Finished | Oct 03 02:02:28 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205382376 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3205382376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.1405155639 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 45220451 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 02:02:24 AM UTC 24 |
| Finished | Oct 03 02:02:28 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405155639 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1405155639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.1023261810 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 34914137 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 02:02:26 AM UTC 24 |
| Finished | Oct 03 02:02:29 AM UTC 24 |
| Peak memory | 224932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023261810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1023261810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.2327286714 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 819578317 ps |
| CPU time | 3.47 seconds |
| Started | Oct 03 02:02:22 AM UTC 24 |
| Finished | Oct 03 02:02:27 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327286714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2327286714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.932428836 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1564243238 ps |
| CPU time | 12.64 seconds |
| Started | Oct 03 02:02:26 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 225472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932428836 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.932428836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.4134087747 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 516871388 ps |
| CPU time | 17.82 seconds |
| Started | Oct 03 02:02:25 AM UTC 24 |
| Finished | Oct 03 02:02:44 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134087747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4134087747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.1702618109 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 46726237 ps |
| CPU time | 3.18 seconds |
| Started | Oct 03 02:02:26 AM UTC 24 |
| Finished | Oct 03 02:02:30 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702618109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1702618109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.1920044870 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 16459577 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 02:02:32 AM UTC 24 |
| Finished | Oct 03 02:02:34 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920044870 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1920044870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.3303468135 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 184600809 ps |
| CPU time | 9.98 seconds |
| Started | Oct 03 02:02:29 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303468135 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3303468135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.1104217913 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 105795208 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 02:02:30 AM UTC 24 |
| Finished | Oct 03 02:02:34 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104217913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1104217913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.2004438740 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 63461361 ps |
| CPU time | 2.43 seconds |
| Started | Oct 03 02:02:30 AM UTC 24 |
| Finished | Oct 03 02:02:34 AM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004438740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2004438740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1062762950 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 129116511 ps |
| CPU time | 5.16 seconds |
| Started | Oct 03 02:02:30 AM UTC 24 |
| Finished | Oct 03 02:02:37 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062762950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1062762950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.2255250939 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 479250290 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 02:02:30 AM UTC 24 |
| Finished | Oct 03 02:02:35 AM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255250939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2255250939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.1383489723 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 179635431 ps |
| CPU time | 7.98 seconds |
| Started | Oct 03 02:02:30 AM UTC 24 |
| Finished | Oct 03 02:02:39 AM UTC 24 |
| Peak memory | 231444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383489723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1383489723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_random.1116693787 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 110494480 ps |
| CPU time | 7.01 seconds |
| Started | Oct 03 02:02:29 AM UTC 24 |
| Finished | Oct 03 02:02:37 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116693787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1116693787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.3536550326 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 146822380 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 02:02:28 AM UTC 24 |
| Finished | Oct 03 02:02:32 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536550326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3536550326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.2265041384 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 98525299 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 02:02:29 AM UTC 24 |
| Finished | Oct 03 02:02:35 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265041384 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2265041384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.605085235 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 221948873 ps |
| CPU time | 7.15 seconds |
| Started | Oct 03 02:02:28 AM UTC 24 |
| Finished | Oct 03 02:02:36 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605085235 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.605085235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.3342430077 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 194973270 ps |
| CPU time | 4.97 seconds |
| Started | Oct 03 02:02:29 AM UTC 24 |
| Finished | Oct 03 02:02:35 AM UTC 24 |
| Peak memory | 217340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342430077 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3342430077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1560562377 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 199513735 ps |
| CPU time | 3.25 seconds |
| Started | Oct 03 02:02:31 AM UTC 24 |
| Finished | Oct 03 02:02:36 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560562377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1560562377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.2611319658 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 457083731 ps |
| CPU time | 10.62 seconds |
| Started | Oct 03 02:02:28 AM UTC 24 |
| Finished | Oct 03 02:02:39 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611319658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2611319658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.2590021343 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3517009648 ps |
| CPU time | 37.22 seconds |
| Started | Oct 03 02:02:32 AM UTC 24 |
| Finished | Oct 03 02:03:10 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590021343 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2590021343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all_with_rand_reset.3800272148 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 676882602 ps |
| CPU time | 18.44 seconds |
| Started | Oct 03 02:02:32 AM UTC 24 |
| Finished | Oct 03 02:02:51 AM UTC 24 |
| Peak memory | 231596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3800272148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymg r_stress_all_with_rand_reset.3800272148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.3642091369 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 105675310 ps |
| CPU time | 3.32 seconds |
| Started | Oct 03 02:02:30 AM UTC 24 |
| Finished | Oct 03 02:02:35 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642091369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3642091369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.800526031 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 291166484 ps |
| CPU time | 3.58 seconds |
| Started | Oct 03 02:02:32 AM UTC 24 |
| Finished | Oct 03 02:02:36 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800526031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.800526031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.2276840299 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 12986490 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 02:02:38 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276840299 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2276840299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.3368155206 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 34349077 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 02:02:34 AM UTC 24 |
| Finished | Oct 03 02:02:39 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368155206 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3368155206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.1033599819 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 309990878 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 02:02:35 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033599819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1033599819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.875165651 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 593921114 ps |
| CPU time | 5.55 seconds |
| Started | Oct 03 02:02:35 AM UTC 24 |
| Finished | Oct 03 02:02:42 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875165651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.875165651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.1420770245 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 476174554 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 02:02:36 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420770245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1420770245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.1911701656 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 79152467 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 02:02:35 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 231408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911701656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1911701656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_random.3456306156 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 265180470 ps |
| CPU time | 3.78 seconds |
| Started | Oct 03 02:02:34 AM UTC 24 |
| Finished | Oct 03 02:02:39 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456306156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3456306156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.258252805 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 929147336 ps |
| CPU time | 6.11 seconds |
| Started | Oct 03 02:02:33 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258252805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.258252805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.3903934293 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 529248474 ps |
| CPU time | 7.58 seconds |
| Started | Oct 03 02:02:34 AM UTC 24 |
| Finished | Oct 03 02:02:43 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903934293 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3903934293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.3475540122 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 166409420 ps |
| CPU time | 4.3 seconds |
| Started | Oct 03 02:02:33 AM UTC 24 |
| Finished | Oct 03 02:02:38 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475540122 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3475540122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.1060567874 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 410541445 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 02:02:34 AM UTC 24 |
| Finished | Oct 03 02:02:40 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060567874 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1060567874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.2179172723 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 210567252 ps |
| CPU time | 3.28 seconds |
| Started | Oct 03 02:02:37 AM UTC 24 |
| Finished | Oct 03 02:02:41 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179172723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2179172723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.3464346497 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 254449119 ps |
| CPU time | 2.84 seconds |
| Started | Oct 03 02:02:33 AM UTC 24 |
| Finished | Oct 03 02:02:37 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464346497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3464346497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.917643006 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1006914434 ps |
| CPU time | 9.26 seconds |
| Started | Oct 03 02:02:37 AM UTC 24 |
| Finished | Oct 03 02:02:47 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917643006 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.917643006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.2931654996 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 47863434 ps |
| CPU time | 4.11 seconds |
| Started | Oct 03 02:02:35 AM UTC 24 |
| Finished | Oct 03 02:02:41 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931654996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2931654996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.4226256018 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 40588524 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 02:02:42 AM UTC 24 |
| Finished | Oct 03 02:02:44 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226256018 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4226256018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.482603299 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 712953571 ps |
| CPU time | 35.17 seconds |
| Started | Oct 03 02:02:40 AM UTC 24 |
| Finished | Oct 03 02:03:17 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482603299 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.482603299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.4273929589 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 74446272 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 02:02:41 AM UTC 24 |
| Finished | Oct 03 02:02:44 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273929589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.4273929589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.958260832 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 51129851 ps |
| CPU time | 3.12 seconds |
| Started | Oct 03 02:02:41 AM UTC 24 |
| Finished | Oct 03 02:02:45 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958260832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.958260832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.1777061032 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 105239663 ps |
| CPU time | 3.2 seconds |
| Started | Oct 03 02:02:41 AM UTC 24 |
| Finished | Oct 03 02:02:45 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777061032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1777061032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.2032206441 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 77068207 ps |
| CPU time | 3.53 seconds |
| Started | Oct 03 02:02:41 AM UTC 24 |
| Finished | Oct 03 02:02:45 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032206441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2032206441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.2092284443 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 221469983 ps |
| CPU time | 6.63 seconds |
| Started | Oct 03 02:02:41 AM UTC 24 |
| Finished | Oct 03 02:02:48 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092284443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2092284443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_random.3788057935 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 19896376576 ps |
| CPU time | 86.21 seconds |
| Started | Oct 03 02:02:40 AM UTC 24 |
| Finished | Oct 03 02:04:09 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788057935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3788057935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.844449663 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 256899447 ps |
| CPU time | 4.46 seconds |
| Started | Oct 03 02:02:38 AM UTC 24 |
| Finished | Oct 03 02:02:44 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844449663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.844449663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.2866669336 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 605969616 ps |
| CPU time | 21.78 seconds |
| Started | Oct 03 02:02:38 AM UTC 24 |
| Finished | Oct 03 02:03:01 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866669336 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2866669336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.4131375622 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 270603085 ps |
| CPU time | 5.42 seconds |
| Started | Oct 03 02:02:38 AM UTC 24 |
| Finished | Oct 03 02:02:45 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131375622 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.4131375622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.1871742926 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 114259332 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 02:02:39 AM UTC 24 |
| Finished | Oct 03 02:02:44 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871742926 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1871742926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.3565214353 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 106984549 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 02:02:42 AM UTC 24 |
| Finished | Oct 03 02:02:46 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565214353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3565214353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.3156887685 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1216432489 ps |
| CPU time | 18.24 seconds |
| Started | Oct 03 02:02:38 AM UTC 24 |
| Finished | Oct 03 02:02:57 AM UTC 24 |
| Peak memory | 217196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156887685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3156887685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.1085840746 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 504864767 ps |
| CPU time | 3.33 seconds |
| Started | Oct 03 02:02:42 AM UTC 24 |
| Finished | Oct 03 02:02:46 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085840746 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1085840746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.3691551116 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 362711344 ps |
| CPU time | 4.98 seconds |
| Started | Oct 03 02:02:41 AM UTC 24 |
| Finished | Oct 03 02:02:47 AM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691551116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3691551116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.2199851097 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 47254074 ps |
| CPU time | 3.08 seconds |
| Started | Oct 03 02:02:42 AM UTC 24 |
| Finished | Oct 03 02:02:46 AM UTC 24 |
| Peak memory | 217340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199851097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2199851097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.1761951195 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 39453144 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 02:02:47 AM UTC 24 |
| Finished | Oct 03 02:02:50 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761951195 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1761951195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.1955635139 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 48724163 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 02:02:45 AM UTC 24 |
| Finished | Oct 03 02:02:49 AM UTC 24 |
| Peak memory | 225592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955635139 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1955635139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.1987561401 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 608109751 ps |
| CPU time | 3.47 seconds |
| Started | Oct 03 02:02:45 AM UTC 24 |
| Finished | Oct 03 02:02:49 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987561401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1987561401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.1390826435 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 75516482 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 02:02:45 AM UTC 24 |
| Finished | Oct 03 02:02:50 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390826435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1390826435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.1776549869 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 35020421 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 02:02:46 AM UTC 24 |
| Finished | Oct 03 02:02:50 AM UTC 24 |
| Peak memory | 225396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776549869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1776549869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.2872947963 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 545899693 ps |
| CPU time | 4.46 seconds |
| Started | Oct 03 02:02:45 AM UTC 24 |
| Finished | Oct 03 02:02:50 AM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872947963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2872947963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_random.1664881416 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 368475384 ps |
| CPU time | 5.97 seconds |
| Started | Oct 03 02:02:45 AM UTC 24 |
| Finished | Oct 03 02:02:52 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664881416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1664881416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.3652830181 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 55476453 ps |
| CPU time | 3.29 seconds |
| Started | Oct 03 02:02:42 AM UTC 24 |
| Finished | Oct 03 02:02:47 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652830181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3652830181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.2972212570 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 92347487 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 02:02:43 AM UTC 24 |
| Finished | Oct 03 02:02:48 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972212570 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2972212570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.3171100827 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 295114009 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 02:02:43 AM UTC 24 |
| Finished | Oct 03 02:02:48 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171100827 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3171100827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.2788322352 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 840985430 ps |
| CPU time | 8.19 seconds |
| Started | Oct 03 02:02:44 AM UTC 24 |
| Finished | Oct 03 02:02:53 AM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788322352 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2788322352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.2408368623 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 325460150 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 02:02:46 AM UTC 24 |
| Finished | Oct 03 02:02:50 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408368623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2408368623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.952842389 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 85464811 ps |
| CPU time | 4.06 seconds |
| Started | Oct 03 02:02:42 AM UTC 24 |
| Finished | Oct 03 02:02:47 AM UTC 24 |
| Peak memory | 217456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952842389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.952842389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.3551131188 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2542312403 ps |
| CPU time | 34.37 seconds |
| Started | Oct 03 02:02:46 AM UTC 24 |
| Finished | Oct 03 02:03:22 AM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551131188 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3551131188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.3967235126 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 102312501 ps |
| CPU time | 8.44 seconds |
| Started | Oct 03 02:02:46 AM UTC 24 |
| Finished | Oct 03 02:02:57 AM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3967235126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.3967235126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.1118761664 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 864092164 ps |
| CPU time | 5.47 seconds |
| Started | Oct 03 02:02:45 AM UTC 24 |
| Finished | Oct 03 02:02:51 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118761664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1118761664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.3028920086 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 467522144 ps |
| CPU time | 2 seconds |
| Started | Oct 03 02:02:46 AM UTC 24 |
| Finished | Oct 03 02:02:49 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028920086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3028920086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2225511246 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 14438540 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 02:02:52 AM UTC 24 |
| Finished | Oct 03 02:02:54 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225511246 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2225511246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.2228937279 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 80537600 ps |
| CPU time | 4.09 seconds |
| Started | Oct 03 02:02:49 AM UTC 24 |
| Finished | Oct 03 02:02:54 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228937279 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2228937279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.206047821 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 589931798 ps |
| CPU time | 4.06 seconds |
| Started | Oct 03 02:02:50 AM UTC 24 |
| Finished | Oct 03 02:02:55 AM UTC 24 |
| Peak memory | 230876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206047821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.206047821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.3418994644 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 707749149 ps |
| CPU time | 5.77 seconds |
| Started | Oct 03 02:02:49 AM UTC 24 |
| Finished | Oct 03 02:02:56 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418994644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3418994644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.4284138774 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 407257810 ps |
| CPU time | 3.86 seconds |
| Started | Oct 03 02:02:50 AM UTC 24 |
| Finished | Oct 03 02:02:55 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284138774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.4284138774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.854349814 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1417848751 ps |
| CPU time | 7.53 seconds |
| Started | Oct 03 02:02:50 AM UTC 24 |
| Finished | Oct 03 02:02:59 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854349814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.854349814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.3423156371 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 33800104 ps |
| CPU time | 3.09 seconds |
| Started | Oct 03 02:02:49 AM UTC 24 |
| Finished | Oct 03 02:02:53 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423156371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3423156371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_random.3269635382 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 34509055 ps |
| CPU time | 2.76 seconds |
| Started | Oct 03 02:02:49 AM UTC 24 |
| Finished | Oct 03 02:02:53 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269635382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3269635382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.568579804 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 15339742640 ps |
| CPU time | 52.33 seconds |
| Started | Oct 03 02:02:48 AM UTC 24 |
| Finished | Oct 03 02:03:41 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568579804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.568579804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.3635146366 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 796872419 ps |
| CPU time | 6.22 seconds |
| Started | Oct 03 02:02:49 AM UTC 24 |
| Finished | Oct 03 02:02:56 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635146366 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3635146366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3702647973 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 110049147 ps |
| CPU time | 3.35 seconds |
| Started | Oct 03 02:02:48 AM UTC 24 |
| Finished | Oct 03 02:02:52 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702647973 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3702647973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.1517438338 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 224887003 ps |
| CPU time | 6.85 seconds |
| Started | Oct 03 02:02:49 AM UTC 24 |
| Finished | Oct 03 02:02:57 AM UTC 24 |
| Peak memory | 217280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517438338 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1517438338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.3165212526 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 514727250 ps |
| CPU time | 4.25 seconds |
| Started | Oct 03 02:02:51 AM UTC 24 |
| Finished | Oct 03 02:02:57 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165212526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3165212526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.21790699 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 567100732 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 02:02:47 AM UTC 24 |
| Finished | Oct 03 02:02:52 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21790699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.21790699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.857934945 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 529561309 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 02:02:52 AM UTC 24 |
| Finished | Oct 03 02:02:56 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857934945 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.857934945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.1323968748 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 176006536 ps |
| CPU time | 7.64 seconds |
| Started | Oct 03 02:02:52 AM UTC 24 |
| Finished | Oct 03 02:03:00 AM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1323968748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg r_stress_all_with_rand_reset.1323968748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.75427322 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 201911452 ps |
| CPU time | 6.31 seconds |
| Started | Oct 03 02:02:50 AM UTC 24 |
| Finished | Oct 03 02:02:57 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75427322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.75427322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.670211389 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 63476630 ps |
| CPU time | 2.48 seconds |
| Started | Oct 03 02:02:51 AM UTC 24 |
| Finished | Oct 03 02:02:55 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670211389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.670211389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.3224703780 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 47284808 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 02:02:58 AM UTC 24 |
| Finished | Oct 03 02:03:00 AM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224703780 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3224703780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.534339669 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 62885355 ps |
| CPU time | 4.75 seconds |
| Started | Oct 03 02:02:54 AM UTC 24 |
| Finished | Oct 03 02:03:00 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534339669 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.534339669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.2261743676 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 129669407 ps |
| CPU time | 7.54 seconds |
| Started | Oct 03 02:02:56 AM UTC 24 |
| Finished | Oct 03 02:03:04 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261743676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2261743676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.37552813 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 513926217 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 02:02:54 AM UTC 24 |
| Finished | Oct 03 02:02:57 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37552813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.37552813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.2558482154 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 332217783 ps |
| CPU time | 4.33 seconds |
| Started | Oct 03 02:02:55 AM UTC 24 |
| Finished | Oct 03 02:03:01 AM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558482154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2558482154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.2798830520 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 68919337 ps |
| CPU time | 2.87 seconds |
| Started | Oct 03 02:02:56 AM UTC 24 |
| Finished | Oct 03 02:02:59 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798830520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2798830520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.608981664 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 101599093 ps |
| CPU time | 4.87 seconds |
| Started | Oct 03 02:02:54 AM UTC 24 |
| Finished | Oct 03 02:03:00 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608981664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.608981664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_random.1801105696 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 7251490446 ps |
| CPU time | 69.36 seconds |
| Started | Oct 03 02:02:53 AM UTC 24 |
| Finished | Oct 03 02:04:04 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801105696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1801105696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.1179744637 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 117511408 ps |
| CPU time | 2.57 seconds |
| Started | Oct 03 02:02:53 AM UTC 24 |
| Finished | Oct 03 02:02:56 AM UTC 24 |
| Peak memory | 217280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179744637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1179744637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.543682316 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 179521949 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 02:02:53 AM UTC 24 |
| Finished | Oct 03 02:02:58 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543682316 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.543682316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.610695111 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 388463468 ps |
| CPU time | 4.33 seconds |
| Started | Oct 03 02:02:53 AM UTC 24 |
| Finished | Oct 03 02:02:58 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610695111 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.610695111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.1320054658 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 103043152 ps |
| CPU time | 5.15 seconds |
| Started | Oct 03 02:02:53 AM UTC 24 |
| Finished | Oct 03 02:02:59 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320054658 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1320054658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.935030550 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 390048371 ps |
| CPU time | 4.7 seconds |
| Started | Oct 03 02:02:57 AM UTC 24 |
| Finished | Oct 03 02:03:02 AM UTC 24 |
| Peak memory | 227648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935030550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.935030550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.409244046 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 113243964 ps |
| CPU time | 4.32 seconds |
| Started | Oct 03 02:02:53 AM UTC 24 |
| Finished | Oct 03 02:02:58 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409244046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.409244046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.1335904413 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2173867093 ps |
| CPU time | 51.4 seconds |
| Started | Oct 03 02:02:57 AM UTC 24 |
| Finished | Oct 03 02:03:50 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335904413 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1335904413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.668335170 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1024335979 ps |
| CPU time | 18.96 seconds |
| Started | Oct 03 02:02:54 AM UTC 24 |
| Finished | Oct 03 02:03:15 AM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668335170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.668335170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.366475809 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 142690187 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 02:02:57 AM UTC 24 |
| Finished | Oct 03 02:03:02 AM UTC 24 |
| Peak memory | 217360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366475809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.366475809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.129612845 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 27420288 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 01:58:45 AM UTC 24 |
| Finished | Oct 03 01:58:47 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129612845 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.129612845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.2725348562 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 31592627 ps |
| CPU time | 3.61 seconds |
| Started | Oct 03 01:58:40 AM UTC 24 |
| Finished | Oct 03 01:58:45 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725348562 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2725348562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.2059505975 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 104051244 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 01:58:40 AM UTC 24 |
| Finished | Oct 03 01:58:45 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059505975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2059505975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.2544798758 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 45741867 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 01:58:43 AM UTC 24 |
| Finished | Oct 03 01:58:47 AM UTC 24 |
| Peak memory | 231412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544798758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2544798758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.300735676 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 293340160 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 01:58:42 AM UTC 24 |
| Finished | Oct 03 01:58:46 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300735676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.300735676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_random.2834086251 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 64248139 ps |
| CPU time | 4 seconds |
| Started | Oct 03 01:58:40 AM UTC 24 |
| Finished | Oct 03 01:58:45 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834086251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2834086251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.2951294910 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 63779251 ps |
| CPU time | 3.41 seconds |
| Started | Oct 03 01:58:38 AM UTC 24 |
| Finished | Oct 03 01:58:42 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951294910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2951294910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.3699097459 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 123209884 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 01:58:39 AM UTC 24 |
| Finished | Oct 03 01:58:44 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699097459 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3699097459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.4013575613 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 579855974 ps |
| CPU time | 9.96 seconds |
| Started | Oct 03 01:58:39 AM UTC 24 |
| Finished | Oct 03 01:58:50 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013575613 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4013575613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.1933019298 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 165691530 ps |
| CPU time | 5.7 seconds |
| Started | Oct 03 01:58:40 AM UTC 24 |
| Finished | Oct 03 01:58:47 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933019298 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1933019298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.3343764249 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 182114505 ps |
| CPU time | 3.29 seconds |
| Started | Oct 03 01:58:43 AM UTC 24 |
| Finished | Oct 03 01:58:47 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343764249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3343764249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.965690706 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 832279901 ps |
| CPU time | 7.26 seconds |
| Started | Oct 03 01:58:37 AM UTC 24 |
| Finished | Oct 03 01:58:45 AM UTC 24 |
| Peak memory | 217196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965690706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.965690706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.1805099218 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1242777344 ps |
| CPU time | 5.37 seconds |
| Started | Oct 03 01:58:43 AM UTC 24 |
| Finished | Oct 03 01:58:49 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805099218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1805099218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.2871589928 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 183102189 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 01:58:44 AM UTC 24 |
| Finished | Oct 03 01:58:48 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871589928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2871589928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.497514316 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 10828662 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:58:52 AM UTC 24 |
| Finished | Oct 03 01:58:54 AM UTC 24 |
| Peak memory | 212888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497514316 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.497514316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.1337837551 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1024927693 ps |
| CPU time | 2.97 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:52 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337837551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1337837551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.2268914951 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 80123565 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:54 AM UTC 24 |
| Peak memory | 217284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268914951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2268914951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_random.4116018966 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 104438398 ps |
| CPU time | 4.47 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:53 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116018966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4116018966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.3507980664 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 488397179 ps |
| CPU time | 8.59 seconds |
| Started | Oct 03 01:58:46 AM UTC 24 |
| Finished | Oct 03 01:58:56 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507980664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3507980664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.3915972147 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 154028013 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 01:58:47 AM UTC 24 |
| Finished | Oct 03 01:58:50 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915972147 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3915972147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.4281512855 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 68149040 ps |
| CPU time | 2.73 seconds |
| Started | Oct 03 01:58:47 AM UTC 24 |
| Finished | Oct 03 01:58:50 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281512855 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4281512855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.581855043 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 113048245 ps |
| CPU time | 2.93 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:52 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581855043 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.581855043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.1046954099 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2335408792 ps |
| CPU time | 13.48 seconds |
| Started | Oct 03 01:58:50 AM UTC 24 |
| Finished | Oct 03 01:59:05 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046954099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1046954099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.979042197 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 88235243 ps |
| CPU time | 2.86 seconds |
| Started | Oct 03 01:58:46 AM UTC 24 |
| Finished | Oct 03 01:58:50 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979042197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.979042197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.3620060986 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 145150276 ps |
| CPU time | 5.21 seconds |
| Started | Oct 03 01:58:48 AM UTC 24 |
| Finished | Oct 03 01:58:54 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620060986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3620060986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3431573279 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 42097852 ps |
| CPU time | 2.76 seconds |
| Started | Oct 03 01:58:51 AM UTC 24 |
| Finished | Oct 03 01:58:54 AM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431573279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3431573279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.1873194925 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 11025777 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 01:58:57 AM UTC 24 |
| Finished | Oct 03 01:58:59 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873194925 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1873194925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.2989384248 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 988160624 ps |
| CPU time | 52.19 seconds |
| Started | Oct 03 01:58:53 AM UTC 24 |
| Finished | Oct 03 01:59:47 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989384248 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2989384248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.2556044893 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 7292398749 ps |
| CPU time | 28.01 seconds |
| Started | Oct 03 01:58:55 AM UTC 24 |
| Finished | Oct 03 01:59:24 AM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556044893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2556044893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.2546380395 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 142160550 ps |
| CPU time | 4.27 seconds |
| Started | Oct 03 01:58:53 AM UTC 24 |
| Finished | Oct 03 01:58:58 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546380395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2546380395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.3856917096 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 121258737 ps |
| CPU time | 5.47 seconds |
| Started | Oct 03 01:58:54 AM UTC 24 |
| Finished | Oct 03 01:59:01 AM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856917096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3856917096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.2578338067 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 252977226 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 01:58:55 AM UTC 24 |
| Finished | Oct 03 01:58:59 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578338067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2578338067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.343861991 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 350757886 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 01:58:54 AM UTC 24 |
| Finished | Oct 03 01:59:00 AM UTC 24 |
| Peak memory | 223500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343861991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.343861991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_random.396392915 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 236519084 ps |
| CPU time | 5.25 seconds |
| Started | Oct 03 01:58:53 AM UTC 24 |
| Finished | Oct 03 01:58:59 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396392915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.396392915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.2597385432 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 57801922 ps |
| CPU time | 2.78 seconds |
| Started | Oct 03 01:58:52 AM UTC 24 |
| Finished | Oct 03 01:58:56 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597385432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2597385432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.1963913664 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 57655249 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 01:58:53 AM UTC 24 |
| Finished | Oct 03 01:58:57 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963913664 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1963913664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.3148916643 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 147699673 ps |
| CPU time | 2.87 seconds |
| Started | Oct 03 01:58:52 AM UTC 24 |
| Finished | Oct 03 01:58:56 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148916643 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3148916643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.2521391405 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 133038836 ps |
| CPU time | 3 seconds |
| Started | Oct 03 01:58:53 AM UTC 24 |
| Finished | Oct 03 01:58:57 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521391405 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2521391405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.4271148028 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 367735377 ps |
| CPU time | 5.17 seconds |
| Started | Oct 03 01:58:56 AM UTC 24 |
| Finished | Oct 03 01:59:02 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271148028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4271148028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.1018243518 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2027764887 ps |
| CPU time | 4.71 seconds |
| Started | Oct 03 01:58:52 AM UTC 24 |
| Finished | Oct 03 01:58:58 AM UTC 24 |
| Peak memory | 217536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018243518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1018243518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.80153512 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 750453691 ps |
| CPU time | 10.33 seconds |
| Started | Oct 03 01:58:56 AM UTC 24 |
| Finished | Oct 03 01:59:07 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=80153512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_s tress_all_with_rand_reset.80153512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.3805465541 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 209634513 ps |
| CPU time | 4.66 seconds |
| Started | Oct 03 01:58:54 AM UTC 24 |
| Finished | Oct 03 01:59:00 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805465541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3805465541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.1321400803 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 34047100 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:58:56 AM UTC 24 |
| Finished | Oct 03 01:58:59 AM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321400803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1321400803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3560946411 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 29683323 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 01:59:02 AM UTC 24 |
| Finished | Oct 03 01:59:04 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560946411 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3560946411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.1980737263 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 100256759 ps |
| CPU time | 4.31 seconds |
| Started | Oct 03 01:58:59 AM UTC 24 |
| Finished | Oct 03 01:59:04 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980737263 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1980737263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.3533240627 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 196245225 ps |
| CPU time | 8.77 seconds |
| Started | Oct 03 01:59:00 AM UTC 24 |
| Finished | Oct 03 01:59:10 AM UTC 24 |
| Peak memory | 220052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533240627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3533240627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.1503741170 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 495712677 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 01:58:59 AM UTC 24 |
| Finished | Oct 03 01:59:03 AM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503741170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1503741170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.2932972324 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 119037508 ps |
| CPU time | 7.09 seconds |
| Started | Oct 03 01:59:00 AM UTC 24 |
| Finished | Oct 03 01:59:08 AM UTC 24 |
| Peak memory | 225808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932972324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2932972324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.4228374591 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 261042111 ps |
| CPU time | 3.32 seconds |
| Started | Oct 03 01:59:00 AM UTC 24 |
| Finished | Oct 03 01:59:04 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228374591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4228374591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.388092461 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 144233049 ps |
| CPU time | 3.12 seconds |
| Started | Oct 03 01:58:59 AM UTC 24 |
| Finished | Oct 03 01:59:03 AM UTC 24 |
| Peak memory | 223404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388092461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.388092461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_random.3855800787 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 94397656 ps |
| CPU time | 6.43 seconds |
| Started | Oct 03 01:58:58 AM UTC 24 |
| Finished | Oct 03 01:59:06 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855800787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3855800787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.4032069152 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 96356688 ps |
| CPU time | 4.52 seconds |
| Started | Oct 03 01:58:57 AM UTC 24 |
| Finished | Oct 03 01:59:03 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032069152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4032069152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.3574342650 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1164199896 ps |
| CPU time | 24.82 seconds |
| Started | Oct 03 01:58:57 AM UTC 24 |
| Finished | Oct 03 01:59:23 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574342650 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3574342650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.4157842387 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 234530609 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 01:58:57 AM UTC 24 |
| Finished | Oct 03 01:59:02 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157842387 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4157842387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.2352072309 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 248591482 ps |
| CPU time | 5.05 seconds |
| Started | Oct 03 01:58:57 AM UTC 24 |
| Finished | Oct 03 01:59:03 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352072309 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2352072309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.2539998973 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 237683756 ps |
| CPU time | 4.35 seconds |
| Started | Oct 03 01:59:01 AM UTC 24 |
| Finished | Oct 03 01:59:06 AM UTC 24 |
| Peak memory | 217268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539998973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2539998973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.920461010 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 94195302 ps |
| CPU time | 4.07 seconds |
| Started | Oct 03 01:58:57 AM UTC 24 |
| Finished | Oct 03 01:59:02 AM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920461010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.920461010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.1584708578 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 116214291 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 01:59:00 AM UTC 24 |
| Finished | Oct 03 01:59:05 AM UTC 24 |
| Peak memory | 217256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584708578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1584708578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.1784425430 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 63529007 ps |
| CPU time | 2.92 seconds |
| Started | Oct 03 01:59:01 AM UTC 24 |
| Finished | Oct 03 01:59:05 AM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784425430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1784425430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2448073218 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 8573273 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 01:59:08 AM UTC 24 |
| Finished | Oct 03 01:59:10 AM UTC 24 |
| Peak memory | 212912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448073218 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2448073218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.2280177547 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 869853720 ps |
| CPU time | 9.23 seconds |
| Started | Oct 03 01:59:06 AM UTC 24 |
| Finished | Oct 03 01:59:17 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280177547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2280177547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.1751512224 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 66939915 ps |
| CPU time | 3.87 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 01:59:09 AM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751512224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1751512224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.1706398503 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 969870030 ps |
| CPU time | 3.85 seconds |
| Started | Oct 03 01:59:05 AM UTC 24 |
| Finished | Oct 03 01:59:10 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706398503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1706398503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.4100857085 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 42358273 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 01:59:05 AM UTC 24 |
| Finished | Oct 03 01:59:09 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100857085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4100857085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.80405064 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 84561829 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 01:59:05 AM UTC 24 |
| Finished | Oct 03 01:59:11 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80405064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.80405064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_random.2349955528 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 6992104119 ps |
| CPU time | 89.53 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 02:00:35 AM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349955528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2349955528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.3072161837 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2933814614 ps |
| CPU time | 20.21 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 01:59:25 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072161837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3072161837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.1348413918 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 195758327 ps |
| CPU time | 7.77 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 01:59:13 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348413918 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1348413918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.2866282269 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 140437484 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 01:59:07 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866282269 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2866282269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.3348292200 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 199390514 ps |
| CPU time | 5.68 seconds |
| Started | Oct 03 01:59:04 AM UTC 24 |
| Finished | Oct 03 01:59:10 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348292200 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3348292200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.557506902 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 114030933 ps |
| CPU time | 4.55 seconds |
| Started | Oct 03 01:59:06 AM UTC 24 |
| Finished | Oct 03 01:59:12 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557506902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.557506902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.2450770357 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 335720359 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 01:59:02 AM UTC 24 |
| Finished | Oct 03 01:59:08 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450770357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2450770357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.1212775349 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 957692597 ps |
| CPU time | 5.99 seconds |
| Started | Oct 03 01:59:05 AM UTC 24 |
| Finished | Oct 03 01:59:12 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212775349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1212775349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.618226351 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 38635938 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:59:06 AM UTC 24 |
| Finished | Oct 03 01:59:09 AM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618226351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.618226351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
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