Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2812307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

619097

1

T1

180

T2

167

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3014306	1			T1	709		T2	350		T3	1
values[0x0]	207361	1			T1	48		T2	66		T3	7
values[0x1]	209737	1			T1	37		T2	47		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1933367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1498037

1

T1

366

T2

223

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14490	1			T1	2		T4	2		T5	3
valid_sources[0x01]	16045	1			T1	2		T4	2		T5	6
valid_sources[0x02]	11366	1			T1	7		T4	8		T5	1
valid_sources[0x03]	11297	1			T1	4		T4	5		T5	2
valid_sources[0x04]	13094	1			T1	6		T4	7		T5	2
valid_sources[0x05]	19426	1			T1	1		T4	4		T5	5
valid_sources[0x06]	12437	1			T4	6		T5	2		T15	4
valid_sources[0x07]	11430	1			T1	8		T4	10		T15	1
valid_sources[0x08]	16068	1			T1	8		T4	3		T15	3
valid_sources[0x09]	13704	1			T1	4		T4	2		T5	3
valid_sources[0x0a]	12375	1			T1	4		T4	9		T5	2
valid_sources[0x0b]	12724	1			T1	2		T4	9		T5	2
valid_sources[0x0c]	11456	1			T1	3		T4	2		T5	1
valid_sources[0x0d]	12223	1			T1	5		T5	2		T15	7
valid_sources[0x0e]	12237	1			T1	3		T4	1		T5	2
valid_sources[0x0f]	13813	1			T1	5		T4	5		T5	5
valid_sources[0x10]	12085	1			T1	2		T4	3		T5	2
valid_sources[0x11]	19231	1			T1	5		T4	3		T5	1
valid_sources[0x12]	15721	1			T1	1		T4	4		T5	3
valid_sources[0x13]	11972	1			T1	2		T5	1		T15	4
valid_sources[0x14]	12060	1			T1	2		T4	3		T5	2
valid_sources[0x15]	12018	1			T1	5		T4	1		T5	1
valid_sources[0x16]	11770	1			T1	7		T4	6		T5	4
valid_sources[0x17]	13346	1			T1	6		T4	2		T5	3
valid_sources[0x18]	11706	1			T1	5		T4	5		T5	1
valid_sources[0x19]	12265	1			T4	4		T5	6		T15	3
valid_sources[0x1a]	12521	1			T4	4		T5	3		T15	6
valid_sources[0x1b]	12310	1			T1	3		T4	8		T5	3
valid_sources[0x1c]	11618	1			T1	5		T5	1		T15	2
valid_sources[0x1d]	11126	1			T1	5		T4	6		T5	1
valid_sources[0x1e]	11380	1			T1	3		T4	4		T5	1
valid_sources[0x1f]	11615	1			T1	1		T4	6		T5	3
valid_sources[0x20]	14256	1			T1	5		T4	4		T5	3
valid_sources[0x21]	11876	1			T4	3		T5	1		T15	4
valid_sources[0x22]	12240	1			T1	4		T3	1		T4	1
valid_sources[0x23]	12761	1			T1	4		T4	3		T5	4
valid_sources[0x24]	12384	1			T1	2		T3	3		T4	5
valid_sources[0x25]	12356	1			T1	2		T4	4		T15	1
valid_sources[0x26]	11273	1			T1	2		T4	5		T15	5
valid_sources[0x27]	12389	1			T4	4		T15	7		T6	3
valid_sources[0x28]	11300	1			T1	3		T4	2		T5	1
valid_sources[0x29]	11752	1			T1	3		T4	6		T5	4
valid_sources[0x2a]	13022	1			T1	5		T4	3		T5	2
valid_sources[0x2b]	11456	1			T1	2		T5	1		T15	4
valid_sources[0x2c]	11922	1			T1	8		T4	1		T5	3
valid_sources[0x2d]	13998	1			T1	4		T4	2		T5	6
valid_sources[0x2e]	11457	1			T4	1		T5	2		T15	3
valid_sources[0x2f]	13280	1			T1	2		T4	5		T15	2
valid_sources[0x30]	14248	1			T1	5		T4	12		T5	2
valid_sources[0x31]	11097	1			T1	4		T4	5		T5	3
valid_sources[0x32]	11553	1			T1	3		T4	2		T5	4
valid_sources[0x33]	10931	1			T1	1		T4	7		T5	2
valid_sources[0x34]	12210	1			T1	7		T4	1		T5	2
valid_sources[0x35]	11377	1			T1	8		T4	3		T5	1
valid_sources[0x36]	13125	1			T1	3		T4	2		T5	8
valid_sources[0x37]	14666	1			T1	2		T4	2		T5	5
valid_sources[0x38]	17650	1			T1	1		T4	5		T5	2
valid_sources[0x39]	11010	1			T4	2		T5	3		T15	2
valid_sources[0x3a]	13495	1			T1	5		T4	2		T5	3
valid_sources[0x3b]	11804	1			T1	1		T4	4		T5	1
valid_sources[0x3c]	15456	1			T1	3		T4	1		T5	4
valid_sources[0x3d]	11183	1			T1	2		T4	8		T5	1
valid_sources[0x3e]	17754	1			T1	4		T4	9		T5	1
valid_sources[0x3f]	11883	1			T1	6		T4	2		T15	3
valid_sources[0x40]	12860	1			T1	4		T4	1		T5	1
valid_sources[0x41]	12183	1			T1	4		T4	4		T5	3
valid_sources[0x42]	12718	1			T1	3		T4	4		T5	2
valid_sources[0x43]	37867	1			T1	6		T4	2		T15	4
valid_sources[0x44]	11664	1			T1	4		T4	4		T5	4
valid_sources[0x45]	33755	1			T1	6		T4	4		T5	1
valid_sources[0x46]	12095	1			T1	4		T4	3		T5	1
valid_sources[0x47]	12360	1			T1	6		T4	4		T5	2
valid_sources[0x48]	12269	1			T3	1		T4	3		T5	3
valid_sources[0x49]	14162	1			T1	1		T4	8		T5	2
valid_sources[0x4a]	11332	1			T1	2		T4	3		T5	2
valid_sources[0x4b]	13528	1			T1	2		T4	5		T15	3
valid_sources[0x4c]	40539	1			T1	7		T4	1		T15	3
valid_sources[0x4d]	12497	1			T1	2		T3	1		T4	3
valid_sources[0x4e]	11502	1			T1	4		T4	2		T5	5
valid_sources[0x4f]	11761	1			T1	4		T4	2		T5	2
valid_sources[0x50]	14012	1			T1	4		T4	3		T5	3
valid_sources[0x51]	15003	1			T1	1		T4	2		T5	6
valid_sources[0x52]	12279	1			T1	5		T5	4		T15	1
valid_sources[0x53]	20003	1			T1	4		T4	5		T5	2
valid_sources[0x54]	12558	1			T1	2		T4	4		T5	4
valid_sources[0x55]	11539	1			T1	7		T4	3		T5	1
valid_sources[0x56]	12126	1			T1	4		T5	1		T15	2
valid_sources[0x57]	11348	1			T1	4		T4	5		T15	5
valid_sources[0x58]	11457	1			T1	6		T4	6		T15	2
valid_sources[0x59]	11076	1			T1	1		T4	6		T5	1
valid_sources[0x5a]	14026	1			T1	3		T4	5		T5	1
valid_sources[0x5b]	16941	1			T1	4		T4	2		T5	1
valid_sources[0x5c]	11450	1			T1	1		T4	13		T15	8
valid_sources[0x5d]	17857	1			T1	4		T4	3		T5	1
valid_sources[0x5e]	13687	1			T1	4		T4	14		T5	2
valid_sources[0x5f]	13250	1			T1	1		T4	5		T5	7
valid_sources[0x60]	11006	1			T1	3		T4	3		T5	1
valid_sources[0x61]	12444	1			T4	8		T5	2		T15	5
valid_sources[0x62]	12344	1			T1	4		T4	11		T5	1
valid_sources[0x63]	11704	1			T1	5		T4	6		T5	2
valid_sources[0x64]	14877	1			T1	1		T4	8		T5	1
valid_sources[0x65]	15217	1			T1	6		T4	2		T15	1
valid_sources[0x66]	11919	1			T1	4		T4	16		T5	4
valid_sources[0x67]	16983	1			T1	6		T4	13		T5	6
valid_sources[0x68]	11182	1			T1	2		T4	3		T5	4
valid_sources[0x69]	12126	1			T1	2		T3	4		T4	4
valid_sources[0x6a]	12276	1			T4	4		T5	1		T15	3
valid_sources[0x6b]	11438	1			T1	1		T4	4		T5	3
valid_sources[0x6c]	11626	1			T1	1		T4	1		T5	1
valid_sources[0x6d]	13354	1			T1	2		T4	4		T15	4
valid_sources[0x6e]	11696	1			T1	3		T4	3		T5	2
valid_sources[0x6f]	12155	1			T1	3		T4	19		T5	1
valid_sources[0x70]	11589	1			T4	6		T5	1		T15	2
valid_sources[0x71]	12103	1			T1	4		T4	3		T5	2
valid_sources[0x72]	11163	1			T1	1		T4	9		T15	4
valid_sources[0x73]	11562	1			T1	1		T4	1		T15	2
valid_sources[0x74]	11555	1			T1	3		T4	4		T5	1
valid_sources[0x75]	13562	1			T1	2		T4	6		T5	2
valid_sources[0x76]	12056	1			T4	1		T5	2		T15	3
valid_sources[0x77]	13874	1			T1	2		T4	6		T5	9
valid_sources[0x78]	13735	1			T1	1		T5	2		T15	2
valid_sources[0x79]	11981	1			T1	4		T4	7		T15	3
valid_sources[0x7a]	13585	1			T1	4		T4	5		T5	1
valid_sources[0x7b]	11754	1			T1	3		T4	3		T15	3
valid_sources[0x7c]	12531	1			T1	5		T4	9		T5	5
valid_sources[0x7d]	11403	1			T1	1		T4	2		T5	2
valid_sources[0x7e]	11240	1			T1	1		T4	1		T5	4
valid_sources[0x7f]	48439	1			T1	2		T4	1		T15	6
valid_sources[0x80]	12478	1			T1	1		T4	2		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333704

1

T1

150

T2

131

T3

1

values[0x0]

all_enables

biggest_size

150523

1

T1

20

T2

26

T3

2

values[0x1]

all_enables

biggest_size

134870

1

T1

10

T2

10

T3

3