| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.74 | 99.03 | 97.75 | 98.53 | 100.00 | 99.01 | 98.63 | 91.19 |
| T1005 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3562010473 | Oct 12 02:21:30 AM UTC 24 | Oct 12 02:21:34 AM UTC 24 | 54695830 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.341442333 | Oct 12 02:21:32 AM UTC 24 | Oct 12 02:21:34 AM UTC 24 | 45397552 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4130959663 | Oct 12 02:21:30 AM UTC 24 | Oct 12 02:21:34 AM UTC 24 | 153974243 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4183202706 | Oct 12 02:21:27 AM UTC 24 | Oct 12 02:21:35 AM UTC 24 | 468879505 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.2389954937 | Oct 12 02:21:28 AM UTC 24 | Oct 12 02:21:35 AM UTC 24 | 112107684 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1001235711 | Oct 12 02:21:33 AM UTC 24 | Oct 12 02:21:35 AM UTC 24 | 46602358 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.144954108 | Oct 12 02:21:31 AM UTC 24 | Oct 12 02:21:35 AM UTC 24 | 268390899 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2800464051 | Oct 12 02:21:33 AM UTC 24 | Oct 12 02:21:36 AM UTC 24 | 169425675 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.3117987576 | Oct 12 02:21:32 AM UTC 24 | Oct 12 02:21:36 AM UTC 24 | 76267161 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3864623810 | Oct 12 02:21:33 AM UTC 24 | Oct 12 02:21:36 AM UTC 24 | 105129198 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.252452845 | Oct 12 02:21:34 AM UTC 24 | Oct 12 02:21:37 AM UTC 24 | 198949598 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.3015008508 | Oct 12 02:21:35 AM UTC 24 | Oct 12 02:21:37 AM UTC 24 | 69478963 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1696165908 | Oct 12 02:21:36 AM UTC 24 | Oct 12 02:21:39 AM UTC 24 | 30743583 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.194556901 | Oct 12 02:21:32 AM UTC 24 | Oct 12 02:21:40 AM UTC 24 | 136421240 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3739960676 | Oct 12 02:21:37 AM UTC 24 | Oct 12 02:21:40 AM UTC 24 | 174764721 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2155634147 | Oct 12 02:21:36 AM UTC 24 | Oct 12 02:21:41 AM UTC 24 | 168471340 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3524524317 | Oct 12 02:21:39 AM UTC 24 | Oct 12 02:21:41 AM UTC 24 | 20873983 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.387558101 | Oct 12 02:21:35 AM UTC 24 | Oct 12 02:21:41 AM UTC 24 | 52061399 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.3842686502 | Oct 12 02:21:40 AM UTC 24 | Oct 12 02:21:42 AM UTC 24 | 85421805 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2677596882 | Oct 12 02:21:37 AM UTC 24 | Oct 12 02:21:43 AM UTC 24 | 133215330 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.326871388 | Oct 12 02:21:35 AM UTC 24 | Oct 12 02:21:43 AM UTC 24 | 853354210 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.26847398 | Oct 12 02:21:38 AM UTC 24 | Oct 12 02:21:44 AM UTC 24 | 861527689 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.367817664 | Oct 12 02:21:41 AM UTC 24 | Oct 12 02:21:44 AM UTC 24 | 64992303 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.11812622 | Oct 12 02:21:37 AM UTC 24 | Oct 12 02:21:44 AM UTC 24 | 1121381659 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2794812217 | Oct 12 02:21:43 AM UTC 24 | Oct 12 02:21:45 AM UTC 24 | 16469267 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1437342294 | Oct 12 02:21:38 AM UTC 24 | Oct 12 02:21:48 AM UTC 24 | 257634211 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3983621412 | Oct 12 02:21:31 AM UTC 24 | Oct 12 02:21:47 AM UTC 24 | 1821153780 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1405691468 | Oct 12 02:21:46 AM UTC 24 | Oct 12 02:21:48 AM UTC 24 | 15532260 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1873737951 | Oct 12 02:21:42 AM UTC 24 | Oct 12 02:21:48 AM UTC 24 | 179359415 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1376582698 | Oct 12 02:21:45 AM UTC 24 | Oct 12 02:21:48 AM UTC 24 | 49451014 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3939587764 | Oct 12 02:21:45 AM UTC 24 | Oct 12 02:21:49 AM UTC 24 | 85330275 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2328039292 | Oct 12 02:21:47 AM UTC 24 | Oct 12 02:21:50 AM UTC 24 | 19719360 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2709897421 | Oct 12 02:21:47 AM UTC 24 | Oct 12 02:21:50 AM UTC 24 | 194107682 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.756786643 | Oct 12 02:21:45 AM UTC 24 | Oct 12 02:21:50 AM UTC 24 | 559324216 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.150027238 | Oct 12 02:21:45 AM UTC 24 | Oct 12 02:21:50 AM UTC 24 | 340349429 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1315655516 | Oct 12 02:21:45 AM UTC 24 | Oct 12 02:21:51 AM UTC 24 | 282035785 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2276296710 | Oct 12 02:21:48 AM UTC 24 | Oct 12 02:21:51 AM UTC 24 | 27977340 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3586082655 | Oct 12 02:21:48 AM UTC 24 | Oct 12 02:21:51 AM UTC 24 | 127993115 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.4222384381 | Oct 12 02:21:49 AM UTC 24 | Oct 12 02:21:52 AM UTC 24 | 48129264 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3140701853 | Oct 12 02:21:49 AM UTC 24 | Oct 12 02:21:52 AM UTC 24 | 26937604 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1585747986 | Oct 12 02:21:51 AM UTC 24 | Oct 12 02:21:53 AM UTC 24 | 10202130 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.4243228082 | Oct 12 02:21:51 AM UTC 24 | Oct 12 02:21:53 AM UTC 24 | 24437773 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3617237980 | Oct 12 02:21:51 AM UTC 24 | Oct 12 02:21:53 AM UTC 24 | 21846415 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3810093224 | Oct 12 02:21:42 AM UTC 24 | Oct 12 02:21:53 AM UTC 24 | 144392449 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1044088207 | Oct 12 02:21:51 AM UTC 24 | Oct 12 02:21:53 AM UTC 24 | 109011725 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3211999868 | Oct 12 02:21:50 AM UTC 24 | Oct 12 02:21:54 AM UTC 24 | 48700931 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2150921047 | Oct 12 02:21:52 AM UTC 24 | Oct 12 02:21:54 AM UTC 24 | 65251132 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1282625391 | Oct 12 02:21:52 AM UTC 24 | Oct 12 02:21:54 AM UTC 24 | 64024717 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.1925638344 | Oct 12 02:21:49 AM UTC 24 | Oct 12 02:21:54 AM UTC 24 | 46753114 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.3849647935 | Oct 12 02:21:52 AM UTC 24 | Oct 12 02:21:54 AM UTC 24 | 49219975 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.4064134332 | Oct 12 02:21:46 AM UTC 24 | Oct 12 02:21:55 AM UTC 24 | 217307135 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4280705594 | Oct 12 02:21:53 AM UTC 24 | Oct 12 02:21:55 AM UTC 24 | 38111125 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3218893763 | Oct 12 02:21:53 AM UTC 24 | Oct 12 02:21:55 AM UTC 24 | 25996648 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.309593433 | Oct 12 02:21:53 AM UTC 24 | Oct 12 02:21:55 AM UTC 24 | 16484492 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3418522249 | Oct 12 02:21:49 AM UTC 24 | Oct 12 02:21:56 AM UTC 24 | 381072841 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.4084492981 | Oct 12 02:21:54 AM UTC 24 | Oct 12 02:21:56 AM UTC 24 | 14805133 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.29965248 | Oct 12 02:21:55 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 10016315 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.747820127 | Oct 12 02:21:55 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 18851361 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.2288158038 | Oct 12 02:21:54 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 15073973 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.2645118889 | Oct 12 02:21:55 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 21719596 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1302545555 | Oct 12 02:21:55 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 10848248 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1625833799 | Oct 12 02:21:55 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 18364339 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.4240944747 | Oct 12 02:21:49 AM UTC 24 | Oct 12 02:21:57 AM UTC 24 | 142051585 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.82392775 | Oct 12 02:21:56 AM UTC 24 | Oct 12 02:21:58 AM UTC 24 | 7743945 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3711423585 | Oct 12 02:21:56 AM UTC 24 | Oct 12 02:21:58 AM UTC 24 | 23517116 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2942368331 | Oct 12 02:21:56 AM UTC 24 | Oct 12 02:21:58 AM UTC 24 | 13920142 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.3718099540 | Oct 12 02:21:56 AM UTC 24 | Oct 12 02:21:58 AM UTC 24 | 9427582 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2810926491 | Oct 12 02:21:56 AM UTC 24 | Oct 12 02:21:58 AM UTC 24 | 11967943 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2881257200 | Oct 12 02:21:56 AM UTC 24 | Oct 12 02:21:58 AM UTC 24 | 30203894 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1953603481 | Oct 12 02:21:58 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 33987101 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.816571978 | Oct 12 02:21:57 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 13241145 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4173108909 | Oct 12 02:21:57 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 37210051 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3430809058 | Oct 12 02:21:57 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 58180411 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.583300615 | Oct 12 02:21:57 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 11439341 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.3726406292 | Oct 12 02:21:57 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 64907737 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1769219704 | Oct 12 02:21:57 AM UTC 24 | Oct 12 02:22:00 AM UTC 24 | 13689938 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3860011750 | Oct 12 02:21:59 AM UTC 24 | Oct 12 02:22:01 AM UTC 24 | 40888003 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.183001497 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 133095118 ps |
| CPU time | 4.03 seconds |
| Started | Oct 12 02:33:22 AM UTC 24 |
| Finished | Oct 12 02:33:27 AM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183001497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.183001497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.493192823 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5603065374 ps |
| CPU time | 17.36 seconds |
| Started | Oct 12 02:33:55 AM UTC 24 |
| Finished | Oct 12 02:34:14 AM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=493192823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_ stress_all_with_rand_reset.493192823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3906720295 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4686061351 ps |
| CPU time | 28.77 seconds |
| Started | Oct 12 02:33:27 AM UTC 24 |
| Finished | Oct 12 02:33:57 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906720295 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3906720295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.2201941049 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 588698420 ps |
| CPU time | 11.38 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:36 AM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201941049 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2201941049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3121025260 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 155308068 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 02:33:22 AM UTC 24 |
| Finished | Oct 12 02:33:26 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121025260 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3121025260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.884566165 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 455297124 ps |
| CPU time | 15.31 seconds |
| Started | Oct 12 02:33:44 AM UTC 24 |
| Finished | Oct 12 02:34:01 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884566165 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.884566165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.706479945 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 123655684 ps |
| CPU time | 5.99 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:50 AM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706479945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.706479945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.757872224 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 112696515 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:27 AM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757872224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.757872224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.1796287914 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 138503658 ps |
| CPU time | 7.45 seconds |
| Started | Oct 12 02:33:48 AM UTC 24 |
| Finished | Oct 12 02:33:57 AM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796287914 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1796287914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.3522297372 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 543635202 ps |
| CPU time | 23.59 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:45 AM UTC 24 |
| Peak memory | 232116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3522297372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg r_stress_all_with_rand_reset.3522297372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.1524540766 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 48969982 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:35 AM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524540766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1524540766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3520165650 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 409773375 ps |
| CPU time | 17.87 seconds |
| Started | Oct 12 02:19:55 AM UTC 24 |
| Finished | Oct 12 02:20:14 AM UTC 24 |
| Peak memory | 232400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520165650 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.3520165650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.2542219382 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 8077821503 ps |
| CPU time | 23 seconds |
| Started | Oct 12 02:33:38 AM UTC 24 |
| Finished | Oct 12 02:34:02 AM UTC 24 |
| Peak memory | 230556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542219382 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2542219382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.3894662894 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 221665149 ps |
| CPU time | 10.31 seconds |
| Started | Oct 12 02:33:35 AM UTC 24 |
| Finished | Oct 12 02:33:47 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894662894 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3894662894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.3116547581 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 254467790 ps |
| CPU time | 12.92 seconds |
| Started | Oct 12 02:33:44 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 230288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3116547581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr _stress_all_with_rand_reset.3116547581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.539413668 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 5211545317 ps |
| CPU time | 61.35 seconds |
| Started | Oct 12 02:33:42 AM UTC 24 |
| Finished | Oct 12 02:34:45 AM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539413668 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.539413668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.4244427251 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 53236657 ps |
| CPU time | 3.12 seconds |
| Started | Oct 12 02:33:48 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 223684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244427251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4244427251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.2793529188 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 119678131 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 02:33:25 AM UTC 24 |
| Finished | Oct 12 02:33:29 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793529188 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2793529188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1822505816 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1186628444 ps |
| CPU time | 50.84 seconds |
| Started | Oct 12 02:35:07 AM UTC 24 |
| Finished | Oct 12 02:36:00 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822505816 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1822505816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.2467767229 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4306868534 ps |
| CPU time | 23.56 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:29 AM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2467767229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr _stress_all_with_rand_reset.2467767229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.1103196721 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 267791419 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 02:34:08 AM UTC 24 |
| Finished | Oct 12 02:34:13 AM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103196721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1103196721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.738433500 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 159361416 ps |
| CPU time | 4.97 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:29 AM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738433500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.738433500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.2853419314 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 489677831 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 02:33:36 AM UTC 24 |
| Finished | Oct 12 02:33:43 AM UTC 24 |
| Peak memory | 219712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853419314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2853419314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.3138363326 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 159545741 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:48 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138363326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3138363326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.4055007355 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 342811697 ps |
| CPU time | 15.06 seconds |
| Started | Oct 12 02:34:07 AM UTC 24 |
| Finished | Oct 12 02:34:23 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055007355 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4055007355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3633148139 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5394570021 ps |
| CPU time | 11.43 seconds |
| Started | Oct 12 02:20:30 AM UTC 24 |
| Finished | Oct 12 02:20:43 AM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633148139 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.3633148139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.4131066227 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 240132829 ps |
| CPU time | 13.05 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:29 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131066227 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.4131066227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.2657243266 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 374435819 ps |
| CPU time | 10.21 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:33 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657243266 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2657243266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.3148707190 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 56486438 ps |
| CPU time | 3.5 seconds |
| Started | Oct 12 02:33:27 AM UTC 24 |
| Finished | Oct 12 02:33:32 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148707190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3148707190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.3462489836 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 94557716 ps |
| CPU time | 3.39 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:35:40 AM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462489836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3462489836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.4150716714 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 11403798597 ps |
| CPU time | 71.24 seconds |
| Started | Oct 12 02:33:55 AM UTC 24 |
| Finished | Oct 12 02:35:09 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150716714 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4150716714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.3573722008 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 222968902 ps |
| CPU time | 8.43 seconds |
| Started | Oct 12 02:33:50 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3573722008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr _stress_all_with_rand_reset.3573722008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.553251723 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 758217340 ps |
| CPU time | 7.53 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:41 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553251723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.553251723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.2071031147 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3047384282 ps |
| CPU time | 65.48 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:35:40 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071031147 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2071031147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.4141422880 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 228490755 ps |
| CPU time | 8.06 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:32 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141422880 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4141422880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.3836702532 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 93344206 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:07 AM UTC 24 |
| Peak memory | 223300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836702532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3836702532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.1359183928 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 183750234 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 02:34:08 AM UTC 24 |
| Finished | Oct 12 02:34:12 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359183928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1359183928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.3818665812 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 70506827 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 02:34:08 AM UTC 24 |
| Finished | Oct 12 02:34:11 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818665812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3818665812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.1970993365 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 102637072 ps |
| CPU time | 4.89 seconds |
| Started | Oct 12 02:34:31 AM UTC 24 |
| Finished | Oct 12 02:34:37 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970993365 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1970993365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.1916580 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 242916727 ps |
| CPU time | 7.29 seconds |
| Started | Oct 12 02:35:02 AM UTC 24 |
| Finished | Oct 12 02:35:13 AM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1916580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.2072090795 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 43427692 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:33:45 AM UTC 24 |
| Finished | Oct 12 02:33:47 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072090795 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2072090795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.2707911507 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 57898632930 ps |
| CPU time | 532.61 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:44:12 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707911507 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2707911507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.3337023555 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2056309199 ps |
| CPU time | 21.53 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:43 AM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337023555 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3337023555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.805351470 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 299644571 ps |
| CPU time | 7.09 seconds |
| Started | Oct 12 02:35:57 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805351470 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.805351470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.275381886 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 139790176 ps |
| CPU time | 4.94 seconds |
| Started | Oct 12 02:21:08 AM UTC 24 |
| Finished | Oct 12 02:21:14 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275381886 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.275381886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.874050763 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 752298484 ps |
| CPU time | 12.23 seconds |
| Started | Oct 12 02:33:31 AM UTC 24 |
| Finished | Oct 12 02:33:45 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874050763 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.874050763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.2644558515 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5641803356 ps |
| CPU time | 39.81 seconds |
| Started | Oct 12 02:36:13 AM UTC 24 |
| Finished | Oct 12 02:37:18 AM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644558515 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2644558515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.1767874765 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 68191789 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:25 AM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767874765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1767874765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.389034875 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 695628621 ps |
| CPU time | 29.85 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:36 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389034875 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.389034875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.1429733897 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 298626293 ps |
| CPU time | 4.68 seconds |
| Started | Oct 12 02:33:35 AM UTC 24 |
| Finished | Oct 12 02:33:41 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429733897 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1429733897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.3922956093 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 189449943 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 02:21:17 AM UTC 24 |
| Finished | Oct 12 02:21:21 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922956093 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.3922956093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.332925797 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 302752084 ps |
| CPU time | 5.05 seconds |
| Started | Oct 12 02:34:26 AM UTC 24 |
| Finished | Oct 12 02:34:33 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332925797 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.332925797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.2448082266 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 87866656 ps |
| CPU time | 3.03 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:36 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448082266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2448082266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.2626285891 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 417131190 ps |
| CPU time | 4.94 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:36:11 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626285891 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2626285891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.3416064119 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 57777477 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 02:33:46 AM UTC 24 |
| Finished | Oct 12 02:33:50 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416064119 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3416064119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.3365066311 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 290394748 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:16 AM UTC 24 |
| Peak memory | 232116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365066311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3365066311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.1571092093 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 93323167 ps |
| CPU time | 3 seconds |
| Started | Oct 12 02:34:40 AM UTC 24 |
| Finished | Oct 12 02:34:48 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571092093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1571092093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.2752582559 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 697882376 ps |
| CPU time | 5.92 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752582559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2752582559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.1600742380 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 52750832 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 02:21:21 AM UTC 24 |
| Finished | Oct 12 02:21:26 AM UTC 24 |
| Peak memory | 225972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600742380 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.1600742380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.4129528829 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 562954944 ps |
| CPU time | 9.88 seconds |
| Started | Oct 12 02:20:23 AM UTC 24 |
| Finished | Oct 12 02:20:34 AM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129528829 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.4129528829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.1059906815 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 298546956 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:35:59 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059906815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1059906815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.2050099780 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 46592092 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:03 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050099780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2050099780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.330730652 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 111565855 ps |
| CPU time | 4.48 seconds |
| Started | Oct 12 02:34:27 AM UTC 24 |
| Finished | Oct 12 02:34:32 AM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330730652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.330730652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.1467936690 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1574789245 ps |
| CPU time | 14.54 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1467936690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg r_stress_all_with_rand_reset.1467936690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.3146966768 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1210359727 ps |
| CPU time | 37.24 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:48 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146966768 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3146966768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.2875401311 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 67995569 ps |
| CPU time | 3.58 seconds |
| Started | Oct 12 02:34:24 AM UTC 24 |
| Finished | Oct 12 02:34:28 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875401311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2875401311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.986861324 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 591033883 ps |
| CPU time | 4.26 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:38 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986861324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.986861324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.3711836203 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 664011731 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 02:36:48 AM UTC 24 |
| Finished | Oct 12 02:37:10 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711836203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3711836203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.3737124584 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 198764074 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 02:35:07 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737124584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3737124584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.1935980713 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1471468511 ps |
| CPU time | 10.39 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:24 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935980713 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1935980713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.1487004037 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 189018270 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487004037 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1487004037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.1675751763 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 382962734 ps |
| CPU time | 7.15 seconds |
| Started | Oct 12 02:20:51 AM UTC 24 |
| Finished | Oct 12 02:20:59 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675751763 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.1675751763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.3067765079 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 60682506 ps |
| CPU time | 2.37 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:26 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067765079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3067765079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.801499519 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 179521861 ps |
| CPU time | 4.16 seconds |
| Started | Oct 12 02:34:14 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801499519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.801499519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.3817777178 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 295936839 ps |
| CPU time | 3.6 seconds |
| Started | Oct 12 02:34:18 AM UTC 24 |
| Finished | Oct 12 02:34:23 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817777178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3817777178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.170200551 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2961125230 ps |
| CPU time | 26.16 seconds |
| Started | Oct 12 02:35:17 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170200551 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.170200551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.739167230 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 46904602 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:32 AM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739167230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.739167230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.520287760 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1009643812 ps |
| CPU time | 24.51 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:55 AM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520287760 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.520287760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.2620048516 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 159808620 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620048516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2620048516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.916043665 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 102406503 ps |
| CPU time | 4.21 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916043665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.916043665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.2421045034 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3757072019 ps |
| CPU time | 14.31 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:36:05 AM UTC 24 |
| Peak memory | 225800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421045034 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2421045034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all_with_rand_reset.2520113974 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 853536683 ps |
| CPU time | 13.06 seconds |
| Started | Oct 12 02:35:50 AM UTC 24 |
| Finished | Oct 12 02:36:05 AM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2520113974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymg r_stress_all_with_rand_reset.2520113974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.213163545 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 571172906 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 02:36:29 AM UTC 24 |
| Finished | Oct 12 02:36:42 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213163545 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.213163545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.3390001161 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 639917971 ps |
| CPU time | 17.04 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:37:02 AM UTC 24 |
| Peak memory | 231748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3390001161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymg r_stress_all_with_rand_reset.3390001161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.3362478583 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1518756537 ps |
| CPU time | 17.16 seconds |
| Started | Oct 12 02:36:49 AM UTC 24 |
| Finished | Oct 12 02:37:07 AM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362478583 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3362478583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.2516621882 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 834438054 ps |
| CPU time | 11.92 seconds |
| Started | Oct 12 02:34:01 AM UTC 24 |
| Finished | Oct 12 02:34:14 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2516621882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr _stress_all_with_rand_reset.2516621882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1355127109 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 521669103 ps |
| CPU time | 7.65 seconds |
| Started | Oct 12 02:21:35 AM UTC 24 |
| Finished | Oct 12 02:21:44 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355127109 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.1355127109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1437342294 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 257634211 ps |
| CPU time | 8.93 seconds |
| Started | Oct 12 02:21:38 AM UTC 24 |
| Finished | Oct 12 02:21:48 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437342294 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.1437342294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.4240944747 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 142051585 ps |
| CPU time | 6.85 seconds |
| Started | Oct 12 02:21:49 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240944747 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.4240944747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.2567534637 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 185074631 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 02:20:57 AM UTC 24 |
| Finished | Oct 12 02:21:02 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567534637 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.2567534637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.3648825723 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 341725966 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 02:36:31 AM UTC 24 |
| Finished | Oct 12 02:36:38 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648825723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3648825723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.839405304 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 481960812 ps |
| CPU time | 3.98 seconds |
| Started | Oct 12 02:34:36 AM UTC 24 |
| Finished | Oct 12 02:34:41 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839405304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.839405304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2103790704 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 48763567 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 02:20:07 AM UTC 24 |
| Finished | Oct 12 02:20:11 AM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2103790704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w ith_rand_reset.2103790704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.4156340601 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 119438518 ps |
| CPU time | 5.08 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:29 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156340601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4156340601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.4036946915 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 58956800 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:27 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036946915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4036946915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.4239451698 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1653043801 ps |
| CPU time | 5.11 seconds |
| Started | Oct 12 02:33:21 AM UTC 24 |
| Finished | Oct 12 02:33:28 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239451698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4239451698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.3517107677 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 108229406 ps |
| CPU time | 3.51 seconds |
| Started | Oct 12 02:34:18 AM UTC 24 |
| Finished | Oct 12 02:34:23 AM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517107677 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3517107677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_random.1086262749 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 324699366 ps |
| CPU time | 5.58 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:29 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086262749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1086262749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.2577932816 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 227205513 ps |
| CPU time | 5.78 seconds |
| Started | Oct 12 02:34:27 AM UTC 24 |
| Finished | Oct 12 02:34:34 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577932816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2577932816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.1494296199 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 49909167 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 02:34:28 AM UTC 24 |
| Finished | Oct 12 02:34:32 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494296199 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1494296199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.4245114648 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 85267541 ps |
| CPU time | 3.33 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:36 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245114648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.4245114648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.4239822921 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1620574030 ps |
| CPU time | 13 seconds |
| Started | Oct 12 02:34:41 AM UTC 24 |
| Finished | Oct 12 02:34:58 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239822921 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4239822921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.3570303265 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1420441427 ps |
| CPU time | 12.07 seconds |
| Started | Oct 12 02:34:50 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3570303265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg r_stress_all_with_rand_reset.3570303265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.1422699933 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 304694894 ps |
| CPU time | 4.02 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:17 AM UTC 24 |
| Peak memory | 230252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422699933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1422699933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.2368950576 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 51177243 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 02:35:21 AM UTC 24 |
| Finished | Oct 12 02:35:25 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368950576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2368950576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.450823214 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 135571117 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450823214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.450823214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.1963879829 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 56870697 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963879829 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1963879829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.2982233123 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1604799357 ps |
| CPU time | 39.48 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:36:20 AM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982233123 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2982233123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.1859085300 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1425067284 ps |
| CPU time | 40.6 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:36:30 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859085300 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1859085300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.1323719721 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 89194790 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:02 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323719721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1323719721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.4138970214 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4721668528 ps |
| CPU time | 135.27 seconds |
| Started | Oct 12 02:36:00 AM UTC 24 |
| Finished | Oct 12 02:38:17 AM UTC 24 |
| Peak memory | 231972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138970214 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4138970214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.3877726001 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 60544404 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:14 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877726001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3877726001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.3196491754 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2988162026 ps |
| CPU time | 25.45 seconds |
| Started | Oct 12 02:36:39 AM UTC 24 |
| Finished | Oct 12 02:37:06 AM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196491754 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3196491754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1407376625 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 114146587 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:48 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407376625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1407376625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.1699893759 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 153975827 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:48 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699893759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1699893759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.2310595107 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 257953296 ps |
| CPU time | 6.43 seconds |
| Started | Oct 12 02:20:04 AM UTC 24 |
| Finished | Oct 12 02:20:12 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310595107 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2310595107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3417622454 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 486936552 ps |
| CPU time | 16.55 seconds |
| Started | Oct 12 02:20:03 AM UTC 24 |
| Finished | Oct 12 02:20:21 AM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417622454 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3417622454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1934690534 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 43332616 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:20:00 AM UTC 24 |
| Finished | Oct 12 02:20:03 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934690534 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1934690534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1328177523 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 35495360 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 02:20:03 AM UTC 24 |
| Finished | Oct 12 02:20:06 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328177523 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1328177523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.1772891238 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 45258932 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:20:00 AM UTC 24 |
| Finished | Oct 12 02:20:02 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772891238 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1772891238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1219322174 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 90748360 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 02:20:05 AM UTC 24 |
| Finished | Oct 12 02:20:11 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219322174 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1219322174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1613574142 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 242861519 ps |
| CPU time | 3.82 seconds |
| Started | Oct 12 02:19:55 AM UTC 24 |
| Finished | Oct 12 02:20:00 AM UTC 24 |
| Peak memory | 226400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613574142 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.1613574142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.357708502 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 606803493 ps |
| CPU time | 5.15 seconds |
| Started | Oct 12 02:19:58 AM UTC 24 |
| Finished | Oct 12 02:20:04 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357708502 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.357708502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.2259234084 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 601862461 ps |
| CPU time | 5.58 seconds |
| Started | Oct 12 02:19:59 AM UTC 24 |
| Finished | Oct 12 02:20:06 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259234084 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.2259234084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.162269689 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 772009127 ps |
| CPU time | 9.99 seconds |
| Started | Oct 12 02:20:17 AM UTC 24 |
| Finished | Oct 12 02:20:28 AM UTC 24 |
| Peak memory | 215564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162269689 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.162269689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1588593096 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 132349175 ps |
| CPU time | 10.31 seconds |
| Started | Oct 12 02:20:17 AM UTC 24 |
| Finished | Oct 12 02:20:29 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588593096 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1588593096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1605145995 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 67740496 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:20:15 AM UTC 24 |
| Finished | Oct 12 02:20:18 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605145995 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1605145995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1740171772 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 30167664 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:20:19 AM UTC 24 |
| Finished | Oct 12 02:20:22 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1740171772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.1740171772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.3318503276 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 20585773 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:20:17 AM UTC 24 |
| Finished | Oct 12 02:20:19 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318503276 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3318503276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.4038625454 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 15735059 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:20:14 AM UTC 24 |
| Finished | Oct 12 02:20:16 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038625454 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4038625454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.818226365 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 103053607 ps |
| CPU time | 4.99 seconds |
| Started | Oct 12 02:20:18 AM UTC 24 |
| Finished | Oct 12 02:20:24 AM UTC 24 |
| Peak memory | 215816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818226365 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.818226365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.599018898 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 117014128 ps |
| CPU time | 4.36 seconds |
| Started | Oct 12 02:20:08 AM UTC 24 |
| Finished | Oct 12 02:20:13 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599018898 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.599018898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.551856017 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 92484579 ps |
| CPU time | 6.01 seconds |
| Started | Oct 12 02:20:12 AM UTC 24 |
| Finished | Oct 12 02:20:19 AM UTC 24 |
| Peak memory | 226208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551856017 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.551856017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.2982258176 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 44864565 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 02:20:12 AM UTC 24 |
| Finished | Oct 12 02:20:16 AM UTC 24 |
| Peak memory | 226004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982258176 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2982258176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.383507714 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 270118112 ps |
| CPU time | 6.11 seconds |
| Started | Oct 12 02:20:13 AM UTC 24 |
| Finished | Oct 12 02:20:20 AM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383507714 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.383507714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1396078232 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 159164317 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:21:19 AM UTC 24 |
| Finished | Oct 12 02:21:22 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1396078232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.1396078232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.789497997 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 11929760 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:21:18 AM UTC 24 |
| Finished | Oct 12 02:21:20 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789497997 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.789497997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.1374078894 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 13079526 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:21:18 AM UTC 24 |
| Finished | Oct 12 02:21:20 AM UTC 24 |
| Peak memory | 213608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374078894 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1374078894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1653828679 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 273967284 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 02:21:19 AM UTC 24 |
| Finished | Oct 12 02:21:22 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653828679 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.1653828679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1386521150 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 574189135 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 02:21:14 AM UTC 24 |
| Finished | Oct 12 02:21:20 AM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386521150 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.1386521150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3252840749 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 306629829 ps |
| CPU time | 5.99 seconds |
| Started | Oct 12 02:21:16 AM UTC 24 |
| Finished | Oct 12 02:21:23 AM UTC 24 |
| Peak memory | 232324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252840749 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.3252840749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.1511850018 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 313385963 ps |
| CPU time | 4.67 seconds |
| Started | Oct 12 02:21:16 AM UTC 24 |
| Finished | Oct 12 02:21:21 AM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511850018 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1511850018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.306280670 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 197959414 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 02:21:23 AM UTC 24 |
| Finished | Oct 12 02:21:27 AM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=306280670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_w ith_rand_reset.306280670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3208018702 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 56325134 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:21:22 AM UTC 24 |
| Finished | Oct 12 02:21:25 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208018702 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3208018702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.1821755722 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 17366144 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:21:22 AM UTC 24 |
| Finished | Oct 12 02:21:25 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821755722 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1821755722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1722792163 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 116164986 ps |
| CPU time | 2.38 seconds |
| Started | Oct 12 02:21:22 AM UTC 24 |
| Finished | Oct 12 02:21:26 AM UTC 24 |
| Peak memory | 215728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722792163 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.1722792163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1501142192 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 173622017 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 02:21:20 AM UTC 24 |
| Finished | Oct 12 02:21:23 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501142192 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.1501142192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1535056986 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 216897185 ps |
| CPU time | 9.56 seconds |
| Started | Oct 12 02:21:21 AM UTC 24 |
| Finished | Oct 12 02:21:32 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535056986 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.1535056986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2648312153 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 135195646 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:21:21 AM UTC 24 |
| Finished | Oct 12 02:21:26 AM UTC 24 |
| Peak memory | 226048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648312153 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2648312153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.477221650 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 52173385 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 02:21:26 AM UTC 24 |
| Finished | Oct 12 02:21:30 AM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=477221650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_w ith_rand_reset.477221650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.1055269065 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 17391803 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:21:26 AM UTC 24 |
| Finished | Oct 12 02:21:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055269065 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1055269065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.513443602 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 8493815 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:21:25 AM UTC 24 |
| Finished | Oct 12 02:21:27 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513443602 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.513443602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2868753649 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 801440378 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:21:26 AM UTC 24 |
| Finished | Oct 12 02:21:30 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868753649 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.2868753649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1165122453 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 54766072 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:21:24 AM UTC 24 |
| Finished | Oct 12 02:21:27 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165122453 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.1165122453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2541075254 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 353821080 ps |
| CPU time | 6.19 seconds |
| Started | Oct 12 02:21:24 AM UTC 24 |
| Finished | Oct 12 02:21:31 AM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541075254 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.2541075254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.730986692 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 214764860 ps |
| CPU time | 5.14 seconds |
| Started | Oct 12 02:21:24 AM UTC 24 |
| Finished | Oct 12 02:21:30 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730986692 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.730986692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.2323658546 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 279036932 ps |
| CPU time | 7.03 seconds |
| Started | Oct 12 02:21:24 AM UTC 24 |
| Finished | Oct 12 02:21:32 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323658546 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.2323658546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3562010473 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 54695830 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 02:21:30 AM UTC 24 |
| Finished | Oct 12 02:21:34 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3562010473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.3562010473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.1004986778 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 46827592 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:21:29 AM UTC 24 |
| Finished | Oct 12 02:21:32 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004986778 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1004986778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.4066839109 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 45637391 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:21:28 AM UTC 24 |
| Finished | Oct 12 02:21:30 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066839109 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4066839109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4130959663 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 153974243 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:21:30 AM UTC 24 |
| Finished | Oct 12 02:21:34 AM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130959663 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.4130959663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2793633800 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 371342767 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:21:27 AM UTC 24 |
| Finished | Oct 12 02:21:31 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793633800 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.2793633800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4183202706 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 468879505 ps |
| CPU time | 6.43 seconds |
| Started | Oct 12 02:21:27 AM UTC 24 |
| Finished | Oct 12 02:21:35 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183202706 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.4183202706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.974158189 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 42717839 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 02:21:28 AM UTC 24 |
| Finished | Oct 12 02:21:34 AM UTC 24 |
| Peak memory | 226040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974158189 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.974158189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.2389954937 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 112107684 ps |
| CPU time | 5.92 seconds |
| Started | Oct 12 02:21:28 AM UTC 24 |
| Finished | Oct 12 02:21:35 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389954937 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.2389954937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3864623810 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 105129198 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 02:21:33 AM UTC 24 |
| Finished | Oct 12 02:21:36 AM UTC 24 |
| Peak memory | 230208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3864623810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.3864623810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1001235711 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 46602358 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:21:33 AM UTC 24 |
| Finished | Oct 12 02:21:35 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001235711 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1001235711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.341442333 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 45397552 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:21:32 AM UTC 24 |
| Finished | Oct 12 02:21:34 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341442333 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.341442333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2800464051 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 169425675 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:21:33 AM UTC 24 |
| Finished | Oct 12 02:21:36 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800464051 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.2800464051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.144954108 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 268390899 ps |
| CPU time | 3.75 seconds |
| Started | Oct 12 02:21:31 AM UTC 24 |
| Finished | Oct 12 02:21:35 AM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144954108 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.144954108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3983621412 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 1821153780 ps |
| CPU time | 14.72 seconds |
| Started | Oct 12 02:21:31 AM UTC 24 |
| Finished | Oct 12 02:21:47 AM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983621412 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.3983621412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.3117987576 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 76267161 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:21:32 AM UTC 24 |
| Finished | Oct 12 02:21:36 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117987576 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3117987576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.194556901 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 136421240 ps |
| CPU time | 6.86 seconds |
| Started | Oct 12 02:21:32 AM UTC 24 |
| Finished | Oct 12 02:21:40 AM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194556901 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.194556901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3739960676 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 174764721 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 02:21:37 AM UTC 24 |
| Finished | Oct 12 02:21:40 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3739960676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_ with_rand_reset.3739960676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1696165908 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 30743583 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:21:36 AM UTC 24 |
| Finished | Oct 12 02:21:39 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696165908 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1696165908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.3015008508 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 69478963 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:21:35 AM UTC 24 |
| Finished | Oct 12 02:21:37 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015008508 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3015008508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2155634147 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 168471340 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 02:21:36 AM UTC 24 |
| Finished | Oct 12 02:21:41 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155634147 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.2155634147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.252452845 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 198949598 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:21:34 AM UTC 24 |
| Finished | Oct 12 02:21:37 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252452845 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.252452845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.326871388 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 853354210 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 02:21:35 AM UTC 24 |
| Finished | Oct 12 02:21:43 AM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326871388 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.326871388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.387558101 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 52061399 ps |
| CPU time | 4.75 seconds |
| Started | Oct 12 02:21:35 AM UTC 24 |
| Finished | Oct 12 02:21:41 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387558101 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.387558101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.367817664 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 64992303 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:21:41 AM UTC 24 |
| Finished | Oct 12 02:21:44 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=367817664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_w ith_rand_reset.367817664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.3842686502 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 85421805 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:21:40 AM UTC 24 |
| Finished | Oct 12 02:21:42 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842686502 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3842686502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3524524317 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 20873983 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:21:39 AM UTC 24 |
| Finished | Oct 12 02:21:41 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524524317 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3524524317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.157103494 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 361311845 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 02:21:41 AM UTC 24 |
| Finished | Oct 12 02:21:45 AM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157103494 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.157103494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2677596882 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 133215330 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 02:21:37 AM UTC 24 |
| Finished | Oct 12 02:21:43 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677596882 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.2677596882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.11812622 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 1121381659 ps |
| CPU time | 6.41 seconds |
| Started | Oct 12 02:21:37 AM UTC 24 |
| Finished | Oct 12 02:21:44 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11812622 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.11812622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.26847398 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 861527689 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 02:21:38 AM UTC 24 |
| Finished | Oct 12 02:21:44 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26847398 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.26847398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1376582698 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 49451014 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 02:21:45 AM UTC 24 |
| Finished | Oct 12 02:21:48 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1376582698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.1376582698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.876743571 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 13593743 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:21:44 AM UTC 24 |
| Finished | Oct 12 02:21:47 AM UTC 24 |
| Peak memory | 213676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876743571 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.876743571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.2794812217 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 16469267 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:21:43 AM UTC 24 |
| Finished | Oct 12 02:21:45 AM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794812217 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2794812217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3939587764 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 85330275 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 02:21:45 AM UTC 24 |
| Finished | Oct 12 02:21:49 AM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939587764 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.3939587764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1873737951 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 179359415 ps |
| CPU time | 4.71 seconds |
| Started | Oct 12 02:21:42 AM UTC 24 |
| Finished | Oct 12 02:21:48 AM UTC 24 |
| Peak memory | 226524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873737951 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.1873737951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3810093224 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 144392449 ps |
| CPU time | 9.9 seconds |
| Started | Oct 12 02:21:42 AM UTC 24 |
| Finished | Oct 12 02:21:53 AM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810093224 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.3810093224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.2581002501 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 58807470 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 02:21:42 AM UTC 24 |
| Finished | Oct 12 02:21:46 AM UTC 24 |
| Peak memory | 226000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581002501 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2581002501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.2855040579 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 104629719 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 02:21:42 AM UTC 24 |
| Finished | Oct 12 02:21:47 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855040579 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.2855040579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2276296710 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 27977340 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:21:48 AM UTC 24 |
| Finished | Oct 12 02:21:51 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2276296710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.2276296710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2328039292 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 19719360 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 02:21:47 AM UTC 24 |
| Finished | Oct 12 02:21:50 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328039292 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2328039292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1405691468 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 15532260 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:21:46 AM UTC 24 |
| Finished | Oct 12 02:21:48 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405691468 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1405691468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2709897421 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 194107682 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:21:47 AM UTC 24 |
| Finished | Oct 12 02:21:50 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709897421 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.2709897421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.150027238 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 340349429 ps |
| CPU time | 4.51 seconds |
| Started | Oct 12 02:21:45 AM UTC 24 |
| Finished | Oct 12 02:21:50 AM UTC 24 |
| Peak memory | 226336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150027238 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.150027238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1315655516 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 282035785 ps |
| CPU time | 4.79 seconds |
| Started | Oct 12 02:21:45 AM UTC 24 |
| Finished | Oct 12 02:21:51 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315655516 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.1315655516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.756786643 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 559324216 ps |
| CPU time | 4.45 seconds |
| Started | Oct 12 02:21:45 AM UTC 24 |
| Finished | Oct 12 02:21:50 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756786643 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.756786643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.4064134332 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 217307135 ps |
| CPU time | 8.02 seconds |
| Started | Oct 12 02:21:46 AM UTC 24 |
| Finished | Oct 12 02:21:55 AM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064134332 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.4064134332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1044088207 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 109011725 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:21:51 AM UTC 24 |
| Finished | Oct 12 02:21:53 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1044088207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.1044088207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.3140701853 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 26937604 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:21:49 AM UTC 24 |
| Finished | Oct 12 02:21:52 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140701853 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3140701853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.4222384381 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 48129264 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:21:49 AM UTC 24 |
| Finished | Oct 12 02:21:52 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222384381 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4222384381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3211999868 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 48700931 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 02:21:50 AM UTC 24 |
| Finished | Oct 12 02:21:54 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211999868 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.3211999868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3586082655 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 127993115 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 02:21:48 AM UTC 24 |
| Finished | Oct 12 02:21:51 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586082655 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.3586082655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3418522249 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 381072841 ps |
| CPU time | 5.49 seconds |
| Started | Oct 12 02:21:49 AM UTC 24 |
| Finished | Oct 12 02:21:56 AM UTC 24 |
| Peak memory | 232324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418522249 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.3418522249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.1925638344 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 46753114 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 02:21:49 AM UTC 24 |
| Finished | Oct 12 02:21:54 AM UTC 24 |
| Peak memory | 225972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925638344 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1925638344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.2065392693 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 261045753 ps |
| CPU time | 8.99 seconds |
| Started | Oct 12 02:20:28 AM UTC 24 |
| Finished | Oct 12 02:20:38 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065392693 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2065392693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.414865356 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 4304147369 ps |
| CPU time | 18.03 seconds |
| Started | Oct 12 02:20:27 AM UTC 24 |
| Finished | Oct 12 02:20:46 AM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414865356 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.414865356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1750353296 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 17250820 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:20:25 AM UTC 24 |
| Finished | Oct 12 02:20:27 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750353296 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1750353296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2675047878 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 27882024 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 02:20:29 AM UTC 24 |
| Finished | Oct 12 02:20:32 AM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2675047878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.2675047878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.3357361800 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 97654081 ps |
| CPU time | 2 seconds |
| Started | Oct 12 02:20:26 AM UTC 24 |
| Finished | Oct 12 02:20:29 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357361800 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3357361800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.1388104210 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 13202896 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:20:24 AM UTC 24 |
| Finished | Oct 12 02:20:26 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388104210 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1388104210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.932212862 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 441183016 ps |
| CPU time | 5.88 seconds |
| Started | Oct 12 02:20:29 AM UTC 24 |
| Finished | Oct 12 02:20:36 AM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932212862 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.932212862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1329845395 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 280373682 ps |
| CPU time | 3.86 seconds |
| Started | Oct 12 02:20:20 AM UTC 24 |
| Finished | Oct 12 02:20:25 AM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329845395 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1329845395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3647091101 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 379057951 ps |
| CPU time | 17.09 seconds |
| Started | Oct 12 02:20:20 AM UTC 24 |
| Finished | Oct 12 02:20:39 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647091101 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.3647091101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.1172580365 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 110789037 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 02:20:21 AM UTC 24 |
| Finished | Oct 12 02:20:28 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172580365 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1172580365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1585747986 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 10202130 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:21:51 AM UTC 24 |
| Finished | Oct 12 02:21:53 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585747986 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1585747986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3617237980 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 21846415 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:21:51 AM UTC 24 |
| Finished | Oct 12 02:21:53 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617237980 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3617237980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.4243228082 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 24437773 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:21:51 AM UTC 24 |
| Finished | Oct 12 02:21:53 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243228082 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4243228082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2150921047 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 65251132 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:21:52 AM UTC 24 |
| Finished | Oct 12 02:21:54 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150921047 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2150921047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1282625391 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 64024717 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:21:52 AM UTC 24 |
| Finished | Oct 12 02:21:54 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282625391 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1282625391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.3849647935 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 49219975 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:21:52 AM UTC 24 |
| Finished | Oct 12 02:21:54 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849647935 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3849647935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.309593433 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 16484492 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:21:53 AM UTC 24 |
| Finished | Oct 12 02:21:55 AM UTC 24 |
| Peak memory | 213676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309593433 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.309593433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4280705594 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 38111125 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:21:53 AM UTC 24 |
| Finished | Oct 12 02:21:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280705594 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4280705594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3218893763 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 25996648 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:21:53 AM UTC 24 |
| Finished | Oct 12 02:21:55 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218893763 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3218893763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.2288158038 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 15073973 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:21:54 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288158038 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2288158038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.1520175666 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 184406806 ps |
| CPU time | 7.93 seconds |
| Started | Oct 12 02:20:39 AM UTC 24 |
| Finished | Oct 12 02:20:48 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520175666 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1520175666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.662591315 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 922109344 ps |
| CPU time | 14.85 seconds |
| Started | Oct 12 02:20:38 AM UTC 24 |
| Finished | Oct 12 02:20:54 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662591315 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.662591315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.336194296 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 30020799 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:20:36 AM UTC 24 |
| Finished | Oct 12 02:20:38 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336194296 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.336194296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3856037849 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 42764280 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 02:20:40 AM UTC 24 |
| Finished | Oct 12 02:20:44 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3856037849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.3856037849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1931459463 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 27901399 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:20:37 AM UTC 24 |
| Finished | Oct 12 02:20:39 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931459463 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1931459463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.4215608250 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 42594869 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:20:34 AM UTC 24 |
| Finished | Oct 12 02:20:37 AM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215608250 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4215608250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2495786372 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 110708928 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 02:20:39 AM UTC 24 |
| Finished | Oct 12 02:20:42 AM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495786372 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.2495786372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2591363569 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 249654732 ps |
| CPU time | 3.85 seconds |
| Started | Oct 12 02:20:29 AM UTC 24 |
| Finished | Oct 12 02:20:34 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591363569 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.2591363569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.3987537801 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3169199221 ps |
| CPU time | 5.15 seconds |
| Started | Oct 12 02:20:32 AM UTC 24 |
| Finished | Oct 12 02:20:39 AM UTC 24 |
| Peak memory | 226016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987537801 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3987537801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.3721593037 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 106862272 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 02:20:34 AM UTC 24 |
| Finished | Oct 12 02:20:42 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721593037 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.3721593037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.4084492981 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 14805133 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 02:21:54 AM UTC 24 |
| Finished | Oct 12 02:21:56 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084492981 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4084492981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.29965248 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 10016315 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:21:55 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29965248 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.29965248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.2645118889 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 21719596 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:21:55 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645118889 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2645118889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.747820127 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 18851361 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:21:55 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747820127 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.747820127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1302545555 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 10848248 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:21:55 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 213804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302545555 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1302545555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.1625833799 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 18364339 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:21:55 AM UTC 24 |
| Finished | Oct 12 02:21:57 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625833799 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1625833799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3711423585 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 23517116 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:21:56 AM UTC 24 |
| Finished | Oct 12 02:21:58 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711423585 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3711423585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.82392775 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 7743945 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 02:21:56 AM UTC 24 |
| Finished | Oct 12 02:21:58 AM UTC 24 |
| Peak memory | 213676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82392775 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.82392775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2810926491 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 11967943 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:21:56 AM UTC 24 |
| Finished | Oct 12 02:21:58 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810926491 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2810926491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2942368331 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 13920142 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:21:56 AM UTC 24 |
| Finished | Oct 12 02:21:58 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942368331 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2942368331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.260448358 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 1023630138 ps |
| CPU time | 9.46 seconds |
| Started | Oct 12 02:20:47 AM UTC 24 |
| Finished | Oct 12 02:20:57 AM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260448358 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.260448358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.227346037 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 267996546 ps |
| CPU time | 13.46 seconds |
| Started | Oct 12 02:20:45 AM UTC 24 |
| Finished | Oct 12 02:21:00 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227346037 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.227346037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3753775430 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 21851364 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:20:44 AM UTC 24 |
| Finished | Oct 12 02:20:47 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753775430 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3753775430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.243861205 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 28485478 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 02:20:48 AM UTC 24 |
| Finished | Oct 12 02:20:51 AM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=243861205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_wi th_rand_reset.243861205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.195596682 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 56985832 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 02:20:44 AM UTC 24 |
| Finished | Oct 12 02:20:47 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195596682 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.195596682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.1686287296 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 18806226 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:20:43 AM UTC 24 |
| Finished | Oct 12 02:20:45 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686287296 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1686287296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3656953579 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 108650392 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:20:47 AM UTC 24 |
| Finished | Oct 12 02:20:50 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656953579 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.3656953579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.40156891 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 182094126 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 02:20:40 AM UTC 24 |
| Finished | Oct 12 02:20:44 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40156891 -assert nopostproc +UVM_T ESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.40156891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3940769325 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 1768022456 ps |
| CPU time | 14.95 seconds |
| Started | Oct 12 02:20:40 AM UTC 24 |
| Finished | Oct 12 02:20:57 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940769325 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.3940769325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.3914228535 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 316240558 ps |
| CPU time | 2.87 seconds |
| Started | Oct 12 02:20:43 AM UTC 24 |
| Finished | Oct 12 02:20:47 AM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914228535 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3914228535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.3038433340 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 324708529 ps |
| CPU time | 13.3 seconds |
| Started | Oct 12 02:20:43 AM UTC 24 |
| Finished | Oct 12 02:20:58 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038433340 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.3038433340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.3718099540 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 9427582 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:21:56 AM UTC 24 |
| Finished | Oct 12 02:21:58 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718099540 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3718099540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2881257200 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 30203894 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:21:56 AM UTC 24 |
| Finished | Oct 12 02:21:58 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881257200 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2881257200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.583300615 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 11439341 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:21:57 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583300615 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.583300615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.816571978 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 13241145 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:21:57 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816571978 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.816571978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3430809058 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 58180411 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:21:57 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430809058 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3430809058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4173108909 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 37210051 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:21:57 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173108909 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4173108909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1769219704 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 13689938 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:21:57 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769219704 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1769219704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.3726406292 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 64907737 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:21:57 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 214020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726406292 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3726406292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1953603481 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 33987101 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 02:21:58 AM UTC 24 |
| Finished | Oct 12 02:22:00 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953603481 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1953603481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3860011750 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 40888003 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:21:59 AM UTC 24 |
| Finished | Oct 12 02:22:01 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860011750 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3860011750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.508617576 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 57935852 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 02:20:54 AM UTC 24 |
| Finished | Oct 12 02:20:58 AM UTC 24 |
| Peak memory | 225992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=508617576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_wi th_rand_reset.508617576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.2317247508 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 65103459 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:20:54 AM UTC 24 |
| Finished | Oct 12 02:20:57 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317247508 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2317247508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.3251279266 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8881563 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:20:52 AM UTC 24 |
| Finished | Oct 12 02:20:54 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251279266 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3251279266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.93008947 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 436899298 ps |
| CPU time | 3.06 seconds |
| Started | Oct 12 02:20:54 AM UTC 24 |
| Finished | Oct 12 02:20:58 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93008947 -assert nopostproc +UV M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.93008947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.251703034 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 192166920 ps |
| CPU time | 4.69 seconds |
| Started | Oct 12 02:20:48 AM UTC 24 |
| Finished | Oct 12 02:20:53 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251703034 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.251703034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1181650514 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 219417263 ps |
| CPU time | 6.78 seconds |
| Started | Oct 12 02:20:49 AM UTC 24 |
| Finished | Oct 12 02:20:57 AM UTC 24 |
| Peak memory | 232548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181650514 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.1181650514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.1765660235 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 311305767 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:20:49 AM UTC 24 |
| Finished | Oct 12 02:20:53 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765660235 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1765660235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3371150923 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 81506061 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:21:00 AM UTC 24 |
| Finished | Oct 12 02:21:03 AM UTC 24 |
| Peak memory | 226072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3371150923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w ith_rand_reset.3371150923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.1373321762 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 40792745 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 02:20:59 AM UTC 24 |
| Finished | Oct 12 02:21:02 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373321762 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1373321762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.2918490465 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 13039865 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:20:59 AM UTC 24 |
| Finished | Oct 12 02:21:01 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918490465 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2918490465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2527484444 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 139425175 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 02:20:59 AM UTC 24 |
| Finished | Oct 12 02:21:03 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527484444 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.2527484444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3062963553 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 194011500 ps |
| CPU time | 5.48 seconds |
| Started | Oct 12 02:20:55 AM UTC 24 |
| Finished | Oct 12 02:21:02 AM UTC 24 |
| Peak memory | 226448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062963553 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.3062963553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3226955190 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2850362659 ps |
| CPU time | 13.7 seconds |
| Started | Oct 12 02:20:57 AM UTC 24 |
| Finished | Oct 12 02:21:13 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226955190 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.3226955190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.2809280738 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 291972044 ps |
| CPU time | 4.68 seconds |
| Started | Oct 12 02:20:57 AM UTC 24 |
| Finished | Oct 12 02:21:04 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809280738 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2809280738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2410686755 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 105287382 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 02:21:04 AM UTC 24 |
| Finished | Oct 12 02:21:09 AM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2410686755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w ith_rand_reset.2410686755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.3638653418 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 97303296 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 02:21:03 AM UTC 24 |
| Finished | Oct 12 02:21:06 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638653418 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3638653418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.2097911010 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 15968185 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:21:03 AM UTC 24 |
| Finished | Oct 12 02:21:05 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097911010 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2097911010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3741281711 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 232638972 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:21:04 AM UTC 24 |
| Finished | Oct 12 02:21:07 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741281711 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.3741281711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1539888803 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 330439175 ps |
| CPU time | 5.48 seconds |
| Started | Oct 12 02:21:00 AM UTC 24 |
| Finished | Oct 12 02:21:07 AM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539888803 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.1539888803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.983398104 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 211359082 ps |
| CPU time | 10.27 seconds |
| Started | Oct 12 02:21:01 AM UTC 24 |
| Finished | Oct 12 02:21:13 AM UTC 24 |
| Peak memory | 226188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983398104 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.983398104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.2706614238 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 310745783 ps |
| CPU time | 4.34 seconds |
| Started | Oct 12 02:21:02 AM UTC 24 |
| Finished | Oct 12 02:21:07 AM UTC 24 |
| Peak memory | 225920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706614238 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2706614238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.831245631 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 255445594 ps |
| CPU time | 5.2 seconds |
| Started | Oct 12 02:21:02 AM UTC 24 |
| Finished | Oct 12 02:21:08 AM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831245631 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.831245631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3225818661 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 134779847 ps |
| CPU time | 3.03 seconds |
| Started | Oct 12 02:21:10 AM UTC 24 |
| Finished | Oct 12 02:21:14 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3225818661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w ith_rand_reset.3225818661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.3970025633 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 64673929 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:21:09 AM UTC 24 |
| Finished | Oct 12 02:21:11 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970025633 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3970025633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.1390553880 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 19328808 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:21:09 AM UTC 24 |
| Finished | Oct 12 02:21:11 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390553880 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1390553880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.974480545 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 72687899 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 02:21:09 AM UTC 24 |
| Finished | Oct 12 02:21:13 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974480545 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.974480545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4280451471 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 306130710 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 02:21:04 AM UTC 24 |
| Finished | Oct 12 02:21:09 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280451471 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.4280451471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1123458052 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1354409702 ps |
| CPU time | 15.25 seconds |
| Started | Oct 12 02:21:06 AM UTC 24 |
| Finished | Oct 12 02:21:23 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123458052 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.1123458052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.1935820542 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 271411049 ps |
| CPU time | 6.96 seconds |
| Started | Oct 12 02:21:07 AM UTC 24 |
| Finished | Oct 12 02:21:15 AM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935820542 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1935820542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1825647564 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 48382491 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 02:21:14 AM UTC 24 |
| Finished | Oct 12 02:21:17 AM UTC 24 |
| Peak memory | 213684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1825647564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.1825647564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.1764263941 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 13279272 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:21:14 AM UTC 24 |
| Finished | Oct 12 02:21:17 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764263941 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1764263941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.2891089500 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 17467767 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:21:13 AM UTC 24 |
| Finished | Oct 12 02:21:15 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891089500 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2891089500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2752401253 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 204013126 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 02:21:14 AM UTC 24 |
| Finished | Oct 12 02:21:18 AM UTC 24 |
| Peak memory | 215884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752401253 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.2752401253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3398501415 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 231852344 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 02:21:10 AM UTC 24 |
| Finished | Oct 12 02:21:14 AM UTC 24 |
| Peak memory | 226208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398501415 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3398501415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2987591766 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 609316107 ps |
| CPU time | 7.95 seconds |
| Started | Oct 12 02:21:12 AM UTC 24 |
| Finished | Oct 12 02:21:21 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987591766 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.2987591766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.480022616 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 210408589 ps |
| CPU time | 5.16 seconds |
| Started | Oct 12 02:21:12 AM UTC 24 |
| Finished | Oct 12 02:21:18 AM UTC 24 |
| Peak memory | 226196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480022616 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.480022616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.4048320623 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 74572404 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 02:21:13 AM UTC 24 |
| Finished | Oct 12 02:21:19 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048320623 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.4048320623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.1067162824 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 41829928 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:25 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067162824 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1067162824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.3991754677 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1111620215 ps |
| CPU time | 17.41 seconds |
| Started | Oct 12 02:33:22 AM UTC 24 |
| Finished | Oct 12 02:33:40 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991754677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3991754677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_random.889825947 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 173625297 ps |
| CPU time | 4.85 seconds |
| Started | Oct 12 02:33:22 AM UTC 24 |
| Finished | Oct 12 02:33:28 AM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889825947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.889825947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.1618481102 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 137256077 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 02:33:22 AM UTC 24 |
| Finished | Oct 12 02:33:25 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618481102 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1618481102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.129718040 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 68194728 ps |
| CPU time | 3.39 seconds |
| Started | Oct 12 02:33:21 AM UTC 24 |
| Finished | Oct 12 02:33:26 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129718040 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.129718040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.3399124604 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1361532377 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 02:33:22 AM UTC 24 |
| Finished | Oct 12 02:33:26 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399124604 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3399124604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.554240647 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 613548612 ps |
| CPU time | 10.55 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:35 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554240647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.554240647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.1078383527 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 87358314 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:33:21 AM UTC 24 |
| Finished | Oct 12 02:33:25 AM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078383527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1078383527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.1563744200 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 40011667 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:33:28 AM UTC 24 |
| Finished | Oct 12 02:33:31 AM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563744200 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1563744200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.602564550 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 84568047 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 02:33:25 AM UTC 24 |
| Finished | Oct 12 02:33:28 AM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602564550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.602564550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.111909479 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 56512370 ps |
| CPU time | 2.16 seconds |
| Started | Oct 12 02:33:26 AM UTC 24 |
| Finished | Oct 12 02:33:29 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111909479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.111909479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.1498340931 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 215245255 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 02:33:27 AM UTC 24 |
| Finished | Oct 12 02:33:32 AM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498340931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1498340931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_random.4162373843 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2899548935 ps |
| CPU time | 20.18 seconds |
| Started | Oct 12 02:33:24 AM UTC 24 |
| Finished | Oct 12 02:33:46 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162373843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4162373843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.1698279096 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2266332195 ps |
| CPU time | 13.49 seconds |
| Started | Oct 12 02:33:28 AM UTC 24 |
| Finished | Oct 12 02:33:43 AM UTC 24 |
| Peak memory | 253760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698279096 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1698279096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.1222168368 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 222139894 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:27 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222168368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1222168368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.3362473362 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 221962419 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:29 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362473362 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3362473362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.2686611774 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 212367563 ps |
| CPU time | 6.09 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:31 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686611774 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2686611774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.3602798372 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 129499993 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:27 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602798372 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3602798372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.3121095867 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 40532092 ps |
| CPU time | 2.28 seconds |
| Started | Oct 12 02:33:27 AM UTC 24 |
| Finished | Oct 12 02:33:30 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121095867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3121095867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.1559695797 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1271170421 ps |
| CPU time | 10.46 seconds |
| Started | Oct 12 02:33:23 AM UTC 24 |
| Finished | Oct 12 02:33:35 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559695797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1559695797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.242250221 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 444813208 ps |
| CPU time | 6.74 seconds |
| Started | Oct 12 02:33:26 AM UTC 24 |
| Finished | Oct 12 02:33:34 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242250221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.242250221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.2830683595 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 45598318 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 02:33:27 AM UTC 24 |
| Finished | Oct 12 02:33:31 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830683595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2830683595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.2224169382 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 13662755 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:17 AM UTC 24 |
| Peak memory | 213316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224169382 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2224169382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.2914841061 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2246551673 ps |
| CPU time | 27.29 seconds |
| Started | Oct 12 02:34:12 AM UTC 24 |
| Finished | Oct 12 02:34:41 AM UTC 24 |
| Peak memory | 223720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914841061 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2914841061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.1093445114 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 215083208 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:20 AM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093445114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1093445114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.4162960918 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 148362387 ps |
| CPU time | 3.6 seconds |
| Started | Oct 12 02:34:13 AM UTC 24 |
| Finished | Oct 12 02:34:18 AM UTC 24 |
| Peak memory | 215440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162960918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4162960918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.2376303046 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 243776604 ps |
| CPU time | 3.58 seconds |
| Started | Oct 12 02:34:14 AM UTC 24 |
| Finished | Oct 12 02:34:18 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376303046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2376303046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.584297705 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 272995908 ps |
| CPU time | 4.81 seconds |
| Started | Oct 12 02:34:13 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 219568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584297705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.584297705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_random.650055653 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 238553793 ps |
| CPU time | 5.08 seconds |
| Started | Oct 12 02:34:12 AM UTC 24 |
| Finished | Oct 12 02:34:18 AM UTC 24 |
| Peak memory | 219564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650055653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.650055653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.402885204 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1324519749 ps |
| CPU time | 36.72 seconds |
| Started | Oct 12 02:34:11 AM UTC 24 |
| Finished | Oct 12 02:34:49 AM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402885204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.402885204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.1954803226 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 22841683 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 02:34:12 AM UTC 24 |
| Finished | Oct 12 02:34:16 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954803226 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1954803226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.1138249221 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 220557868 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 02:34:11 AM UTC 24 |
| Finished | Oct 12 02:34:18 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138249221 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1138249221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.2055247448 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 50208249 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:34:12 AM UTC 24 |
| Finished | Oct 12 02:34:16 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055247448 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2055247448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.949405259 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1662668858 ps |
| CPU time | 14.5 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949405259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.949405259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1454629350 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 32717616 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:34:11 AM UTC 24 |
| Finished | Oct 12 02:34:14 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454629350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1454629350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.1065215368 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 437980796 ps |
| CPU time | 7.53 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:24 AM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1065215368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg r_stress_all_with_rand_reset.1065215368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.1223195860 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 301437940 ps |
| CPU time | 5.34 seconds |
| Started | Oct 12 02:34:13 AM UTC 24 |
| Finished | Oct 12 02:34:20 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223195860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1223195860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.3537357082 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 803372847 ps |
| CPU time | 2.71 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537357082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3537357082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.1028726943 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 144501550 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:23 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028726943 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1028726943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.2531428808 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 40055920 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:24 AM UTC 24 |
| Peak memory | 232020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531428808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2531428808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.4110495720 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 67229105 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 02:34:18 AM UTC 24 |
| Finished | Oct 12 02:34:21 AM UTC 24 |
| Peak memory | 217348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110495720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4110495720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.1259993804 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 67410255 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:24 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259993804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1259993804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.1382805524 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 37319407 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 02:34:18 AM UTC 24 |
| Finished | Oct 12 02:34:23 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382805524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1382805524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_random.3180257541 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 256648703 ps |
| CPU time | 3.76 seconds |
| Started | Oct 12 02:34:17 AM UTC 24 |
| Finished | Oct 12 02:34:22 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180257541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3180257541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.2427308883 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2315026042 ps |
| CPU time | 16.39 seconds |
| Started | Oct 12 02:34:17 AM UTC 24 |
| Finished | Oct 12 02:34:34 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427308883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2427308883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.2768768131 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 610088792 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:34:17 AM UTC 24 |
| Finished | Oct 12 02:34:21 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768768131 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2768768131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.1573077149 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 58040453 ps |
| CPU time | 3.21 seconds |
| Started | Oct 12 02:34:17 AM UTC 24 |
| Finished | Oct 12 02:34:21 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573077149 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1573077149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.3807268805 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 96975198 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 02:34:17 AM UTC 24 |
| Finished | Oct 12 02:34:21 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807268805 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3807268805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.1685358447 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 67873366 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:24 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685358447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1685358447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.3737622703 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 61199301 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:34:15 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737622703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3737622703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.2408802579 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 166813062 ps |
| CPU time | 7.89 seconds |
| Started | Oct 12 02:34:18 AM UTC 24 |
| Finished | Oct 12 02:34:27 AM UTC 24 |
| Peak memory | 219636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408802579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2408802579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.4002284335 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 304144459 ps |
| CPU time | 7.5 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:29 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002284335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4002284335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.2987455415 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 33721890 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:34:24 AM UTC 24 |
| Finished | Oct 12 02:34:26 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987455415 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2987455415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.1690372781 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1680239186 ps |
| CPU time | 9.33 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:33 AM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690372781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1690372781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.3822506460 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 176243747 ps |
| CPU time | 4.01 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:28 AM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822506460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3822506460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.1029246552 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 30068552 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:26 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029246552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1029246552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.1552139604 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 230465454 ps |
| CPU time | 3.36 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:27 AM UTC 24 |
| Peak memory | 223804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552139604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1552139604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.2735306316 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 58273102 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:25 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735306316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2735306316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.577992220 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 158992048 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:34:21 AM UTC 24 |
| Finished | Oct 12 02:34:25 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577992220 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.577992220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.3414393592 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 86824691 ps |
| CPU time | 3.88 seconds |
| Started | Oct 12 02:34:21 AM UTC 24 |
| Finished | Oct 12 02:34:26 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414393592 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3414393592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.2848630852 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2126682230 ps |
| CPU time | 9.73 seconds |
| Started | Oct 12 02:34:21 AM UTC 24 |
| Finished | Oct 12 02:34:32 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848630852 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2848630852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.1057991300 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 154389136 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:26 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057991300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1057991300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.1090436420 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 480094362 ps |
| CPU time | 4.97 seconds |
| Started | Oct 12 02:34:20 AM UTC 24 |
| Finished | Oct 12 02:34:27 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090436420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1090436420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.914265845 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2727415530 ps |
| CPU time | 13.01 seconds |
| Started | Oct 12 02:34:24 AM UTC 24 |
| Finished | Oct 12 02:34:38 AM UTC 24 |
| Peak memory | 231240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914265845 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.914265845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.2858614548 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 6420701396 ps |
| CPU time | 14.53 seconds |
| Started | Oct 12 02:34:24 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2858614548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg r_stress_all_with_rand_reset.2858614548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.3337906220 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 337414984 ps |
| CPU time | 4.25 seconds |
| Started | Oct 12 02:34:22 AM UTC 24 |
| Finished | Oct 12 02:34:28 AM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337906220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3337906220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.2333448166 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 97643138 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:34:29 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333448166 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2333448166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.2025415646 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 613800844 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 02:34:28 AM UTC 24 |
| Finished | Oct 12 02:34:33 AM UTC 24 |
| Peak memory | 228032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025415646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2025415646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.976464760 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 36491707 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 02:34:26 AM UTC 24 |
| Finished | Oct 12 02:34:30 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976464760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.976464760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.2243009827 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 222669014 ps |
| CPU time | 3.7 seconds |
| Started | Oct 12 02:34:26 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243009827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2243009827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_random.3358414342 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 324359241 ps |
| CPU time | 4.41 seconds |
| Started | Oct 12 02:34:25 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358414342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3358414342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.3506411696 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 296304473 ps |
| CPU time | 5.26 seconds |
| Started | Oct 12 02:34:24 AM UTC 24 |
| Finished | Oct 12 02:34:30 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506411696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3506411696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.790750934 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 955435242 ps |
| CPU time | 4.5 seconds |
| Started | Oct 12 02:34:25 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790750934 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.790750934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.3393838699 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 264256277 ps |
| CPU time | 7.42 seconds |
| Started | Oct 12 02:34:25 AM UTC 24 |
| Finished | Oct 12 02:34:34 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393838699 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3393838699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.3055064031 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 66192716 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 02:34:25 AM UTC 24 |
| Finished | Oct 12 02:34:30 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055064031 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3055064031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.952485666 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 54277624 ps |
| CPU time | 2.16 seconds |
| Started | Oct 12 02:34:28 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952485666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.952485666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1134007894 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 266130636 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 02:34:24 AM UTC 24 |
| Finished | Oct 12 02:34:27 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134007894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1134007894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.3947518097 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1674498017 ps |
| CPU time | 7.98 seconds |
| Started | Oct 12 02:34:27 AM UTC 24 |
| Finished | Oct 12 02:34:36 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947518097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3947518097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.565274146 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 42782064 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 02:34:28 AM UTC 24 |
| Finished | Oct 12 02:34:32 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565274146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.565274146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.4070382208 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 9969094 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:36 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070382208 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4070382208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.2796606678 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 521488317 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 02:34:31 AM UTC 24 |
| Finished | Oct 12 02:34:34 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796606678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2796606678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.3273864936 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 90917812 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:35 AM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273864936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3273864936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_random.1810261981 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1344534857 ps |
| CPU time | 31.85 seconds |
| Started | Oct 12 02:34:31 AM UTC 24 |
| Finished | Oct 12 02:35:04 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810261981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1810261981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.2833213453 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 325862371 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 02:34:29 AM UTC 24 |
| Finished | Oct 12 02:34:34 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833213453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2833213453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.1553573527 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1472414000 ps |
| CPU time | 33.61 seconds |
| Started | Oct 12 02:34:31 AM UTC 24 |
| Finished | Oct 12 02:35:06 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553573527 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1553573527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.1418551864 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 22746053 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 02:34:29 AM UTC 24 |
| Finished | Oct 12 02:34:33 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418551864 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1418551864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.651126243 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 106882317 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 02:34:31 AM UTC 24 |
| Finished | Oct 12 02:34:34 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651126243 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.651126243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.1888083433 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 457773855 ps |
| CPU time | 5.96 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888083433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1888083433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.3265925269 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 133200010 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:34:29 AM UTC 24 |
| Finished | Oct 12 02:34:33 AM UTC 24 |
| Peak memory | 215564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265925269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3265925269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.726371288 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 557792180 ps |
| CPU time | 18.37 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:53 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=726371288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr _stress_all_with_rand_reset.726371288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.359157884 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 233223473 ps |
| CPU time | 2.66 seconds |
| Started | Oct 12 02:34:32 AM UTC 24 |
| Finished | Oct 12 02:34:36 AM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359157884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.359157884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2054028080 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 14443979 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054028080 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2054028080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.76886102 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 60201538 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76886102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.76886102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.3143396023 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 735608700 ps |
| CPU time | 4.42 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143396023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3143396023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.448090637 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 59082352 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 02:34:36 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448090637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.448090637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.4286351001 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 35075139 ps |
| CPU time | 2.62 seconds |
| Started | Oct 12 02:34:36 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286351001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4286351001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.3558056208 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1085967932 ps |
| CPU time | 4.26 seconds |
| Started | Oct 12 02:34:35 AM UTC 24 |
| Finished | Oct 12 02:34:41 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558056208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3558056208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_random.4164406118 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 608257845 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164406118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4164406118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.1325172757 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 211477586 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:38 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325172757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1325172757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.736471521 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 98693148 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:37 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736471521 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.736471521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.3123625558 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 73824049 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:37 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123625558 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3123625558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.3013929134 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2586385825 ps |
| CPU time | 46.07 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013929134 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3013929134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.3478547126 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 290659961 ps |
| CPU time | 3.72 seconds |
| Started | Oct 12 02:34:36 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 217228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478547126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3478547126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.3177038014 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 156400851 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 02:34:34 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177038014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3177038014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.860694530 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 9451200764 ps |
| CPU time | 191.48 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:37:51 AM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860694530 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.860694530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.4095333817 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 411609391 ps |
| CPU time | 12.72 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:34:51 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4095333817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg r_stress_all_with_rand_reset.4095333817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.2548687932 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 79078997 ps |
| CPU time | 3.69 seconds |
| Started | Oct 12 02:34:35 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548687932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2548687932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3803956660 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 82288825 ps |
| CPU time | 3.51 seconds |
| Started | Oct 12 02:34:36 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803956660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3803956660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.932089965 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 26359590 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 02:34:41 AM UTC 24 |
| Finished | Oct 12 02:34:46 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932089965 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.932089965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.1066486338 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 252250165 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 02:34:39 AM UTC 24 |
| Finished | Oct 12 02:34:45 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066486338 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1066486338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1213077401 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1459721594 ps |
| CPU time | 2.98 seconds |
| Started | Oct 12 02:34:40 AM UTC 24 |
| Finished | Oct 12 02:34:48 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213077401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1213077401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.1199402176 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 199707595 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:34:39 AM UTC 24 |
| Finished | Oct 12 02:34:42 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199402176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1199402176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.1143220411 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 35399684 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 02:34:40 AM UTC 24 |
| Finished | Oct 12 02:34:47 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143220411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1143220411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.1365030406 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 272307272 ps |
| CPU time | 3.03 seconds |
| Started | Oct 12 02:34:39 AM UTC 24 |
| Finished | Oct 12 02:34:43 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365030406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1365030406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_random.4197411660 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 564993291 ps |
| CPU time | 5.22 seconds |
| Started | Oct 12 02:34:39 AM UTC 24 |
| Finished | Oct 12 02:34:46 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197411660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4197411660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2852944751 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 541343229 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:34:42 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852944751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2852944751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.1197245127 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 58498495 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:34:41 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197245127 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1197245127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.3356366410 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 354129659 ps |
| CPU time | 5.17 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:34:43 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356366410 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3356366410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3126070169 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 429537007 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:34:39 AM UTC 24 |
| Finished | Oct 12 02:34:43 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126070169 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3126070169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.147798445 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 365775410 ps |
| CPU time | 3.59 seconds |
| Started | Oct 12 02:34:40 AM UTC 24 |
| Finished | Oct 12 02:34:48 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147798445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.147798445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.70618271 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 38836332 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 02:34:37 AM UTC 24 |
| Finished | Oct 12 02:34:40 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70618271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.70618271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.571904999 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 498379687 ps |
| CPU time | 4.85 seconds |
| Started | Oct 12 02:34:39 AM UTC 24 |
| Finished | Oct 12 02:34:46 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571904999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.571904999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.969611363 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 176058134 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 02:34:41 AM UTC 24 |
| Finished | Oct 12 02:34:47 AM UTC 24 |
| Peak memory | 219632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969611363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.969611363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2382635581 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 14145001 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 02:34:44 AM UTC 24 |
| Finished | Oct 12 02:34:57 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382635581 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2382635581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.1431248582 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 7966307487 ps |
| CPU time | 37.57 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431248582 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1431248582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.3359922618 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 243174399 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:35:03 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359922618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3359922618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.3970707298 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1034712738 ps |
| CPU time | 18.78 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:35:19 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970707298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3970707298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.3779882197 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 191327907 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:35:02 AM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779882197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3779882197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.1004734267 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 258207639 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:34:53 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004734267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1004734267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.1648434647 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 750877877 ps |
| CPU time | 4.09 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:35:05 AM UTC 24 |
| Peak memory | 224000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648434647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1648434647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_random.2015114976 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 376311605 ps |
| CPU time | 6.42 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:34:57 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015114976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2015114976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.3664075884 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 96953181 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 02:34:41 AM UTC 24 |
| Finished | Oct 12 02:34:47 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664075884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3664075884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.1044142227 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 304202090 ps |
| CPU time | 2.24 seconds |
| Started | Oct 12 02:34:44 AM UTC 24 |
| Finished | Oct 12 02:34:48 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044142227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1044142227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.1958242893 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1171273774 ps |
| CPU time | 18.06 seconds |
| Started | Oct 12 02:34:41 AM UTC 24 |
| Finished | Oct 12 02:35:23 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958242893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1958242893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.2420244363 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 7274651115 ps |
| CPU time | 70.72 seconds |
| Started | Oct 12 02:34:44 AM UTC 24 |
| Finished | Oct 12 02:35:57 AM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420244363 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2420244363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.2185500942 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 624032933 ps |
| CPU time | 6.36 seconds |
| Started | Oct 12 02:34:44 AM UTC 24 |
| Finished | Oct 12 02:34:52 AM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2185500942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymg r_stress_all_with_rand_reset.2185500942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.3995201266 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 185154084 ps |
| CPU time | 4.83 seconds |
| Started | Oct 12 02:34:42 AM UTC 24 |
| Finished | Oct 12 02:35:05 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995201266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3995201266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.4245854971 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1038024397 ps |
| CPU time | 6.67 seconds |
| Started | Oct 12 02:34:44 AM UTC 24 |
| Finished | Oct 12 02:34:52 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245854971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4245854971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.3695107326 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 14115834 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:34:51 AM UTC 24 |
| Finished | Oct 12 02:34:56 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695107326 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3695107326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.2399243240 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 616543056 ps |
| CPU time | 7.7 seconds |
| Started | Oct 12 02:34:47 AM UTC 24 |
| Finished | Oct 12 02:35:03 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399243240 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2399243240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.2475555194 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 494076585 ps |
| CPU time | 2.73 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:35:04 AM UTC 24 |
| Peak memory | 224008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475555194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2475555194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.4222714189 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 141512270 ps |
| CPU time | 3.7 seconds |
| Started | Oct 12 02:34:47 AM UTC 24 |
| Finished | Oct 12 02:34:59 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222714189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4222714189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.2688978287 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 163550065 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:34:55 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688978287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2688978287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.531457664 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 483502660 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:35:03 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531457664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.531457664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.3442636807 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 922795679 ps |
| CPU time | 4.92 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:35:06 AM UTC 24 |
| Peak memory | 227968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442636807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3442636807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_random.1150276059 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 504740725 ps |
| CPU time | 4.17 seconds |
| Started | Oct 12 02:34:47 AM UTC 24 |
| Finished | Oct 12 02:35:00 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150276059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1150276059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.1854194470 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 67265777 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 02:34:45 AM UTC 24 |
| Finished | Oct 12 02:34:58 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854194470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1854194470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.1655881453 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 162742645 ps |
| CPU time | 4.84 seconds |
| Started | Oct 12 02:34:46 AM UTC 24 |
| Finished | Oct 12 02:34:55 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655881453 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1655881453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.3255091101 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 353532101 ps |
| CPU time | 9.7 seconds |
| Started | Oct 12 02:34:46 AM UTC 24 |
| Finished | Oct 12 02:35:00 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255091101 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3255091101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.349077948 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 73923117 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:34:46 AM UTC 24 |
| Finished | Oct 12 02:34:53 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349077948 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.349077948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.4237096980 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 48507348 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:35:03 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237096980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4237096980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.2762497089 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 235855605 ps |
| CPU time | 3.78 seconds |
| Started | Oct 12 02:34:45 AM UTC 24 |
| Finished | Oct 12 02:35:00 AM UTC 24 |
| Peak memory | 217388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762497089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2762497089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.3733754698 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1003537409 ps |
| CPU time | 10.96 seconds |
| Started | Oct 12 02:34:50 AM UTC 24 |
| Finished | Oct 12 02:35:19 AM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733754698 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3733754698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.755593284 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1518099437 ps |
| CPU time | 25.31 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755593284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.755593284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.3030798959 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 96913416 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:34:49 AM UTC 24 |
| Finished | Oct 12 02:35:04 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030798959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3030798959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.3770382509 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 13097590 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:10 AM UTC 24 |
| Peak memory | 211796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770382509 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3770382509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.748448544 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 332906870 ps |
| CPU time | 4.25 seconds |
| Started | Oct 12 02:34:55 AM UTC 24 |
| Finished | Oct 12 02:35:00 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748448544 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.748448544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1810957186 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 128999712 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 02:34:58 AM UTC 24 |
| Finished | Oct 12 02:35:02 AM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810957186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1810957186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.2412655421 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 73388325 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 02:34:56 AM UTC 24 |
| Finished | Oct 12 02:35:09 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412655421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2412655421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.4073907898 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 31686063 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 02:34:58 AM UTC 24 |
| Finished | Oct 12 02:35:02 AM UTC 24 |
| Peak memory | 231084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073907898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4073907898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.3998577811 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 121311074 ps |
| CPU time | 2.73 seconds |
| Started | Oct 12 02:34:58 AM UTC 24 |
| Finished | Oct 12 02:35:03 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998577811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3998577811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.3712658428 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 144651136 ps |
| CPU time | 4.32 seconds |
| Started | Oct 12 02:34:56 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712658428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3712658428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_random.2241441374 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 521159557 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 02:34:55 AM UTC 24 |
| Finished | Oct 12 02:35:01 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241441374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2241441374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.2471012614 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1134230881 ps |
| CPU time | 12.67 seconds |
| Started | Oct 12 02:34:53 AM UTC 24 |
| Finished | Oct 12 02:35:08 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471012614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2471012614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.4206890905 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1100278637 ps |
| CPU time | 6.04 seconds |
| Started | Oct 12 02:34:53 AM UTC 24 |
| Finished | Oct 12 02:35:01 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206890905 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4206890905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.2502069981 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 449151298 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 02:34:53 AM UTC 24 |
| Finished | Oct 12 02:34:59 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502069981 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2502069981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.3667972545 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 214999895 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:34:55 AM UTC 24 |
| Finished | Oct 12 02:34:57 AM UTC 24 |
| Peak memory | 214916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667972545 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3667972545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.1951891077 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 72757546 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:34:59 AM UTC 24 |
| Finished | Oct 12 02:35:03 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951891077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1951891077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.342806546 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 85790644 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 02:34:51 AM UTC 24 |
| Finished | Oct 12 02:34:58 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342806546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.342806546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.946290856 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 680049535 ps |
| CPU time | 12.39 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=946290856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr _stress_all_with_rand_reset.946290856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.341588454 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 48247053 ps |
| CPU time | 3.05 seconds |
| Started | Oct 12 02:34:57 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341588454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.341588454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.3813363388 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 241140169 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 02:34:59 AM UTC 24 |
| Finished | Oct 12 02:35:02 AM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813363388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3813363388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.3507127087 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 22998368 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:33:34 AM UTC 24 |
| Finished | Oct 12 02:33:36 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507127087 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3507127087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.414785928 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 105653643 ps |
| CPU time | 7.37 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:39 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414785928 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.414785928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.1845509682 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2895887688 ps |
| CPU time | 43.99 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:34:16 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845509682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1845509682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.1658774047 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 278484649 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:35 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658774047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1658774047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.2492335908 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 76672489 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:33 AM UTC 24 |
| Peak memory | 223284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492335908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2492335908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3519765811 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 82623991 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:36 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519765811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3519765811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_random.1999590668 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 210942825 ps |
| CPU time | 3.89 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:35 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999590668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1999590668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.1291999801 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6964203595 ps |
| CPU time | 10.1 seconds |
| Started | Oct 12 02:33:33 AM UTC 24 |
| Finished | Oct 12 02:33:44 AM UTC 24 |
| Peak memory | 258584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291999801 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1291999801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.1800117280 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 180353585 ps |
| CPU time | 2.33 seconds |
| Started | Oct 12 02:33:28 AM UTC 24 |
| Finished | Oct 12 02:33:32 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800117280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1800117280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.1770856286 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 493582293 ps |
| CPU time | 4.03 seconds |
| Started | Oct 12 02:33:29 AM UTC 24 |
| Finished | Oct 12 02:33:34 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770856286 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1770856286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.190812732 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2574921670 ps |
| CPU time | 6.4 seconds |
| Started | Oct 12 02:33:28 AM UTC 24 |
| Finished | Oct 12 02:33:36 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190812732 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.190812732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.2554398772 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 814339520 ps |
| CPU time | 19.38 seconds |
| Started | Oct 12 02:33:29 AM UTC 24 |
| Finished | Oct 12 02:33:49 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554398772 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2554398772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.3137349520 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3246461047 ps |
| CPU time | 25.77 seconds |
| Started | Oct 12 02:33:31 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137349520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3137349520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.2530764210 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 53903881 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 02:33:28 AM UTC 24 |
| Finished | Oct 12 02:33:32 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530764210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2530764210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.3465449407 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1061389294 ps |
| CPU time | 9.15 seconds |
| Started | Oct 12 02:33:31 AM UTC 24 |
| Finished | Oct 12 02:33:42 AM UTC 24 |
| Peak memory | 228144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3465449407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr _stress_all_with_rand_reset.3465449407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.2893444756 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 118291485 ps |
| CPU time | 4.34 seconds |
| Started | Oct 12 02:33:30 AM UTC 24 |
| Finished | Oct 12 02:33:36 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893444756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2893444756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.3239835783 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 29684301 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:33:31 AM UTC 24 |
| Finished | Oct 12 02:33:34 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239835783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3239835783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.843986775 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 42057946 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:07 AM UTC 24 |
| Peak memory | 213280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843986775 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.843986775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.4035678280 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 87704202 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:35:03 AM UTC 24 |
| Finished | Oct 12 02:35:07 AM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035678280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4035678280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.2989322059 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 102855204 ps |
| CPU time | 3.77 seconds |
| Started | Oct 12 02:35:02 AM UTC 24 |
| Finished | Oct 12 02:35:10 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989322059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2989322059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.3253406635 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 761968017 ps |
| CPU time | 5 seconds |
| Started | Oct 12 02:35:03 AM UTC 24 |
| Finished | Oct 12 02:35:10 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253406635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3253406635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2708686555 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 42006208 ps |
| CPU time | 2 seconds |
| Started | Oct 12 02:35:03 AM UTC 24 |
| Finished | Oct 12 02:35:07 AM UTC 24 |
| Peak memory | 222048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708686555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2708686555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.696600582 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 130537833 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 02:35:03 AM UTC 24 |
| Finished | Oct 12 02:35:08 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696600582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.696600582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_random.1543308560 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 201983099 ps |
| CPU time | 5.82 seconds |
| Started | Oct 12 02:35:02 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543308560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1543308560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.3598978488 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 62054765 ps |
| CPU time | 2.95 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598978488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3598978488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.175983176 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 395666537 ps |
| CPU time | 5.38 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:14 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175983176 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.175983176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.690991998 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 128069782 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690991998 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.690991998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.3035682126 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 65024536 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035682126 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3035682126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.4201406194 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 74581422 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:35:03 AM UTC 24 |
| Finished | Oct 12 02:35:07 AM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201406194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4201406194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.3341940292 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 8089157821 ps |
| CPU time | 29.28 seconds |
| Started | Oct 12 02:35:01 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341940292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3341940292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.19952065 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 234092434 ps |
| CPU time | 14.53 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=19952065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_ stress_all_with_rand_reset.19952065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.3322594723 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 301863461 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 02:35:03 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322594723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3322594723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.1207244906 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 97877330 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:08 AM UTC 24 |
| Peak memory | 217232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207244906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1207244906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.2040798557 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 140398902 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:35:09 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040798557 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2040798557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.3116578760 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 129385502 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 02:35:08 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116578760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3116578760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.983768585 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 40434858 ps |
| CPU time | 3.55 seconds |
| Started | Oct 12 02:35:07 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983768585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.983768585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.249499143 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 43967701 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 02:35:08 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249499143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.249499143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.3530202808 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 509194050 ps |
| CPU time | 3.59 seconds |
| Started | Oct 12 02:35:07 AM UTC 24 |
| Finished | Oct 12 02:35:12 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530202808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3530202808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_random.3211607426 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 109479234 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 02:35:06 AM UTC 24 |
| Finished | Oct 12 02:35:10 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211607426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3211607426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.3134668466 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 202380098 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134668466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3134668466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.1822902050 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 109366767 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 02:35:06 AM UTC 24 |
| Finished | Oct 12 02:35:10 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822902050 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1822902050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.3495433218 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 67951138 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:09 AM UTC 24 |
| Peak memory | 217808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495433218 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3495433218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.348468435 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 14611427084 ps |
| CPU time | 50.05 seconds |
| Started | Oct 12 02:35:06 AM UTC 24 |
| Finished | Oct 12 02:35:58 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348468435 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.348468435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.1659836137 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 60193798 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 02:35:08 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659836137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1659836137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.3624507856 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 670712933 ps |
| CPU time | 4.65 seconds |
| Started | Oct 12 02:35:05 AM UTC 24 |
| Finished | Oct 12 02:35:11 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624507856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3624507856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.3929638427 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2075504637 ps |
| CPU time | 19.74 seconds |
| Started | Oct 12 02:35:09 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929638427 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3929638427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all_with_rand_reset.4120828926 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 282565202 ps |
| CPU time | 7.57 seconds |
| Started | Oct 12 02:35:09 AM UTC 24 |
| Finished | Oct 12 02:35:18 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4120828926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymg r_stress_all_with_rand_reset.4120828926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.2269035845 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 393620509 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 02:35:07 AM UTC 24 |
| Finished | Oct 12 02:35:15 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269035845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2269035845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.1382122203 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 517957697 ps |
| CPU time | 7.54 seconds |
| Started | Oct 12 02:35:09 AM UTC 24 |
| Finished | Oct 12 02:35:18 AM UTC 24 |
| Peak memory | 219704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382122203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1382122203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.1651752398 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 37688500 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:16 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651752398 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1651752398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.2738934762 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 69996978 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:15 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738934762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2738934762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.1975643608 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 489580087 ps |
| CPU time | 6.4 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975643608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1975643608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.1199254241 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 59484610 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:17 AM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199254241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1199254241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_random.1411367951 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 173329876 ps |
| CPU time | 6.22 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:19 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411367951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1411367951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.7955616 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 125184234 ps |
| CPU time | 2.45 seconds |
| Started | Oct 12 02:35:10 AM UTC 24 |
| Finished | Oct 12 02:35:14 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7955616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.7955616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.642645453 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 357831742 ps |
| CPU time | 4.27 seconds |
| Started | Oct 12 02:35:10 AM UTC 24 |
| Finished | Oct 12 02:35:16 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642645453 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.642645453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.1514132540 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 120451702 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 02:35:10 AM UTC 24 |
| Finished | Oct 12 02:35:15 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514132540 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1514132540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3918422815 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 98588530 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:16 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918422815 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3918422815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.2303830924 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 96604411 ps |
| CPU time | 3.21 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:17 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303830924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2303830924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.1736761300 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1430471811 ps |
| CPU time | 24.07 seconds |
| Started | Oct 12 02:35:10 AM UTC 24 |
| Finished | Oct 12 02:35:36 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736761300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1736761300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.3799027502 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 152131556 ps |
| CPU time | 7.05 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799027502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3799027502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.904963706 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 159763983 ps |
| CPU time | 3.84 seconds |
| Started | Oct 12 02:35:12 AM UTC 24 |
| Finished | Oct 12 02:35:18 AM UTC 24 |
| Peak memory | 219920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904963706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.904963706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.3962596938 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 14112834 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:35:19 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962596938 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3962596938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.778448312 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 108185288 ps |
| CPU time | 4.34 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 225352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778448312 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.778448312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.871565978 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 84654007 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 02:35:17 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871565978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.871565978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.3671708734 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 47370667 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:18 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671708734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3671708734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.3772699369 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 50115678 ps |
| CPU time | 3.98 seconds |
| Started | Oct 12 02:35:16 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772699369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3772699369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.1711596727 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 394067273 ps |
| CPU time | 5.29 seconds |
| Started | Oct 12 02:35:16 AM UTC 24 |
| Finished | Oct 12 02:35:22 AM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711596727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1711596727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.2832693062 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 53037594 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 02:35:16 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832693062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2832693062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_random.3015547993 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 316698206 ps |
| CPU time | 5.81 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015547993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3015547993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.3190427959 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 38166402 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:19 AM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190427959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3190427959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.4106211610 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1722078838 ps |
| CPU time | 12.25 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:28 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106211610 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4106211610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.1883164445 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 259626575 ps |
| CPU time | 4.77 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883164445 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1883164445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.3262302843 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 31574381 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:19 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262302843 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3262302843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.3330847761 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 30027135 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 02:35:17 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330847761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3330847761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.1344539255 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 424980752 ps |
| CPU time | 4.64 seconds |
| Started | Oct 12 02:35:14 AM UTC 24 |
| Finished | Oct 12 02:35:20 AM UTC 24 |
| Peak memory | 217504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344539255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1344539255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.3298920935 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 65621031 ps |
| CPU time | 4.27 seconds |
| Started | Oct 12 02:35:16 AM UTC 24 |
| Finished | Oct 12 02:35:21 AM UTC 24 |
| Peak memory | 223788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298920935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3298920935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.2118194310 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 72585062 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 02:35:17 AM UTC 24 |
| Finished | Oct 12 02:35:22 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118194310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2118194310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.2255695507 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 39780532 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:25 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255695507 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2255695507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.1088936335 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 223437321 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 02:35:20 AM UTC 24 |
| Finished | Oct 12 02:35:25 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088936335 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1088936335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.2003671883 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 916528297 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 02:35:21 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003671883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2003671883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.2280280623 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1625456803 ps |
| CPU time | 4.17 seconds |
| Started | Oct 12 02:35:21 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280280623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2280280623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.1702567089 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 71479480 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 02:35:21 AM UTC 24 |
| Finished | Oct 12 02:35:24 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702567089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1702567089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.2228819841 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 92408867 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 02:35:21 AM UTC 24 |
| Finished | Oct 12 02:35:24 AM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228819841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2228819841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_random.177663417 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 488834751 ps |
| CPU time | 5.13 seconds |
| Started | Oct 12 02:35:20 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177663417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.177663417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.1647271401 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 117463083 ps |
| CPU time | 3.44 seconds |
| Started | Oct 12 02:35:19 AM UTC 24 |
| Finished | Oct 12 02:35:23 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647271401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1647271401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1095493459 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 76203005 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 02:35:19 AM UTC 24 |
| Finished | Oct 12 02:35:24 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095493459 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1095493459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.3760025849 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 188747027 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 02:35:19 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760025849 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3760025849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.4210842441 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 184030091 ps |
| CPU time | 5.8 seconds |
| Started | Oct 12 02:35:19 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210842441 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4210842441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.819291534 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 206411201 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:35:22 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819291534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.819291534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.1880594724 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1541272731 ps |
| CPU time | 28.9 seconds |
| Started | Oct 12 02:35:19 AM UTC 24 |
| Finished | Oct 12 02:35:49 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880594724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1880594724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.3824665485 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 344190618 ps |
| CPU time | 7.04 seconds |
| Started | Oct 12 02:35:22 AM UTC 24 |
| Finished | Oct 12 02:35:31 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824665485 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3824665485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.1179702642 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2190253741 ps |
| CPU time | 17.44 seconds |
| Started | Oct 12 02:35:22 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1179702642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymg r_stress_all_with_rand_reset.1179702642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1632521245 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3714341686 ps |
| CPU time | 22.01 seconds |
| Started | Oct 12 02:35:21 AM UTC 24 |
| Finished | Oct 12 02:35:44 AM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632521245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1632521245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.3234721151 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 153212688 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 02:35:22 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 219632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234721151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3234721151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.4123147488 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 74543406 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 02:35:25 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123147488 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.4123147488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.1827020386 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 104770022 ps |
| CPU time | 4.4 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:28 AM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827020386 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1827020386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.1670319389 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 248053546 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 02:35:24 AM UTC 24 |
| Finished | Oct 12 02:35:28 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670319389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1670319389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.1448801941 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 102581415 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448801941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1448801941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.2649007122 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 284206590 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:28 AM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649007122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2649007122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.3892443779 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 46416458 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 223896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892443779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3892443779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_random.3396590136 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 380455107 ps |
| CPU time | 5.63 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396590136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3396590136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.2003224324 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 81042288 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:26 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003224324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2003224324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.3082878779 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 67795453 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082878779 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3082878779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.481729322 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 72980220 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:27 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481729322 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.481729322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.896286624 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 189164884 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896286624 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.896286624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.264548074 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 127777526 ps |
| CPU time | 3.14 seconds |
| Started | Oct 12 02:35:24 AM UTC 24 |
| Finished | Oct 12 02:35:29 AM UTC 24 |
| Peak memory | 217488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264548074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.264548074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3735734933 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 6137482511 ps |
| CPU time | 22.22 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735734933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3735734933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.4195796189 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 616486029 ps |
| CPU time | 6.45 seconds |
| Started | Oct 12 02:35:25 AM UTC 24 |
| Finished | Oct 12 02:35:32 AM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195796189 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4195796189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.3548502007 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 101348246 ps |
| CPU time | 4.3 seconds |
| Started | Oct 12 02:35:23 AM UTC 24 |
| Finished | Oct 12 02:35:29 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548502007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3548502007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.1400384468 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 436588322 ps |
| CPU time | 4.57 seconds |
| Started | Oct 12 02:35:24 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400384468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1400384468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.1813826753 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 46728947 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 02:35:29 AM UTC 24 |
| Finished | Oct 12 02:35:31 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813826753 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1813826753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2616547808 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 947504417 ps |
| CPU time | 9.52 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:39 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616547808 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2616547808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.1150121674 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 938103872 ps |
| CPU time | 6.47 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:36 AM UTC 24 |
| Peak memory | 217916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150121674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1150121674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.3545067988 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 15148791962 ps |
| CPU time | 33.95 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:36:04 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545067988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3545067988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.3630239836 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 67625124 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:32 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630239836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3630239836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.1794163614 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 198032758 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:32 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794163614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1794163614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_random.2175415066 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 745980604 ps |
| CPU time | 3.32 seconds |
| Started | Oct 12 02:35:26 AM UTC 24 |
| Finished | Oct 12 02:35:31 AM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175415066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2175415066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.2621150440 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 54914049 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 02:35:25 AM UTC 24 |
| Finished | Oct 12 02:35:28 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621150440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2621150440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.4001596061 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 65867630 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 02:35:26 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001596061 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4001596061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.599947220 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 254939503 ps |
| CPU time | 4.03 seconds |
| Started | Oct 12 02:35:25 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599947220 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.599947220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.3130136575 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 99031439 ps |
| CPU time | 2.72 seconds |
| Started | Oct 12 02:35:26 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130136575 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3130136575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.1531288420 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 39525138 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:32 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531288420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1531288420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.3706641971 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 541911148 ps |
| CPU time | 4.04 seconds |
| Started | Oct 12 02:35:25 AM UTC 24 |
| Finished | Oct 12 02:35:30 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706641971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3706641971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all_with_rand_reset.1294064056 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 437092473 ps |
| CPU time | 12.74 seconds |
| Started | Oct 12 02:35:29 AM UTC 24 |
| Finished | Oct 12 02:35:43 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1294064056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymg r_stress_all_with_rand_reset.1294064056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.46704253 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2303267509 ps |
| CPU time | 24.18 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:54 AM UTC 24 |
| Peak memory | 219636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46704253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.46704253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.987034600 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 461277351 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 02:35:28 AM UTC 24 |
| Finished | Oct 12 02:35:33 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987034600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.987034600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.3692298308 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 14477652 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:35 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692298308 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3692298308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.483695724 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 487245623 ps |
| CPU time | 5.56 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:37 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483695724 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.483695724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.3434251617 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1926925058 ps |
| CPU time | 6.32 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:40 AM UTC 24 |
| Peak memory | 223264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434251617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3434251617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.1605453113 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 32927342 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:33 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605453113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1605453113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.2333212243 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 78657069 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:35 AM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333212243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2333212243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.3904639271 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 151617525 ps |
| CPU time | 6 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:39 AM UTC 24 |
| Peak memory | 223308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904639271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3904639271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.3514861522 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 133522736 ps |
| CPU time | 3.27 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:35 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514861522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3514861522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_random.3237437665 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 27200750 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:34 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237437665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3237437665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.310628375 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 789386553 ps |
| CPU time | 5.41 seconds |
| Started | Oct 12 02:35:29 AM UTC 24 |
| Finished | Oct 12 02:35:35 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310628375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.310628375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.1603768260 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 195840247 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:34 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603768260 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1603768260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1229500520 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 122708517 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:34 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229500520 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1229500520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.3440043996 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 204799298 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:33 AM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440043996 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3440043996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.3110865870 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 590764126 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:37 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110865870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3110865870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.849836348 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 469854773 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 02:35:29 AM UTC 24 |
| Finished | Oct 12 02:35:34 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849836348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.849836348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.2096795289 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1025370259 ps |
| CPU time | 20.87 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:54 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096795289 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2096795289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all_with_rand_reset.1182863770 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 174036427 ps |
| CPU time | 11.26 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1182863770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymg r_stress_all_with_rand_reset.1182863770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.3488056377 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 65139238 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:35:30 AM UTC 24 |
| Finished | Oct 12 02:35:35 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488056377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3488056377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.528941710 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 233791535 ps |
| CPU time | 2.95 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:36 AM UTC 24 |
| Peak memory | 219600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528941710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.528941710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.136867731 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 13394595 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136867731 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.136867731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.1954395712 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 48239188 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954395712 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1954395712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.2309768660 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1859674189 ps |
| CPU time | 10.09 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309768660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2309768660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.3182141584 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 240054849 ps |
| CPU time | 3 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182141584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3182141584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.2118846286 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 50492206 ps |
| CPU time | 2.26 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:35:39 AM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118846286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2118846286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.481443334 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 43156238 ps |
| CPU time | 2.62 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:37 AM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481443334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.481443334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_random.1718033663 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1008718754 ps |
| CPU time | 3.54 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718033663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1718033663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.1445705582 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 181218487 ps |
| CPU time | 3.06 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:37 AM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445705582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1445705582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.2315474367 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 24245578 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:35 AM UTC 24 |
| Peak memory | 217388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315474367 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2315474367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.1642121378 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 31289926 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:36 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642121378 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1642121378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.2545187316 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 221813270 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:40 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545187316 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2545187316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.1623648121 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 32338253 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:35:39 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623648121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1623648121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.2210155464 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 109611253 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 02:35:32 AM UTC 24 |
| Finished | Oct 12 02:35:36 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210155464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2210155464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.2147737776 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1736460879 ps |
| CPU time | 25.75 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:36:03 AM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147737776 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2147737776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.3756034902 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 717833301 ps |
| CPU time | 20.12 seconds |
| Started | Oct 12 02:35:34 AM UTC 24 |
| Finished | Oct 12 02:35:55 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756034902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3756034902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.3087960520 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 47090435 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:35:35 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087960520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3087960520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.1435247705 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 24788919 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435247705 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1435247705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.553267412 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 147373988 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:44 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553267412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.553267412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.3864287694 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 626565797 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:42 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864287694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3864287694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.3035932269 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 396253215 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:43 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035932269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3035932269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.2231209855 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 79150809 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231209855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2231209855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_random.1147148902 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 162210758 ps |
| CPU time | 5.1 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:43 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147148902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1147148902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.3629750274 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 117007342 ps |
| CPU time | 3.2 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629750274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3629750274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.2098414139 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 97082546 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098414139 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2098414139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.1610720336 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 259908003 ps |
| CPU time | 3.58 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610720336 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1610720336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.3230722873 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 433208580 ps |
| CPU time | 9.21 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230722873 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3230722873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3807526349 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 34422614 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:42 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807526349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3807526349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3133724285 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 146627632 ps |
| CPU time | 3.38 seconds |
| Started | Oct 12 02:35:37 AM UTC 24 |
| Finished | Oct 12 02:35:41 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133724285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3133724285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.3546909365 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 636067095 ps |
| CPU time | 9.38 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:50 AM UTC 24 |
| Peak memory | 231280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3546909365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg r_stress_all_with_rand_reset.3546909365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.168833183 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 339399630 ps |
| CPU time | 7.33 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168833183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.168833183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.2158016811 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 284978989 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 02:35:39 AM UTC 24 |
| Finished | Oct 12 02:35:43 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158016811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2158016811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.2058739063 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 41795090 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:33:38 AM UTC 24 |
| Finished | Oct 12 02:33:40 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058739063 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2058739063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.663032843 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 239511418 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 02:33:36 AM UTC 24 |
| Finished | Oct 12 02:33:41 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663032843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.663032843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.2260255883 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 86077720 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 02:33:36 AM UTC 24 |
| Finished | Oct 12 02:33:42 AM UTC 24 |
| Peak memory | 231464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260255883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2260255883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.573206422 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 222063347 ps |
| CPU time | 3.44 seconds |
| Started | Oct 12 02:33:36 AM UTC 24 |
| Finished | Oct 12 02:33:41 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573206422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.573206422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.435883919 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 506173859 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 02:33:36 AM UTC 24 |
| Finished | Oct 12 02:33:42 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435883919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.435883919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_random.1251628219 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1406944015 ps |
| CPU time | 11.28 seconds |
| Started | Oct 12 02:33:35 AM UTC 24 |
| Finished | Oct 12 02:33:48 AM UTC 24 |
| Peak memory | 223752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251628219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1251628219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.1131604011 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 342922858 ps |
| CPU time | 8.93 seconds |
| Started | Oct 12 02:33:38 AM UTC 24 |
| Finished | Oct 12 02:33:48 AM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131604011 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1131604011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.2497927455 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 102797494 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:33:34 AM UTC 24 |
| Finished | Oct 12 02:33:38 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497927455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2497927455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.2480166152 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 193093181 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 02:33:35 AM UTC 24 |
| Finished | Oct 12 02:33:41 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480166152 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2480166152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.1063644001 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 48963467 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 02:33:34 AM UTC 24 |
| Finished | Oct 12 02:33:37 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063644001 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1063644001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.2062078636 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 28099012 ps |
| CPU time | 2.96 seconds |
| Started | Oct 12 02:33:37 AM UTC 24 |
| Finished | Oct 12 02:33:41 AM UTC 24 |
| Peak memory | 227960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062078636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2062078636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.434978162 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 34620297 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 02:33:34 AM UTC 24 |
| Finished | Oct 12 02:33:37 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434978162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.434978162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.3031470714 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1427847719 ps |
| CPU time | 29.19 seconds |
| Started | Oct 12 02:33:36 AM UTC 24 |
| Finished | Oct 12 02:34:07 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031470714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3031470714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.1057777761 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 186002289 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 02:33:38 AM UTC 24 |
| Finished | Oct 12 02:33:41 AM UTC 24 |
| Peak memory | 217264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057777761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1057777761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.2224784620 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 11625075 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224784620 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2224784620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.3233801183 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 533591127 ps |
| CPU time | 4.97 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233801183 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3233801183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.3626813064 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 424862117 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 224136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626813064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3626813064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.410109062 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 34561340 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:44 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410109062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.410109062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.138865638 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 509376386 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 223688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138865638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.138865638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.3040547156 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 516467479 ps |
| CPU time | 4.06 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040547156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3040547156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_random.2297810342 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 80945902 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297810342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2297810342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.3672622615 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 249222532 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672622615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3672622615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.3573102124 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 622118856 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:49 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573102124 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3573102124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.3842238458 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 75642499 ps |
| CPU time | 2.97 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842238458 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3842238458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.1829385431 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 124896534 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829385431 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1829385431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3130432684 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 219631016 ps |
| CPU time | 2.85 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130432684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3130432684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.1645210960 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3773791836 ps |
| CPU time | 15.84 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:58 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645210960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1645210960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3461866585 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 51404205 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:35:41 AM UTC 24 |
| Finished | Oct 12 02:35:45 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461866585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3461866585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.3411931809 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 288984520 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 217712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411931809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3411931809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.3910389615 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 46139487 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:50 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910389615 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3910389615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.4005590370 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 489959448 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:50 AM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005590370 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4005590370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.1412705476 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 43816880 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:48 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412705476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1412705476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.1547034137 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 103175331 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:48 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547034137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1547034137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.2743926931 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 452604068 ps |
| CPU time | 4.82 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743926931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2743926931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.3698840800 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 201040526 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:48 AM UTC 24 |
| Peak memory | 229360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698840800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3698840800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_random.3113502619 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 99729941 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:49 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113502619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3113502619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.2665085931 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 57843462 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665085931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2665085931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.3409513854 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 221883237 ps |
| CPU time | 5.88 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:50 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409513854 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3409513854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.1262677904 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 234029054 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:50 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262677904 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1262677904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.2958334123 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 138673118 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958334123 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2958334123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.1042871508 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 157029076 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:48 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042871508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1042871508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.3147159083 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 91682861 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 02:35:43 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 213492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147159083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3147159083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all_with_rand_reset.2390517561 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 573552082 ps |
| CPU time | 19.07 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2390517561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymg r_stress_all_with_rand_reset.2390517561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.1751779723 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 228487303 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 02:35:45 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751779723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1751779723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.3987299037 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 64606536 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987299037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3987299037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.2565683206 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 16802713 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 02:35:50 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565683206 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2565683206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.1888068732 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 115621829 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:53 AM UTC 24 |
| Peak memory | 223692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888068732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1888068732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.1718770845 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 202558359 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718770845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1718770845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.1786900914 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 63089366 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 230860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786900914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1786900914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.2389590656 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 74929240 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 223804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389590656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2389590656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.4269337685 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 188821851 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269337685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4269337685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_random.2119148376 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 254460635 ps |
| CPU time | 3.92 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:53 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119148376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2119148376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.2879952209 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 808514766 ps |
| CPU time | 12.4 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:36:01 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879952209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2879952209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.1698009873 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 300737329 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698009873 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1698009873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.2751187218 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 79642365 ps |
| CPU time | 3.27 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751187218 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2751187218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.2145003628 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 39335818 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145003628 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2145003628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.2056383070 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 88729533 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:51 AM UTC 24 |
| Peak memory | 223344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056383070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2056383070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.3392770126 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 122069646 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392770126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3392770126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1470767316 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 956938630 ps |
| CPU time | 20.06 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470767316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1470767316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.3422600181 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 37485016 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:35:48 AM UTC 24 |
| Finished | Oct 12 02:35:52 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422600181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3422600181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.306140000 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 25051708 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:06 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306140000 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.306140000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.4012609071 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 508234994 ps |
| CPU time | 13.21 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012609071 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4012609071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.171801487 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 75407363 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:35:57 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171801487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.171801487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.1333652611 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 139466880 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 223752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333652611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1333652611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.2710382783 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 68530526 ps |
| CPU time | 2.43 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 223684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710382783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2710382783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.3082816940 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 366365690 ps |
| CPU time | 3.82 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:35:59 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082816940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3082816940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_random.3509263994 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 235208629 ps |
| CPU time | 7.45 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:36:02 AM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509263994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3509263994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.3673558903 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 156636076 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 02:35:50 AM UTC 24 |
| Finished | Oct 12 02:35:54 AM UTC 24 |
| Peak memory | 217808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673558903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3673558903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.4097655039 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 24889814 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 02:35:50 AM UTC 24 |
| Finished | Oct 12 02:35:53 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097655039 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4097655039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.3667050689 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 483926957 ps |
| CPU time | 2.73 seconds |
| Started | Oct 12 02:35:50 AM UTC 24 |
| Finished | Oct 12 02:35:57 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667050689 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3667050689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.3037264008 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 201583206 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:35:57 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037264008 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3037264008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.3422452018 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 34781681 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:35:56 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422452018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3422452018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.3491669622 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 137370412 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 02:35:50 AM UTC 24 |
| Finished | Oct 12 02:35:53 AM UTC 24 |
| Peak memory | 217408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491669622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3491669622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3709727427 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 910945339 ps |
| CPU time | 16.81 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:22 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709727427 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3709727427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.3149110413 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 783136302 ps |
| CPU time | 9.44 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:15 AM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3149110413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymg r_stress_all_with_rand_reset.3149110413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.657320920 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 426420488 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:35:58 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657320920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.657320920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.4024429974 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 388015111 ps |
| CPU time | 2.46 seconds |
| Started | Oct 12 02:35:51 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024429974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.4024429974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.3290050524 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 45941206 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:07 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290050524 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3290050524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.1298232995 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 63516886 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298232995 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1298232995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.179693400 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 599425768 ps |
| CPU time | 4 seconds |
| Started | Oct 12 02:35:54 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179693400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.179693400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.3112720337 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 348595699 ps |
| CPU time | 6.11 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:12 AM UTC 24 |
| Peak memory | 228108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112720337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3112720337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.3484732146 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 110644421 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 02:35:54 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484732146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3484732146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.4273219392 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 510577295 ps |
| CPU time | 4 seconds |
| Started | Oct 12 02:35:54 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273219392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4273219392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.3635063662 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 156005848 ps |
| CPU time | 5.83 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:12 AM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635063662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3635063662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_random.3326049069 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 252994749 ps |
| CPU time | 5.49 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:11 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326049069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3326049069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.1629926188 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 45692834 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629926188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1629926188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.552646957 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 499721059 ps |
| CPU time | 12.03 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:18 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552646957 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.552646957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.3109300688 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 110048768 ps |
| CPU time | 4.26 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109300688 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3109300688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.986471908 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 615981627 ps |
| CPU time | 4.33 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986471908 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.986471908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.303015967 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 393079121 ps |
| CPU time | 3 seconds |
| Started | Oct 12 02:35:54 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303015967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.303015967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.3507528061 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1548075738 ps |
| CPU time | 11.04 seconds |
| Started | Oct 12 02:35:53 AM UTC 24 |
| Finished | Oct 12 02:36:16 AM UTC 24 |
| Peak memory | 217544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507528061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3507528061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1480023488 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2629235081 ps |
| CPU time | 20.95 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:27 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480023488 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1480023488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.2052295569 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 263297837 ps |
| CPU time | 5.77 seconds |
| Started | Oct 12 02:35:54 AM UTC 24 |
| Finished | Oct 12 02:36:11 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052295569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2052295569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.2629737176 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 97168971 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 02:35:54 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629737176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2629737176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.2651436411 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 10716840 ps |
| CPU time | 0.65 seconds |
| Started | Oct 12 02:36:00 AM UTC 24 |
| Finished | Oct 12 02:36:01 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651436411 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2651436411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.3937273778 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 48866326 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:02 AM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937273778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3937273778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.2108986550 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 137584381 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:03 AM UTC 24 |
| Peak memory | 231028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108986550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2108986550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.237938618 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 27187121 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:02 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237938618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.237938618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.442411531 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 74592344 ps |
| CPU time | 3 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:03 AM UTC 24 |
| Peak memory | 217280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442411531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.442411531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_random.121898057 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 31931789 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 02:35:57 AM UTC 24 |
| Finished | Oct 12 02:36:03 AM UTC 24 |
| Peak memory | 223796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121898057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.121898057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.1342278938 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 84974958 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342278938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1342278938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.619656815 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 90873516 ps |
| CPU time | 4.04 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:11 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619656815 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.619656815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.363296412 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 951863501 ps |
| CPU time | 5.5 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:15 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363296412 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.363296412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.3465498555 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 88232452 ps |
| CPU time | 2.95 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465498555 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3465498555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.3227102552 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 142329975 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:02 AM UTC 24 |
| Peak memory | 217328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227102552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3227102552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.2719517253 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 399411961 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 02:35:55 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719517253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2719517253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.1584945316 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 860798336 ps |
| CPU time | 14.88 seconds |
| Started | Oct 12 02:36:00 AM UTC 24 |
| Finished | Oct 12 02:36:16 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1584945316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymg r_stress_all_with_rand_reset.1584945316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.1190866046 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 136088752 ps |
| CPU time | 5 seconds |
| Started | Oct 12 02:35:58 AM UTC 24 |
| Finished | Oct 12 02:36:05 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190866046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1190866046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.2990486655 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 159893033 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 02:36:00 AM UTC 24 |
| Finished | Oct 12 02:36:04 AM UTC 24 |
| Peak memory | 219896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990486655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2990486655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2635735964 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 16427257 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 02:36:06 AM UTC 24 |
| Finished | Oct 12 02:36:11 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635735964 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2635735964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.2154727976 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 63430892 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154727976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2154727976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.724887433 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 16638638 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:36:07 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724887433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.724887433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.1574923515 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 139732853 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 225324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574923515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1574923515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.2324321219 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 104266661 ps |
| CPU time | 4.78 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:36:11 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324321219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2324321219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.3737376395 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 80593372 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737376395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3737376395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_random.374592846 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 217798939 ps |
| CPU time | 4.04 seconds |
| Started | Oct 12 02:36:03 AM UTC 24 |
| Finished | Oct 12 02:36:10 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374592846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.374592846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.655119295 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 112493771 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 02:36:01 AM UTC 24 |
| Finished | Oct 12 02:36:44 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655119295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.655119295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2077817222 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 210218578 ps |
| CPU time | 5.73 seconds |
| Started | Oct 12 02:36:02 AM UTC 24 |
| Finished | Oct 12 02:36:12 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077817222 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2077817222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.2508758909 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 872325360 ps |
| CPU time | 24.27 seconds |
| Started | Oct 12 02:36:03 AM UTC 24 |
| Finished | Oct 12 02:36:30 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508758909 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2508758909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.2216755870 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 45286521 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 02:36:05 AM UTC 24 |
| Finished | Oct 12 02:36:08 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216755870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2216755870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.2588708225 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 204332513 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 02:36:00 AM UTC 24 |
| Finished | Oct 12 02:36:03 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588708225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2588708225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.61132247 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 6476601684 ps |
| CPU time | 62.42 seconds |
| Started | Oct 12 02:36:05 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61132247 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.61132247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.731719416 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 25901300958 ps |
| CPU time | 66.57 seconds |
| Started | Oct 12 02:36:04 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731719416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.731719416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.3194338841 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 83535784 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:36:05 AM UTC 24 |
| Finished | Oct 12 02:36:09 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194338841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3194338841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.1036719176 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 442359332 ps |
| CPU time | 5 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:15 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036719176 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1036719176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.3496059211 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 36789555 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:36:10 AM UTC 24 |
| Finished | Oct 12 02:36:12 AM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496059211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3496059211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.3434207048 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 241413321 ps |
| CPU time | 5.24 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:16 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434207048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3434207048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.1834095507 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 130000893 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:13 AM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834095507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1834095507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.3133075966 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 225538992 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:13 AM UTC 24 |
| Peak memory | 222084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133075966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3133075966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_random.1069295057 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 766269282 ps |
| CPU time | 4.35 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:15 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069295057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1069295057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2242276161 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 323566808 ps |
| CPU time | 4.8 seconds |
| Started | Oct 12 02:36:08 AM UTC 24 |
| Finished | Oct 12 02:36:21 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242276161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2242276161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.1513802753 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 803985319 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:15 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513802753 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1513802753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.3140447853 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 294684259 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 02:36:08 AM UTC 24 |
| Finished | Oct 12 02:36:18 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140447853 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3140447853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.2529646155 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 296670190 ps |
| CPU time | 2.85 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:13 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529646155 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2529646155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1811068175 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 16956412 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:28 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811068175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1811068175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.1488167540 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 255056829 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:36:06 AM UTC 24 |
| Finished | Oct 12 02:36:13 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488167540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1488167540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.117304985 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2560706748 ps |
| CPU time | 37.84 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:37:04 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117304985 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.117304985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.82971861 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1620708287 ps |
| CPU time | 16.07 seconds |
| Started | Oct 12 02:36:09 AM UTC 24 |
| Finished | Oct 12 02:36:27 AM UTC 24 |
| Peak memory | 227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82971861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.82971861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.615584828 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 282810587 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:28 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615584828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.615584828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.218974014 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 9317696 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 02:36:13 AM UTC 24 |
| Finished | Oct 12 02:36:39 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218974014 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.218974014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.594984686 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 70655074 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:33 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594984686 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.594984686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.1401341196 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 80816338 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401341196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1401341196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.3771068038 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 149931678 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:32 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771068038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3771068038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.340755697 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 31929736 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340755697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.340755697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.2699576263 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 34608989 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 223812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699576263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2699576263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.681319533 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 327497636 ps |
| CPU time | 3.72 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:34 AM UTC 24 |
| Peak memory | 219700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681319533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.681319533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_random.2485094990 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 482937926 ps |
| CPU time | 4.48 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:35 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485094990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2485094990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.253265036 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 346519381 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:33 AM UTC 24 |
| Peak memory | 215436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253265036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.253265036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.2209311622 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 57212014 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:33 AM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209311622 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2209311622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.3122494584 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2782940350 ps |
| CPU time | 24.03 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:51 AM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122494584 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3122494584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.818324178 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 216457923 ps |
| CPU time | 4.81 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:35 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818324178 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.818324178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.570160753 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 79557140 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:32 AM UTC 24 |
| Peak memory | 217292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570160753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.570160753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.1463970815 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 702350586 ps |
| CPU time | 9.86 seconds |
| Started | Oct 12 02:36:13 AM UTC 24 |
| Finished | Oct 12 02:36:48 AM UTC 24 |
| Peak memory | 231984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1463970815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.1463970815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.935640312 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1089929064 ps |
| CPU time | 7.51 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:45 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935640312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.935640312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.4091683553 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 108898662 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:36:12 AM UTC 24 |
| Finished | Oct 12 02:36:32 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091683553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4091683553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.2351077275 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 17189297 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 02:36:17 AM UTC 24 |
| Finished | Oct 12 02:36:26 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351077275 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2351077275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.879534527 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 40583261 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:18 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879534527 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.879534527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.2194727108 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 186352280 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 02:36:16 AM UTC 24 |
| Finished | Oct 12 02:36:24 AM UTC 24 |
| Peak memory | 232296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194727108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2194727108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.3628924462 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 202188098 ps |
| CPU time | 5.21 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:21 AM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628924462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3628924462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.3067275645 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 127152496 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:36:16 AM UTC 24 |
| Finished | Oct 12 02:36:22 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067275645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3067275645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.1039925474 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 259786032 ps |
| CPU time | 5.05 seconds |
| Started | Oct 12 02:36:16 AM UTC 24 |
| Finished | Oct 12 02:36:25 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039925474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1039925474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.716939847 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 535441562 ps |
| CPU time | 3.51 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:19 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716939847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.716939847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_random.3664202028 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 132351490 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:20 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664202028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3664202028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.4161847180 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 2594912212 ps |
| CPU time | 21.68 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:37 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161847180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4161847180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.4221518906 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1677355700 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:21 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221518906 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4221518906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.3286218569 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1171761067 ps |
| CPU time | 13.74 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:29 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286218569 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3286218569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.2836377312 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 72001418 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:18 AM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836377312 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2836377312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.956724419 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 411858584 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 02:36:16 AM UTC 24 |
| Finished | Oct 12 02:36:23 AM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956724419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.956724419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.2164504014 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 756342182 ps |
| CPU time | 15 seconds |
| Started | Oct 12 02:36:14 AM UTC 24 |
| Finished | Oct 12 02:36:30 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164504014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2164504014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.2745315922 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 628053371 ps |
| CPU time | 10.93 seconds |
| Started | Oct 12 02:36:17 AM UTC 24 |
| Finished | Oct 12 02:36:36 AM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745315922 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2745315922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.401373700 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 325634081 ps |
| CPU time | 5.84 seconds |
| Started | Oct 12 02:36:16 AM UTC 24 |
| Finished | Oct 12 02:36:26 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401373700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.401373700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.1034343100 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 142535386 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:36:16 AM UTC 24 |
| Finished | Oct 12 02:36:23 AM UTC 24 |
| Peak memory | 219832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034343100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1034343100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.1768631017 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 464467953 ps |
| CPU time | 4.22 seconds |
| Started | Oct 12 02:33:42 AM UTC 24 |
| Finished | Oct 12 02:33:47 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768631017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1768631017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.737986243 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 411620517 ps |
| CPU time | 5.07 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:49 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737986243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.737986243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_random.3216122547 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 171633706 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 02:33:41 AM UTC 24 |
| Finished | Oct 12 02:33:47 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216122547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3216122547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.395341639 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1115437655 ps |
| CPU time | 5.96 seconds |
| Started | Oct 12 02:33:45 AM UTC 24 |
| Finished | Oct 12 02:33:52 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395341639 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.395341639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.2781927240 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 37266309 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 02:33:40 AM UTC 24 |
| Finished | Oct 12 02:33:43 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781927240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2781927240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.1908359280 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 162622485 ps |
| CPU time | 6.64 seconds |
| Started | Oct 12 02:33:41 AM UTC 24 |
| Finished | Oct 12 02:33:49 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908359280 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1908359280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.2584190541 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 146118542 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 02:33:40 AM UTC 24 |
| Finished | Oct 12 02:33:44 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584190541 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2584190541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.1845680120 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 71935578 ps |
| CPU time | 3.75 seconds |
| Started | Oct 12 02:33:41 AM UTC 24 |
| Finished | Oct 12 02:33:46 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845680120 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1845680120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.3153148566 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 529017702 ps |
| CPU time | 9.46 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:54 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153148566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3153148566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.1900941705 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 49756424 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 02:33:39 AM UTC 24 |
| Finished | Oct 12 02:33:43 AM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900941705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1900941705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.1116309397 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 207823381 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:49 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116309397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1116309397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.3536843617 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 41018138 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 02:33:43 AM UTC 24 |
| Finished | Oct 12 02:33:47 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536843617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3536843617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.2758415687 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 31143947 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 02:36:27 AM UTC 24 |
| Finished | Oct 12 02:36:36 AM UTC 24 |
| Peak memory | 213152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758415687 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2758415687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.3710190745 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 59389452 ps |
| CPU time | 3.59 seconds |
| Started | Oct 12 02:36:21 AM UTC 24 |
| Finished | Oct 12 02:36:29 AM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710190745 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3710190745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.210180766 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 32670302 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:36:23 AM UTC 24 |
| Finished | Oct 12 02:36:27 AM UTC 24 |
| Peak memory | 228992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210180766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.210180766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.1627375239 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 115371627 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:36:21 AM UTC 24 |
| Finished | Oct 12 02:36:27 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627375239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1627375239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.3062026662 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 632359171 ps |
| CPU time | 2.65 seconds |
| Started | Oct 12 02:36:22 AM UTC 24 |
| Finished | Oct 12 02:36:32 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062026662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3062026662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.4045043322 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 138942766 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 02:36:22 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045043322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4045043322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.2291557211 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 175941204 ps |
| CPU time | 2.69 seconds |
| Started | Oct 12 02:36:21 AM UTC 24 |
| Finished | Oct 12 02:36:28 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291557211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2291557211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_random.3624659408 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 515587610 ps |
| CPU time | 6.55 seconds |
| Started | Oct 12 02:36:20 AM UTC 24 |
| Finished | Oct 12 02:36:48 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624659408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3624659408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.1247144034 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 51433463 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:36:18 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247144034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1247144034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.393103638 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 24706571 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:36:19 AM UTC 24 |
| Finished | Oct 12 02:36:32 AM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393103638 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.393103638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.2658304913 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 320157681 ps |
| CPU time | 3.72 seconds |
| Started | Oct 12 02:36:19 AM UTC 24 |
| Finished | Oct 12 02:36:42 AM UTC 24 |
| Peak memory | 217712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658304913 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2658304913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.1191098756 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 199585315 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 02:36:20 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191098756 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1191098756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.685929146 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 159800079 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 02:36:24 AM UTC 24 |
| Finished | Oct 12 02:36:28 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685929146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.685929146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.2133568745 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 32277311 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 02:36:18 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133568745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2133568745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.645977838 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4176120606 ps |
| CPU time | 32.38 seconds |
| Started | Oct 12 02:36:25 AM UTC 24 |
| Finished | Oct 12 02:36:58 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645977838 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.645977838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.3858044602 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 679141978 ps |
| CPU time | 12.12 seconds |
| Started | Oct 12 02:36:26 AM UTC 24 |
| Finished | Oct 12 02:36:49 AM UTC 24 |
| Peak memory | 231900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3858044602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.3858044602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.1189261282 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1361845802 ps |
| CPU time | 27.86 seconds |
| Started | Oct 12 02:36:21 AM UTC 24 |
| Finished | Oct 12 02:36:53 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189261282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1189261282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.3438593711 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 268425118 ps |
| CPU time | 4.07 seconds |
| Started | Oct 12 02:36:24 AM UTC 24 |
| Finished | Oct 12 02:36:30 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438593711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3438593711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.1044752604 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 15714241 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 02:36:31 AM UTC 24 |
| Finished | Oct 12 02:36:36 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044752604 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1044752604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.481103288 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 222094702 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 02:36:30 AM UTC 24 |
| Finished | Oct 12 02:36:45 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481103288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.481103288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.1687242170 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 198823456 ps |
| CPU time | 2.72 seconds |
| Started | Oct 12 02:36:29 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687242170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1687242170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.3219345159 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 264441285 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:36:30 AM UTC 24 |
| Finished | Oct 12 02:36:44 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219345159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3219345159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.2015949953 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 65189604 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 02:36:30 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015949953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2015949953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.1611630380 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 78345703 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 02:36:29 AM UTC 24 |
| Finished | Oct 12 02:36:42 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611630380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1611630380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_random.943461090 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 133925778 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 02:36:29 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943461090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.943461090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.600701938 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 76532622 ps |
| CPU time | 3.38 seconds |
| Started | Oct 12 02:36:28 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600701938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.600701938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.3884017593 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 96914699 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 02:36:29 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884017593 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3884017593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.2563982904 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 65567306 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:36:28 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563982904 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2563982904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.3058428651 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 223915708 ps |
| CPU time | 5.51 seconds |
| Started | Oct 12 02:36:29 AM UTC 24 |
| Finished | Oct 12 02:36:43 AM UTC 24 |
| Peak memory | 217432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058428651 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3058428651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.785516471 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 815057638 ps |
| CPU time | 4.39 seconds |
| Started | Oct 12 02:36:30 AM UTC 24 |
| Finished | Oct 12 02:36:46 AM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785516471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.785516471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.3124187715 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 84025202 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 02:36:27 AM UTC 24 |
| Finished | Oct 12 02:36:38 AM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124187715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3124187715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.1359003756 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1412420508 ps |
| CPU time | 9.68 seconds |
| Started | Oct 12 02:36:31 AM UTC 24 |
| Finished | Oct 12 02:36:45 AM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359003756 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1359003756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.1479882307 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 484463022 ps |
| CPU time | 15.23 seconds |
| Started | Oct 12 02:36:31 AM UTC 24 |
| Finished | Oct 12 02:36:51 AM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1479882307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymg r_stress_all_with_rand_reset.1479882307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.2905001029 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4374290551 ps |
| CPU time | 23.23 seconds |
| Started | Oct 12 02:36:30 AM UTC 24 |
| Finished | Oct 12 02:37:05 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905001029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2905001029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.822526380 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 58344775 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 02:36:39 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822526380 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.822526380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.664249631 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 394345615 ps |
| CPU time | 4.02 seconds |
| Started | Oct 12 02:36:35 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664249631 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.664249631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2829039755 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 375329463 ps |
| CPU time | 3.31 seconds |
| Started | Oct 12 02:36:37 AM UTC 24 |
| Finished | Oct 12 02:36:41 AM UTC 24 |
| Peak memory | 230576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829039755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2829039755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.588405935 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 326636593 ps |
| CPU time | 7.65 seconds |
| Started | Oct 12 02:36:35 AM UTC 24 |
| Finished | Oct 12 02:36:44 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588405935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.588405935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.1553965262 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 249758910 ps |
| CPU time | 2.4 seconds |
| Started | Oct 12 02:36:37 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 213560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553965262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1553965262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.2646771772 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 101911898 ps |
| CPU time | 4 seconds |
| Started | Oct 12 02:36:37 AM UTC 24 |
| Finished | Oct 12 02:36:42 AM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646771772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2646771772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.110882951 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 338283300 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 02:36:35 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110882951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.110882951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_random.2371066672 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 377039517 ps |
| CPU time | 5.75 seconds |
| Started | Oct 12 02:36:35 AM UTC 24 |
| Finished | Oct 12 02:36:42 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371066672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2371066672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.737307230 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 146950705 ps |
| CPU time | 2.16 seconds |
| Started | Oct 12 02:36:33 AM UTC 24 |
| Finished | Oct 12 02:36:39 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737307230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.737307230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.3465088185 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 112652604 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:36:33 AM UTC 24 |
| Finished | Oct 12 02:36:39 AM UTC 24 |
| Peak memory | 212908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465088185 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3465088185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.2728023214 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 210406546 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 02:36:33 AM UTC 24 |
| Finished | Oct 12 02:36:42 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728023214 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2728023214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.1057468350 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 108998544 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 02:36:33 AM UTC 24 |
| Finished | Oct 12 02:36:39 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057468350 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1057468350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.432226638 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 36179310 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 02:36:37 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432226638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.432226638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.456339223 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 616442336 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 02:36:33 AM UTC 24 |
| Finished | Oct 12 02:36:39 AM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456339223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.456339223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.850756389 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 386437463 ps |
| CPU time | 14.39 seconds |
| Started | Oct 12 02:36:39 AM UTC 24 |
| Finished | Oct 12 02:36:55 AM UTC 24 |
| Peak memory | 232032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=850756389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr _stress_all_with_rand_reset.850756389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.3207097684 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 877313288 ps |
| CPU time | 6.06 seconds |
| Started | Oct 12 02:36:37 AM UTC 24 |
| Finished | Oct 12 02:36:44 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207097684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3207097684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.1464182417 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 59263295 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 02:36:37 AM UTC 24 |
| Finished | Oct 12 02:36:40 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464182417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1464182417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.3549306112 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 178355189 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 02:36:42 AM UTC 24 |
| Finished | Oct 12 02:36:46 AM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549306112 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3549306112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.3556557420 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 740482619 ps |
| CPU time | 4.1 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:49 AM UTC 24 |
| Peak memory | 232048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556557420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3556557420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.2059359974 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1218200209 ps |
| CPU time | 9.54 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:55 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059359974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2059359974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.2606902151 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 68814922 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:48 AM UTC 24 |
| Peak memory | 219628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606902151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2606902151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.1739464534 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 81394919 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:47 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739464534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1739464534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_random.3962619711 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 296285956 ps |
| CPU time | 8.3 seconds |
| Started | Oct 12 02:36:42 AM UTC 24 |
| Finished | Oct 12 02:36:51 AM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962619711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3962619711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.3372333058 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 512761949 ps |
| CPU time | 5.56 seconds |
| Started | Oct 12 02:36:40 AM UTC 24 |
| Finished | Oct 12 02:36:46 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372333058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3372333058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.1963723065 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 581159151 ps |
| CPU time | 4.34 seconds |
| Started | Oct 12 02:36:40 AM UTC 24 |
| Finished | Oct 12 02:36:45 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963723065 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1963723065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.1150976226 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 301023261 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 02:36:40 AM UTC 24 |
| Finished | Oct 12 02:36:43 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150976226 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1150976226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.4230558888 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 242459862 ps |
| CPU time | 4.75 seconds |
| Started | Oct 12 02:36:40 AM UTC 24 |
| Finished | Oct 12 02:36:45 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230558888 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4230558888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.10449816 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 24192685 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:47 AM UTC 24 |
| Peak memory | 224128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10449816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.10449816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.3592706397 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 534651224 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 02:36:39 AM UTC 24 |
| Finished | Oct 12 02:36:43 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592706397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3592706397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.2628649825 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 24881575094 ps |
| CPU time | 47.64 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:37:33 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628649825 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2628649825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.815758765 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 207451055 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:48 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815758765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.815758765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.756027562 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1287497873 ps |
| CPU time | 7.77 seconds |
| Started | Oct 12 02:36:43 AM UTC 24 |
| Finished | Oct 12 02:36:53 AM UTC 24 |
| Peak memory | 219832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756027562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.756027562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.2171573196 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 118349343 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:11 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171573196 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2171573196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.1245389579 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2542813214 ps |
| CPU time | 37.5 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:48 AM UTC 24 |
| Peak memory | 232108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245389579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1245389579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.703629853 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 100371891 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:36:45 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703629853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.703629853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.3651205563 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 85681990 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:11 AM UTC 24 |
| Peak memory | 221896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651205563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3651205563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.2141266338 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 311885205 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 02:36:45 AM UTC 24 |
| Finished | Oct 12 02:37:10 AM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141266338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2141266338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1815839286 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 594528933 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 227896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815839286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1815839286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all_with_rand_reset.2510546917 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2881581766 ps |
| CPU time | 17.01 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:27 AM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2510546917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymg r_stress_all_with_rand_reset.2510546917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.1597775242 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1063692134 ps |
| CPU time | 4.34 seconds |
| Started | Oct 12 02:36:45 AM UTC 24 |
| Finished | Oct 12 02:37:11 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597775242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1597775242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.4265376687 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 110925846 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265376687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4265376687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.1611070525 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 15371233 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 02:36:49 AM UTC 24 |
| Finished | Oct 12 02:37:01 AM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611070525 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1611070525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.489005967 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 146094884 ps |
| CPU time | 6.85 seconds |
| Started | Oct 12 02:36:47 AM UTC 24 |
| Finished | Oct 12 02:37:12 AM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489005967 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.489005967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.2784878920 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 535604704 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 02:36:47 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784878920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2784878920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.3728972178 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 120675267 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 02:36:48 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728972178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3728972178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.1061756636 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 72530194 ps |
| CPU time | 3.03 seconds |
| Started | Oct 12 02:36:48 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061756636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1061756636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.184702582 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 63910546 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 02:36:47 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 212904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184702582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.184702582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_random.2206453425 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3950916893 ps |
| CPU time | 11.48 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:02 AM UTC 24 |
| Peak memory | 223860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206453425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2206453425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.3089703596 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 54328455 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:03 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089703596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3089703596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.1014261586 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 123985275 ps |
| CPU time | 2.77 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:36:53 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014261586 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1014261586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.1319339787 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 378634453 ps |
| CPU time | 3.83 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:36:54 AM UTC 24 |
| Peak memory | 217564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319339787 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1319339787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.2995386786 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 54687696 ps |
| CPU time | 2 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:36:52 AM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995386786 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2995386786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.3633550998 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 525118360 ps |
| CPU time | 3.2 seconds |
| Started | Oct 12 02:36:48 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633550998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3633550998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.804079439 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 137924784 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 02:36:46 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804079439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.804079439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.4246331524 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 618820837 ps |
| CPU time | 8.87 seconds |
| Started | Oct 12 02:36:49 AM UTC 24 |
| Finished | Oct 12 02:36:59 AM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4246331524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymg r_stress_all_with_rand_reset.4246331524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.1225577301 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 964016622 ps |
| CPU time | 26.35 seconds |
| Started | Oct 12 02:36:48 AM UTC 24 |
| Finished | Oct 12 02:37:31 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225577301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1225577301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.3309192163 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 442616199 ps |
| CPU time | 2.26 seconds |
| Started | Oct 12 02:36:48 AM UTC 24 |
| Finished | Oct 12 02:37:07 AM UTC 24 |
| Peak memory | 217248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309192163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3309192163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.3248171868 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 18110878 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 02:36:58 AM UTC 24 |
| Finished | Oct 12 02:37:05 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248171868 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3248171868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.2127631223 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 34202545 ps |
| CPU time | 2.45 seconds |
| Started | Oct 12 02:36:52 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127631223 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2127631223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.696755868 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 806475841 ps |
| CPU time | 12.12 seconds |
| Started | Oct 12 02:36:54 AM UTC 24 |
| Finished | Oct 12 02:37:07 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696755868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.696755868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.2121670654 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 26055535 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:36:52 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121670654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2121670654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.199251893 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 45903129 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 02:36:53 AM UTC 24 |
| Finished | Oct 12 02:36:57 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199251893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.199251893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.1691940014 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 581769868 ps |
| CPU time | 3.64 seconds |
| Started | Oct 12 02:36:54 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691940014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1691940014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.3391932090 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 346387986 ps |
| CPU time | 3.54 seconds |
| Started | Oct 12 02:36:52 AM UTC 24 |
| Finished | Oct 12 02:37:10 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391932090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3391932090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_random.327459930 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 73593875 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 02:36:52 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327459930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.327459930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.2914623002 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 7200685312 ps |
| CPU time | 40.33 seconds |
| Started | Oct 12 02:36:49 AM UTC 24 |
| Finished | Oct 12 02:37:41 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914623002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2914623002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.2872897474 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 64379651 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:36:50 AM UTC 24 |
| Finished | Oct 12 02:37:04 AM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872897474 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2872897474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.1573678974 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 923468896 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 02:36:49 AM UTC 24 |
| Finished | Oct 12 02:37:03 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573678974 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1573678974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.3178156538 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 4250949706 ps |
| CPU time | 6.07 seconds |
| Started | Oct 12 02:36:50 AM UTC 24 |
| Finished | Oct 12 02:37:11 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178156538 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3178156538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.1637224148 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 276101267 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 02:36:54 AM UTC 24 |
| Finished | Oct 12 02:36:58 AM UTC 24 |
| Peak memory | 217524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637224148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1637224148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.3376049490 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 90269157 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 02:36:49 AM UTC 24 |
| Finished | Oct 12 02:37:04 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376049490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3376049490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.1037714868 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 336502367 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 02:36:55 AM UTC 24 |
| Finished | Oct 12 02:37:10 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037714868 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1037714868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.2346456124 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 54526089 ps |
| CPU time | 2.85 seconds |
| Started | Oct 12 02:36:52 AM UTC 24 |
| Finished | Oct 12 02:37:03 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346456124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2346456124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.748050580 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1074755113 ps |
| CPU time | 4.08 seconds |
| Started | Oct 12 02:36:55 AM UTC 24 |
| Finished | Oct 12 02:37:11 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748050580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.748050580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.3265206729 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 47818001 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 02:37:06 AM UTC 24 |
| Finished | Oct 12 02:37:12 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265206729 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3265206729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.2245769192 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 197205417 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 02:37:03 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245769192 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2245769192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.1027915779 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 260305636 ps |
| CPU time | 6.45 seconds |
| Started | Oct 12 02:37:05 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027915779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1027915779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.3268282064 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 44302804 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:37:03 AM UTC 24 |
| Finished | Oct 12 02:37:07 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268282064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3268282064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.896126932 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1923434319 ps |
| CPU time | 24.93 seconds |
| Started | Oct 12 02:37:04 AM UTC 24 |
| Finished | Oct 12 02:37:31 AM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896126932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.896126932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.3352472220 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 163133231 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 02:37:05 AM UTC 24 |
| Finished | Oct 12 02:37:10 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352472220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3352472220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.3435504707 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 306115245 ps |
| CPU time | 6.71 seconds |
| Started | Oct 12 02:37:03 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435504707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3435504707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_random.4020384621 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 47529099 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 02:37:03 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020384621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4020384621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.1451936144 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1247238780 ps |
| CPU time | 28.78 seconds |
| Started | Oct 12 02:37:00 AM UTC 24 |
| Finished | Oct 12 02:37:30 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451936144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1451936144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.1689385559 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 452089335 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 02:37:02 AM UTC 24 |
| Finished | Oct 12 02:37:10 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689385559 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1689385559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.2528945063 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 90242305 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:37:00 AM UTC 24 |
| Finished | Oct 12 02:37:02 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528945063 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2528945063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.264891559 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 94582220 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 02:37:02 AM UTC 24 |
| Finished | Oct 12 02:37:08 AM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264891559 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.264891559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.1474834032 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 358232828 ps |
| CPU time | 5.82 seconds |
| Started | Oct 12 02:37:05 AM UTC 24 |
| Finished | Oct 12 02:37:12 AM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474834032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1474834032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.3402068611 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 124116405 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:36:59 AM UTC 24 |
| Finished | Oct 12 02:37:03 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402068611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3402068611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.1912432396 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 7231543915 ps |
| CPU time | 45.06 seconds |
| Started | Oct 12 02:37:06 AM UTC 24 |
| Finished | Oct 12 02:37:56 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912432396 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1912432396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.1285440053 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 1381024038 ps |
| CPU time | 10.13 seconds |
| Started | Oct 12 02:37:06 AM UTC 24 |
| Finished | Oct 12 02:37:21 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1285440053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.1285440053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.3236046145 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 79024189 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 02:37:04 AM UTC 24 |
| Finished | Oct 12 02:37:09 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236046145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3236046145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.3237854659 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 121105976 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:37:06 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237854659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3237854659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.1797103290 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 47737956 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:22 AM UTC 24 |
| Peak memory | 211672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797103290 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1797103290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.3713630808 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 32804874 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713630808 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3713630808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.1552381904 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 195915044 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:12 AM UTC 24 |
| Peak memory | 223428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552381904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1552381904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.4216014748 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 128782384 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:13 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216014748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4216014748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.2118563056 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 436374652 ps |
| CPU time | 4.2 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:15 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118563056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2118563056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.4218584289 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 454265077 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218584289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4218584289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.3347796003 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 116133468 ps |
| CPU time | 3.11 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 217596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347796003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3347796003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_random.1045291535 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 72631132 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 02:37:07 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 217508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045291535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1045291535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.218536155 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 380478299 ps |
| CPU time | 3.06 seconds |
| Started | Oct 12 02:37:07 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 217584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218536155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.218536155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.1898116715 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 249527794 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 02:37:07 AM UTC 24 |
| Finished | Oct 12 02:37:15 AM UTC 24 |
| Peak memory | 217808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898116715 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1898116715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.1095567241 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 452037751 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 02:37:07 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095567241 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1095567241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.1386175740 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 155628963 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 02:37:07 AM UTC 24 |
| Finished | Oct 12 02:37:25 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386175740 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1386175740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.1116246231 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 920733453 ps |
| CPU time | 5.69 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:16 AM UTC 24 |
| Peak memory | 227960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116246231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1116246231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.2966700742 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 56990417 ps |
| CPU time | 2.62 seconds |
| Started | Oct 12 02:37:07 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966700742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2966700742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.2254778211 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 15555788048 ps |
| CPU time | 80.66 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:38:43 AM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254778211 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2254778211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.2893152644 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 308116722 ps |
| CPU time | 3.6 seconds |
| Started | Oct 12 02:37:08 AM UTC 24 |
| Finished | Oct 12 02:37:14 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893152644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2893152644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.65541507 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 64971934 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:23 AM UTC 24 |
| Peak memory | 217244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65541507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.65541507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.170064653 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 11331397 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:21 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170064653 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.170064653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3442105615 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 52391946 ps |
| CPU time | 4.57 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:27 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442105615 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3442105615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.1676047677 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 149011026 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:22 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676047677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1676047677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.4212301360 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1457996411 ps |
| CPU time | 9.57 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:32 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212301360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4212301360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.3007253705 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 130287589 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:20 AM UTC 24 |
| Peak memory | 223800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007253705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3007253705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.3235512508 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 230216822 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:22 AM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235512508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3235512508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.2192707021 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2982083928 ps |
| CPU time | 18.27 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:36 AM UTC 24 |
| Peak memory | 230208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192707021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2192707021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_random.3075838347 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 64277087 ps |
| CPU time | 3.18 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:18 AM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075838347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3075838347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.2164316801 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 34350938 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:24 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164316801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2164316801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.1165026028 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 605364814 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:17 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165026028 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1165026028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.3859714401 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 87199025 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:16 AM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859714401 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3859714401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.2287915329 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3015106214 ps |
| CPU time | 19.84 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:35 AM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287915329 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2287915329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.3670346945 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 91210469 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:20 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670346945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3670346945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.3313851356 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 77941151 ps |
| CPU time | 4.48 seconds |
| Started | Oct 12 02:37:10 AM UTC 24 |
| Finished | Oct 12 02:37:26 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313851356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3313851356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.4065922393 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 6642917540 ps |
| CPU time | 40.92 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:38:02 AM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065922393 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4065922393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.3842888741 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 105945244 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:26 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3842888741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymg r_stress_all_with_rand_reset.3842888741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.2130877015 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 188570164 ps |
| CPU time | 4 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:21 AM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130877015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2130877015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.3691629771 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 83535033 ps |
| CPU time | 3.9 seconds |
| Started | Oct 12 02:37:12 AM UTC 24 |
| Finished | Oct 12 02:37:24 AM UTC 24 |
| Peak memory | 217528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691629771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3691629771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.626285883 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 15958331 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:33:51 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626285883 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.626285883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.3026629386 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 117913213 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:33:50 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026629386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3026629386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.3464167214 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 73378766 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 02:33:48 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464167214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3464167214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.3036718196 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 440229252 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 02:33:50 AM UTC 24 |
| Finished | Oct 12 02:33:56 AM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036718196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3036718196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.2359434750 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 121743713 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 02:33:48 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359434750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2359434750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_random.2308883083 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 126232579 ps |
| CPU time | 3.52 seconds |
| Started | Oct 12 02:33:48 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308883083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2308883083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.1498937853 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 108444736 ps |
| CPU time | 3.64 seconds |
| Started | Oct 12 02:33:45 AM UTC 24 |
| Finished | Oct 12 02:33:49 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498937853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1498937853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.1410552528 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 119033303 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 02:33:47 AM UTC 24 |
| Finished | Oct 12 02:33:51 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410552528 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1410552528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.1692856312 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 723783327 ps |
| CPU time | 10.38 seconds |
| Started | Oct 12 02:33:47 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692856312 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1692856312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.4093671482 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 205569150 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 02:33:50 AM UTC 24 |
| Finished | Oct 12 02:33:54 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093671482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4093671482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1532812873 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 213477814 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 02:33:45 AM UTC 24 |
| Finished | Oct 12 02:33:49 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532812873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1532812873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.2589230231 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 677818716 ps |
| CPU time | 10.12 seconds |
| Started | Oct 12 02:33:50 AM UTC 24 |
| Finished | Oct 12 02:34:01 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589230231 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2589230231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.799358152 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 811768729 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 02:33:48 AM UTC 24 |
| Finished | Oct 12 02:33:55 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799358152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.799358152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.2729915117 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 266459729 ps |
| CPU time | 3.36 seconds |
| Started | Oct 12 02:33:50 AM UTC 24 |
| Finished | Oct 12 02:33:54 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729915117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2729915117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.2380461556 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 24291888 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:33:55 AM UTC 24 |
| Finished | Oct 12 02:33:58 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380461556 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2380461556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3800397617 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 920754762 ps |
| CPU time | 37.25 seconds |
| Started | Oct 12 02:33:52 AM UTC 24 |
| Finished | Oct 12 02:34:31 AM UTC 24 |
| Peak memory | 225964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800397617 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3800397617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.3154109514 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 43587272 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:33:57 AM UTC 24 |
| Peak memory | 223320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154109514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3154109514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.2395972299 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 40820502 ps |
| CPU time | 3.01 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:33:58 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395972299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2395972299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.3235539425 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 159255284 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235539425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3235539425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.2883451455 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 584622348 ps |
| CPU time | 6.42 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:34:02 AM UTC 24 |
| Peak memory | 231648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883451455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2883451455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.706535091 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 114870212 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:33:58 AM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706535091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.706535091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_random.3138355089 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 309971504 ps |
| CPU time | 4.55 seconds |
| Started | Oct 12 02:33:52 AM UTC 24 |
| Finished | Oct 12 02:33:58 AM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138355089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3138355089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.2498622565 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1561300690 ps |
| CPU time | 6.6 seconds |
| Started | Oct 12 02:33:51 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498622565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2498622565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.713430439 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 74560080 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 02:33:51 AM UTC 24 |
| Finished | Oct 12 02:33:56 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713430439 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.713430439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.3954628799 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2115030312 ps |
| CPU time | 5.91 seconds |
| Started | Oct 12 02:33:51 AM UTC 24 |
| Finished | Oct 12 02:33:58 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954628799 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3954628799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.2151412442 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 684637157 ps |
| CPU time | 16.33 seconds |
| Started | Oct 12 02:33:51 AM UTC 24 |
| Finished | Oct 12 02:34:09 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151412442 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2151412442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.2950311692 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 92078914 ps |
| CPU time | 4.84 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:34:00 AM UTC 24 |
| Peak memory | 217320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950311692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2950311692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.653943665 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 75815014 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 02:33:51 AM UTC 24 |
| Finished | Oct 12 02:33:56 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653943665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.653943665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.589683391 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3350319507 ps |
| CPU time | 24.32 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:34:20 AM UTC 24 |
| Peak memory | 217576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589683391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.589683391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3719996566 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 113574302 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 02:33:54 AM UTC 24 |
| Finished | Oct 12 02:33:59 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719996566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3719996566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.1162029527 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 15267662 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:34:01 AM UTC 24 |
| Finished | Oct 12 02:34:03 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162029527 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1162029527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.620917085 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 39004206 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:33:58 AM UTC 24 |
| Finished | Oct 12 02:34:02 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620917085 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.620917085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.1261217175 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 295303785 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 02:33:58 AM UTC 24 |
| Finished | Oct 12 02:34:03 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261217175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1261217175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.2090477505 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 29126747 ps |
| CPU time | 2.37 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:03 AM UTC 24 |
| Peak memory | 223272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090477505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2090477505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.2918636116 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 238021223 ps |
| CPU time | 3.46 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:04 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918636116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2918636116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.1788668840 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 129104882 ps |
| CPU time | 4.15 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:04 AM UTC 24 |
| Peak memory | 217464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788668840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1788668840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_random.2118606346 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 260187829 ps |
| CPU time | 6.09 seconds |
| Started | Oct 12 02:33:58 AM UTC 24 |
| Finished | Oct 12 02:34:05 AM UTC 24 |
| Peak memory | 219696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118606346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2118606346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.1522046304 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 113294161 ps |
| CPU time | 4.57 seconds |
| Started | Oct 12 02:33:57 AM UTC 24 |
| Finished | Oct 12 02:34:03 AM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522046304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1522046304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.2022565334 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1318185536 ps |
| CPU time | 15.14 seconds |
| Started | Oct 12 02:33:57 AM UTC 24 |
| Finished | Oct 12 02:34:13 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022565334 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2022565334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.654027638 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 65989156 ps |
| CPU time | 3.63 seconds |
| Started | Oct 12 02:33:57 AM UTC 24 |
| Finished | Oct 12 02:34:02 AM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654027638 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.654027638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.4031100247 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 96655033 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 02:33:57 AM UTC 24 |
| Finished | Oct 12 02:34:02 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031100247 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4031100247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.3145303716 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1725624798 ps |
| CPU time | 15.76 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:16 AM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145303716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3145303716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.4125880473 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 193751756 ps |
| CPU time | 4.32 seconds |
| Started | Oct 12 02:33:55 AM UTC 24 |
| Finished | Oct 12 02:34:01 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125880473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4125880473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.21788164 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2611389199 ps |
| CPU time | 17.27 seconds |
| Started | Oct 12 02:34:01 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 223804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21788164 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.21788164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2382432137 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 253063726 ps |
| CPU time | 5.23 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:05 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382432137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2382432137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.3000085844 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 181365661 ps |
| CPU time | 2.37 seconds |
| Started | Oct 12 02:33:59 AM UTC 24 |
| Finished | Oct 12 02:34:03 AM UTC 24 |
| Peak memory | 217784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000085844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3000085844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3468497333 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 9393546 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:34:05 AM UTC 24 |
| Finished | Oct 12 02:34:07 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468497333 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3468497333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.3489396834 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8981522694 ps |
| CPU time | 98.7 seconds |
| Started | Oct 12 02:34:02 AM UTC 24 |
| Finished | Oct 12 02:35:43 AM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489396834 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3489396834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.3654687620 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 110247163 ps |
| CPU time | 5.33 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 219844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654687620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3654687620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.2773862409 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 19661930 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 02:34:02 AM UTC 24 |
| Finished | Oct 12 02:34:05 AM UTC 24 |
| Peak memory | 217324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773862409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2773862409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.2794637524 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 67624041 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:07 AM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794637524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2794637524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.1042831501 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 145933644 ps |
| CPU time | 5.46 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042831501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1042831501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_random.624036716 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 94484153 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 02:34:02 AM UTC 24 |
| Finished | Oct 12 02:34:07 AM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624036716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.624036716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.2164087332 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 94897715 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 02:34:01 AM UTC 24 |
| Finished | Oct 12 02:34:04 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164087332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2164087332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.3819998052 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 51158585 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:34:02 AM UTC 24 |
| Finished | Oct 12 02:34:06 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819998052 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3819998052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.2949455592 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 353769518 ps |
| CPU time | 3 seconds |
| Started | Oct 12 02:34:02 AM UTC 24 |
| Finished | Oct 12 02:34:06 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949455592 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2949455592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.3095672882 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 37765740 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 02:34:02 AM UTC 24 |
| Finished | Oct 12 02:34:06 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095672882 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3095672882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3052656884 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 359026573 ps |
| CPU time | 11.34 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:17 AM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052656884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3052656884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1017562407 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 171012354 ps |
| CPU time | 2.33 seconds |
| Started | Oct 12 02:34:01 AM UTC 24 |
| Finished | Oct 12 02:34:04 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017562407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1017562407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.1245584070 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 13379073237 ps |
| CPU time | 72.57 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:35:18 AM UTC 24 |
| Peak memory | 225780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245584070 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1245584070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.910808654 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 448114405 ps |
| CPU time | 12.24 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:17 AM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910808654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.910808654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.4151682521 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2046784437 ps |
| CPU time | 13.38 seconds |
| Started | Oct 12 02:34:04 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 219832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151682521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4151682521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2716743794 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 60075551 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:34:11 AM UTC 24 |
| Finished | Oct 12 02:34:13 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716743794 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2716743794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.769476493 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 27581347 ps |
| CPU time | 2.41 seconds |
| Started | Oct 12 02:34:07 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769476493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.769476493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.1470754324 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 102866167 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 02:34:08 AM UTC 24 |
| Finished | Oct 12 02:34:12 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470754324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1470754324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.1559204021 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 84364078 ps |
| CPU time | 3.78 seconds |
| Started | Oct 12 02:34:07 AM UTC 24 |
| Finished | Oct 12 02:34:12 AM UTC 24 |
| Peak memory | 217788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559204021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1559204021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_random.2741351502 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 320675324 ps |
| CPU time | 6.81 seconds |
| Started | Oct 12 02:34:07 AM UTC 24 |
| Finished | Oct 12 02:34:15 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741351502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2741351502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.3795347745 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 80089619 ps |
| CPU time | 3.41 seconds |
| Started | Oct 12 02:34:05 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795347745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3795347745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.1661681029 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 71711374 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 02:34:05 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661681029 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1661681029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.383993731 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 80985229 ps |
| CPU time | 3.96 seconds |
| Started | Oct 12 02:34:05 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 215564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383993731 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.383993731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.727075336 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 227850179 ps |
| CPU time | 7.78 seconds |
| Started | Oct 12 02:34:07 AM UTC 24 |
| Finished | Oct 12 02:34:16 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727075336 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.727075336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.4163672437 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 122304736 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 02:34:08 AM UTC 24 |
| Finished | Oct 12 02:34:13 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163672437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.4163672437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.3637272851 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 37376444 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:34:05 AM UTC 24 |
| Finished | Oct 12 02:34:09 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637272851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3637272851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.604093465 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 933418286 ps |
| CPU time | 27.47 seconds |
| Started | Oct 12 02:34:09 AM UTC 24 |
| Finished | Oct 12 02:34:38 AM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604093465 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.604093465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.3304771038 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 590933903 ps |
| CPU time | 10.77 seconds |
| Started | Oct 12 02:34:11 AM UTC 24 |
| Finished | Oct 12 02:34:23 AM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3304771038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr _stress_all_with_rand_reset.3304771038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.4283708011 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 212054904 ps |
| CPU time | 6.05 seconds |
| Started | Oct 12 02:34:07 AM UTC 24 |
| Finished | Oct 12 02:34:14 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283708011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4283708011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |