Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3133161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601536

1

T1

156

T2

144

T3

156

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3324234	1			T1	395		T2	1895		T3	1399
values[0x0]	203760	1			T1	43		T2	46		T3	47
values[0x1]	206703	1			T1	43		T2	31		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2145988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1588709

1

T1

244

T2

721

T3

571

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12914	1			T2	4		T3	7		T4	4
valid_sources[0x01]	12945	1			T2	5		T3	5		T4	10
valid_sources[0x02]	34456	1			T2	7		T3	12		T4	8
valid_sources[0x03]	12613	1			T2	5		T3	10		T4	4
valid_sources[0x04]	15714	1			T2	3		T3	3		T13	2
valid_sources[0x05]	18753	1			T2	5		T3	10		T4	2
valid_sources[0x06]	11883	1			T2	5		T3	6		T13	1
valid_sources[0x07]	13005	1			T2	12		T3	7		T4	3
valid_sources[0x08]	13386	1			T2	8		T3	6		T4	4
valid_sources[0x09]	13580	1			T2	5		T3	10		T4	1
valid_sources[0x0a]	12784	1			T2	9		T3	7		T4	2
valid_sources[0x0b]	12909	1			T2	9		T3	1		T4	6
valid_sources[0x0c]	13089	1			T2	10		T3	3		T4	7
valid_sources[0x0d]	14143	1			T2	14		T3	6		T4	5
valid_sources[0x0e]	12511	1			T2	17		T3	2		T4	5
valid_sources[0x0f]	12281	1			T2	8		T3	3		T4	3
valid_sources[0x10]	12493	1			T2	6		T3	6		T4	3
valid_sources[0x11]	13062	1			T2	12		T3	8		T4	5
valid_sources[0x12]	13174	1			T2	13		T3	12		T4	2
valid_sources[0x13]	12810	1			T2	8		T3	9		T4	10
valid_sources[0x14]	15342	1			T2	11		T3	9		T13	1
valid_sources[0x15]	12409	1			T2	3		T3	2		T4	3
valid_sources[0x16]	12993	1			T2	11		T3	1		T16	3
valid_sources[0x17]	13069	1			T2	11		T3	3		T4	4
valid_sources[0x18]	14073	1			T2	12		T3	5		T4	3
valid_sources[0x19]	12796	1			T2	9		T3	4		T4	1
valid_sources[0x1a]	12852	1			T2	12		T3	2		T4	6
valid_sources[0x1b]	13223	1			T2	4		T3	4		T13	1
valid_sources[0x1c]	15245	1			T2	13		T3	6		T4	4
valid_sources[0x1d]	13002	1			T2	7		T3	8		T4	6
valid_sources[0x1e]	12210	1			T2	10		T3	11		T4	4
valid_sources[0x1f]	14457	1			T2	10		T3	3		T4	1
valid_sources[0x20]	12587	1			T2	8		T3	8		T4	7
valid_sources[0x21]	12751	1			T2	9		T3	7		T4	4
valid_sources[0x22]	17758	1			T2	5		T3	7		T4	3
valid_sources[0x23]	12550	1			T2	6		T3	2		T4	7
valid_sources[0x24]	48002	1			T2	13		T3	9		T4	2
valid_sources[0x25]	19594	1			T2	8		T3	3		T4	5
valid_sources[0x26]	14678	1			T2	2		T3	4		T4	3
valid_sources[0x27]	14967	1			T2	8		T3	3		T4	7
valid_sources[0x28]	13076	1			T2	18		T3	5		T4	2
valid_sources[0x29]	15120	1			T2	12		T3	5		T4	3
valid_sources[0x2a]	12651	1			T2	15		T3	1		T4	11
valid_sources[0x2b]	12751	1			T2	1		T3	5		T4	4
valid_sources[0x2c]	13066	1			T2	10		T3	11		T4	6
valid_sources[0x2d]	12387	1			T2	8		T3	6		T4	3
valid_sources[0x2e]	12570	1			T2	5		T3	2		T4	5
valid_sources[0x2f]	16401	1			T2	12		T3	7		T4	5
valid_sources[0x30]	12498	1			T2	7		T3	7		T16	2
valid_sources[0x31]	12831	1			T2	1		T3	6		T4	2
valid_sources[0x32]	12404	1			T2	9		T3	3		T4	10
valid_sources[0x33]	13062	1			T2	3		T3	7		T4	3
valid_sources[0x34]	12763	1			T2	7		T3	5		T4	5
valid_sources[0x35]	12543	1			T2	12		T3	11		T4	8
valid_sources[0x36]	12228	1			T2	7		T3	4		T4	3
valid_sources[0x37]	13690	1			T2	10		T3	3		T4	4
valid_sources[0x38]	13442	1			T2	3		T3	2		T4	4
valid_sources[0x39]	13387	1			T2	12		T3	6		T4	4
valid_sources[0x3a]	15715	1			T2	6		T3	5		T4	9
valid_sources[0x3b]	19592	1			T2	8		T3	2		T4	10
valid_sources[0x3c]	13842	1			T2	12		T3	4		T4	3
valid_sources[0x3d]	13586	1			T2	10		T3	7		T4	7
valid_sources[0x3e]	12955	1			T2	9		T3	12		T4	4
valid_sources[0x3f]	14364	1			T2	9		T3	6		T4	4
valid_sources[0x40]	23356	1			T2	5		T3	2		T4	4
valid_sources[0x41]	14273	1			T3	6		T4	9		T16	1
valid_sources[0x42]	12756	1			T2	5		T3	4		T4	10
valid_sources[0x43]	13476	1			T2	14		T3	2		T4	8
valid_sources[0x44]	12469	1			T2	10		T3	4		T4	6
valid_sources[0x45]	13311	1			T2	14		T3	2		T4	6
valid_sources[0x46]	12556	1			T2	16		T3	4		T4	2
valid_sources[0x47]	13022	1			T2	1		T3	9		T4	2
valid_sources[0x48]	13007	1			T2	3		T3	3		T4	7
valid_sources[0x49]	12699	1			T2	9		T3	5		T4	2
valid_sources[0x4a]	12992	1			T2	6		T3	7		T4	4
valid_sources[0x4b]	12857	1			T2	7		T3	2		T4	3
valid_sources[0x4c]	13862	1			T2	5		T3	6		T4	5
valid_sources[0x4d]	16446	1			T2	9		T3	4		T4	5
valid_sources[0x4e]	18586	1			T2	3		T3	3		T4	4
valid_sources[0x4f]	12399	1			T2	14		T3	4		T4	10
valid_sources[0x50]	15488	1			T2	7		T3	6		T4	9
valid_sources[0x51]	14256	1			T2	3		T4	6		T16	1
valid_sources[0x52]	12396	1			T2	4		T3	10		T4	4
valid_sources[0x53]	12122	1			T2	5		T3	6		T4	5
valid_sources[0x54]	17883	1			T2	3		T3	6		T4	5
valid_sources[0x55]	13402	1			T2	5		T3	9		T4	5
valid_sources[0x56]	16355	1			T2	2		T3	12		T4	1
valid_sources[0x57]	12114	1			T2	8		T3	4		T4	6
valid_sources[0x58]	13628	1			T2	10		T3	5		T4	8
valid_sources[0x59]	17027	1			T2	8		T3	5		T4	6
valid_sources[0x5a]	16418	1			T2	9		T3	10		T4	8
valid_sources[0x5b]	13575	1			T2	14		T3	9		T16	3
valid_sources[0x5c]	12879	1			T2	4		T3	6		T4	1
valid_sources[0x5d]	13685	1			T3	2		T4	7		T35	4
valid_sources[0x5e]	16891	1			T2	9		T3	10		T13	1
valid_sources[0x5f]	13020	1			T2	4		T3	13		T4	4
valid_sources[0x60]	13783	1			T2	15		T3	11		T4	9
valid_sources[0x61]	14419	1			T2	12		T3	9		T16	3
valid_sources[0x62]	12761	1			T2	2		T3	8		T4	3
valid_sources[0x63]	12741	1			T2	1		T3	6		T4	1
valid_sources[0x64]	12580	1			T2	14		T3	9		T4	4
valid_sources[0x65]	13071	1			T2	9		T3	3		T4	10
valid_sources[0x66]	12998	1			T2	13		T3	5		T4	2
valid_sources[0x67]	12408	1			T2	3		T3	1		T4	2
valid_sources[0x68]	12580	1			T2	11		T3	3		T35	4
valid_sources[0x69]	13877	1			T2	10		T3	4		T4	5
valid_sources[0x6a]	12383	1			T2	3		T3	8		T4	3
valid_sources[0x6b]	13961	1			T2	5		T3	9		T4	3
valid_sources[0x6c]	16582	1			T2	5		T3	9		T4	1
valid_sources[0x6d]	12659	1			T2	8		T3	4		T4	5
valid_sources[0x6e]	69883	1			T2	6		T3	4		T4	3
valid_sources[0x6f]	13299	1			T2	8		T3	5		T4	2
valid_sources[0x70]	12148	1			T2	5		T3	13		T4	9
valid_sources[0x71]	12557	1			T2	11		T3	5		T4	3
valid_sources[0x72]	12921	1			T2	5		T3	9		T4	4
valid_sources[0x73]	12420	1			T2	10		T3	2		T4	12
valid_sources[0x74]	12786	1			T2	17		T3	6		T4	1
valid_sources[0x75]	13919	1			T2	6		T3	5		T4	4
valid_sources[0x76]	11894	1			T2	14		T3	2		T4	4
valid_sources[0x77]	13043	1			T2	6		T3	6		T16	15
valid_sources[0x78]	13913	1			T2	6		T3	6		T4	5
valid_sources[0x79]	12022	1			T2	6		T3	4		T4	4
valid_sources[0x7a]	14587	1			T2	29		T3	6		T4	2
valid_sources[0x7b]	12799	1			T2	7		T3	3		T16	1
valid_sources[0x7c]	13103	1			T2	5		T3	7		T4	5
valid_sources[0x7d]	15510	1			T2	11		T3	6		T4	3
valid_sources[0x7e]	13059	1			T2	9		T3	3		T4	4
valid_sources[0x7f]	13241	1			T2	6		T3	6		T16	11
valid_sources[0x80]	12623	1			T2	3		T3	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319908

1

T1

126

T2

120

T3

121

values[0x0]

all_enables

biggest_size

147959

1

T1

19

T2

18

T3

24

values[0x1]

all_enables

biggest_size

133669

1

T1

11

T2

6

T3

11