Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3423464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

633801

1

T1

257

T2

156

T3

139

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3634787	1			T1	579		T2	670		T3	4668
values[0x0]	209486	1			T1	79		T2	47		T3	38
values[0x1]	212992	1			T1	70		T2	35		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2342270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1714995

1

T1

360

T2

325

T3

1635

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11800	1			T1	3		T2	4		T3	14
valid_sources[0x01]	14146	1			T1	4		T2	2		T3	20
valid_sources[0x02]	17594	1			T1	1		T2	5		T3	13
valid_sources[0x03]	21513	1			T1	2		T2	7		T3	17
valid_sources[0x04]	12632	1			T1	4		T2	2		T3	24
valid_sources[0x05]	11952	1			T1	3		T2	4		T3	21
valid_sources[0x06]	18022	1			T1	1		T3	23		T4	3
valid_sources[0x07]	12577	1			T1	7		T2	2		T3	15
valid_sources[0x08]	13700	1			T2	4		T3	19		T4	7
valid_sources[0x09]	12892	1			T2	3		T3	24		T4	13
valid_sources[0x0a]	12146	1			T1	7		T2	1		T3	23
valid_sources[0x0b]	19718	1			T1	2		T2	2		T3	24
valid_sources[0x0c]	13059	1			T1	6		T2	4		T3	20
valid_sources[0x0d]	13188	1			T1	1		T2	4		T3	18
valid_sources[0x0e]	16181	1			T1	4		T2	2		T3	17
valid_sources[0x0f]	12601	1			T3	20		T4	6		T5	4
valid_sources[0x10]	12082	1			T2	2		T3	18		T4	2
valid_sources[0x11]	13107	1			T1	3		T2	2		T3	20
valid_sources[0x12]	13705	1			T1	1		T2	3		T3	18
valid_sources[0x13]	15728	1			T1	2		T3	16		T4	7
valid_sources[0x14]	12947	1			T1	7		T2	7		T3	20
valid_sources[0x15]	13822	1			T1	3		T2	2		T3	17
valid_sources[0x16]	29443	1			T1	6		T3	21		T4	7
valid_sources[0x17]	12365	1			T1	3		T2	4		T3	21
valid_sources[0x18]	31232	1			T1	3		T2	1		T3	14
valid_sources[0x19]	12195	1			T1	2		T2	3		T3	24
valid_sources[0x1a]	11842	1			T1	2		T2	4		T3	15
valid_sources[0x1b]	14605	1			T1	4		T2	2		T3	10
valid_sources[0x1c]	11892	1			T1	4		T2	3		T3	28
valid_sources[0x1d]	14310	1			T1	3		T2	2		T3	23
valid_sources[0x1e]	33944	1			T1	9		T2	1		T3	16
valid_sources[0x1f]	12708	1			T1	1		T2	2		T3	10
valid_sources[0x20]	11893	1			T2	3		T3	28		T4	4
valid_sources[0x21]	17401	1			T1	4		T2	5		T3	23
valid_sources[0x22]	11914	1			T1	1		T2	3		T3	21
valid_sources[0x23]	12814	1			T1	3		T2	3		T3	29
valid_sources[0x24]	14893	1			T1	6		T2	2		T3	14
valid_sources[0x25]	23741	1			T1	2		T2	3		T3	24
valid_sources[0x26]	12441	1			T1	4		T2	6		T3	13
valid_sources[0x27]	12207	1			T2	5		T3	21		T5	1
valid_sources[0x28]	14737	1			T1	3		T2	6		T3	21
valid_sources[0x29]	12543	1			T2	3		T3	17		T4	3
valid_sources[0x2a]	21629	1			T1	2		T2	5		T3	16
valid_sources[0x2b]	12306	1			T1	1		T2	1		T3	24
valid_sources[0x2c]	12603	1			T1	1		T2	2		T3	19
valid_sources[0x2d]	13582	1			T2	2		T3	18		T4	2
valid_sources[0x2e]	14472	1			T1	10		T2	5		T3	15
valid_sources[0x2f]	12723	1			T1	2		T2	6		T3	22
valid_sources[0x30]	13902	1			T1	10		T3	14		T4	8
valid_sources[0x31]	12338	1			T2	2		T3	26		T4	5
valid_sources[0x32]	12227	1			T1	5		T2	4		T3	15
valid_sources[0x33]	12428	1			T1	3		T2	7		T3	25
valid_sources[0x34]	16669	1			T2	1		T3	28		T4	2
valid_sources[0x35]	12458	1			T1	3		T2	1		T3	18
valid_sources[0x36]	22522	1			T2	5		T3	21		T4	7
valid_sources[0x37]	13632	1			T1	3		T2	2		T3	19
valid_sources[0x38]	13130	1			T1	3		T2	4		T3	18
valid_sources[0x39]	13116	1			T1	1		T3	21		T4	1
valid_sources[0x3a]	30857	1			T1	2		T2	5		T3	19
valid_sources[0x3b]	15077	1			T2	1		T3	20		T4	4
valid_sources[0x3c]	23393	1			T1	3		T2	3		T3	26
valid_sources[0x3d]	12795	1			T2	3		T3	17		T4	13
valid_sources[0x3e]	22722	1			T1	4		T3	14		T4	2
valid_sources[0x3f]	13819	1			T1	1		T2	3		T3	17
valid_sources[0x40]	17339	1			T1	1		T2	4		T3	15
valid_sources[0x41]	17651	1			T1	1		T2	4		T3	17
valid_sources[0x42]	13957	1			T2	4		T3	17		T4	3
valid_sources[0x43]	12704	1			T1	5		T2	3		T3	13
valid_sources[0x44]	11890	1			T1	2		T2	4		T3	13
valid_sources[0x45]	13973	1			T1	1		T2	2		T3	19
valid_sources[0x46]	11943	1			T1	8		T2	4		T3	19
valid_sources[0x47]	25277	1			T1	4		T2	2		T3	17
valid_sources[0x48]	12572	1			T1	1		T2	5		T3	16
valid_sources[0x49]	12309	1			T1	3		T2	6		T3	24
valid_sources[0x4a]	13169	1			T1	2		T2	4		T3	15
valid_sources[0x4b]	12579	1			T1	3		T2	1		T3	18
valid_sources[0x4c]	11750	1			T1	6		T2	4		T3	16
valid_sources[0x4d]	24215	1			T1	2		T2	1		T3	23
valid_sources[0x4e]	12869	1			T1	1		T2	1		T3	15
valid_sources[0x4f]	14295	1			T2	1		T3	21		T4	7
valid_sources[0x50]	12251	1			T1	1		T2	3		T3	14
valid_sources[0x51]	16354	1			T1	9		T2	1		T3	17
valid_sources[0x52]	13141	1			T1	3		T2	1		T3	18
valid_sources[0x53]	12037	1			T1	2		T2	1		T3	18
valid_sources[0x54]	18181	1			T1	8		T2	5		T3	22
valid_sources[0x55]	11929	1			T1	2		T2	8		T3	22
valid_sources[0x56]	13130	1			T1	14		T2	1		T3	10
valid_sources[0x57]	13383	1			T2	5		T3	24		T4	4
valid_sources[0x58]	12547	1			T2	1		T3	21		T4	8
valid_sources[0x59]	63024	1			T1	1		T2	5		T3	22
valid_sources[0x5a]	12809	1			T1	3		T2	4		T3	25
valid_sources[0x5b]	12402	1			T1	2		T2	5		T3	29
valid_sources[0x5c]	12034	1			T1	6		T2	1		T3	16
valid_sources[0x5d]	16323	1			T1	1		T2	2		T3	12
valid_sources[0x5e]	12155	1			T1	4		T2	5		T3	25
valid_sources[0x5f]	26777	1			T1	4		T2	2		T3	13
valid_sources[0x60]	12972	1			T1	6		T2	2		T3	15
valid_sources[0x61]	12697	1			T1	2		T2	2		T3	14
valid_sources[0x62]	21671	1			T1	4		T2	2		T3	22
valid_sources[0x63]	11885	1			T1	4		T2	5		T3	12
valid_sources[0x64]	12123	1			T1	2		T2	2		T3	14
valid_sources[0x65]	22049	1			T1	4		T2	6		T3	12
valid_sources[0x66]	12798	1			T1	1		T2	3		T3	17
valid_sources[0x67]	13320	1			T1	1		T2	4		T3	17
valid_sources[0x68]	18254	1			T1	5		T2	5		T3	15
valid_sources[0x69]	25900	1			T1	3		T2	1		T3	16
valid_sources[0x6a]	22122	1			T1	2		T2	4		T3	27
valid_sources[0x6b]	17197	1			T2	2		T3	16		T4	9
valid_sources[0x6c]	11831	1			T1	6		T2	3		T3	16
valid_sources[0x6d]	12326	1			T1	3		T2	6		T3	25
valid_sources[0x6e]	20962	1			T1	4		T2	4		T3	14
valid_sources[0x6f]	18404	1			T1	2		T2	2		T3	18
valid_sources[0x70]	16560	1			T1	1		T2	3		T3	15
valid_sources[0x71]	13524	1			T1	3		T2	6		T3	24
valid_sources[0x72]	11331	1			T1	6		T2	5		T3	16
valid_sources[0x73]	12307	1			T1	1		T2	10		T3	16
valid_sources[0x74]	13029	1			T1	2		T2	3		T3	22
valid_sources[0x75]	12799	1			T1	9		T2	1		T3	13
valid_sources[0x76]	11916	1			T1	7		T2	4		T3	18
valid_sources[0x77]	12044	1			T1	4		T2	3		T3	13
valid_sources[0x78]	13308	1			T1	1		T2	4		T3	20
valid_sources[0x79]	13333	1			T2	1		T3	20		T4	3
valid_sources[0x7a]	21020	1			T1	3		T2	3		T3	20
valid_sources[0x7b]	12759	1			T1	1		T2	3		T3	19
valid_sources[0x7c]	11874	1			T1	5		T2	1		T3	20
valid_sources[0x7d]	13928	1			T1	3		T2	2		T3	17
valid_sources[0x7e]	12088	1			T1	3		T2	2		T3	25
valid_sources[0x7f]	17259	1			T1	4		T2	1		T3	12
valid_sources[0x80]	12605	1			T1	3		T2	4		T3	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

345395

1

T1

212

T2

130

T3

105

values[0x0]

all_enables

biggest_size

151689

1

T1

33

T2

16

T3

24

values[0x1]

all_enables

biggest_size

136717

1

T1

12

T2

10

T3

10