Unified Coverage Report :: Module :: tlul_data_integ_dec

Module : tlul_data_integ_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_chk.u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_chk.u_tlul_data_integ_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_chk	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_data_integ_dec

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	25	1	1	100.00

24                      
25         1/1            assign data_err_o = |data_err;
           Tests:       T1 T2 T3