Module Definition
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Module : keymgr_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.90 100.00 99.61 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.90 100.00 99.61 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.90 100.00 99.61 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.48 98.74 99.18 100.00 99.47 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_fault_err 100.00 100.00
u_alert_test_recov_operation_err 100.00 100.00
u_attest_sw_binding_0 100.00 100.00 100.00 100.00
u_attest_sw_binding_1 100.00 100.00 100.00 100.00
u_attest_sw_binding_2 100.00 100.00 100.00 100.00
u_attest_sw_binding_3 100.00 100.00 100.00 100.00
u_attest_sw_binding_4 100.00 100.00 100.00 100.00
u_attest_sw_binding_5 100.00 100.00 100.00 100.00
u_attest_sw_binding_6 100.00 100.00 100.00 100.00
u_attest_sw_binding_7 100.00 100.00 100.00 100.00
u_cfg_regwen 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_control_shadowed_cdi_sel 99.55 100.00 98.21 100.00 100.00
u_control_shadowed_dest_sel 99.55 100.00 98.21 100.00 100.00
u_control_shadowed_operation 99.55 100.00 98.21 100.00 100.00
u_debug_invalid_creator_seed 100.00 100.00 100.00 100.00
u_debug_invalid_dev_id 100.00 100.00 100.00 100.00
u_debug_invalid_digest 100.00 100.00 100.00 100.00
u_debug_invalid_health_state 100.00 100.00 100.00 100.00
u_debug_invalid_key 100.00 100.00 100.00 100.00
u_debug_invalid_key_version 100.00 100.00 100.00 100.00
u_debug_invalid_owner_seed 100.00 100.00 100.00 100.00
u_err_code_invalid_kmac_input 100.00 100.00 100.00 100.00
u_err_code_invalid_op 100.00 100.00 100.00 100.00
u_err_code_invalid_shadow_update 97.22 100.00 91.67 100.00
u_fault_status_cmd 96.30 88.89 100.00 100.00
u_fault_status_ctrl_fsm_chk 96.30 88.89 100.00 100.00
u_fault_status_ctrl_fsm_cnt 96.30 88.89 100.00 100.00
u_fault_status_ctrl_fsm_intg 96.30 88.89 100.00 100.00
u_fault_status_key_ecc 96.30 88.89 100.00 100.00
u_fault_status_kmac_done 96.30 88.89 100.00 100.00
u_fault_status_kmac_fsm 96.30 88.89 100.00 100.00
u_fault_status_kmac_op 96.30 88.89 100.00 100.00
u_fault_status_kmac_out 62.59 77.78 50.00 60.00
u_fault_status_regfile_intg 96.30 88.89 100.00 100.00
u_fault_status_reseed_cnt 96.30 88.89 100.00 100.00
u_fault_status_shadow 96.30 88.89 100.00 100.00
u_fault_status_side_ctrl_fsm 96.30 88.89 100.00 100.00
u_fault_status_side_ctrl_sel 96.30 88.89 100.00 100.00
u_intr_enable 100.00 100.00 100.00 100.00
u_intr_state 100.00 100.00 100.00 100.00
u_intr_test 100.00 100.00
u_key_version 100.00 100.00 100.00 100.00
u_max_creator_key_ver_regwen 100.00 100.00 100.00 100.00
u_max_creator_key_ver_shadowed 99.55 100.00 98.21 100.00 100.00
u_max_owner_int_key_ver_regwen 100.00 100.00 100.00 100.00
u_max_owner_int_key_ver_shadowed 99.55 100.00 98.21 100.00 100.00
u_max_owner_key_ver_regwen 100.00 100.00 100.00 100.00
u_max_owner_key_ver_shadowed 99.55 100.00 98.21 100.00 100.00
u_op_status 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.69 97.14 97.62 100.00 100.00
u_reseed_interval_regwen 100.00 100.00 100.00 100.00
u_reseed_interval_shadowed 99.55 100.00 98.21 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_salt_0 100.00 100.00 100.00 100.00
u_salt_1 100.00 100.00 100.00 100.00
u_salt_2 100.00 100.00 100.00 100.00
u_salt_3 100.00 100.00 100.00 100.00
u_salt_4 100.00 100.00 100.00 100.00
u_salt_5 100.00 100.00 100.00 100.00
u_salt_6 100.00 100.00 100.00 100.00
u_salt_7 100.00 100.00 100.00 100.00
u_sealing_sw_binding_0 100.00 100.00 100.00 100.00
u_sealing_sw_binding_1 100.00 100.00 100.00 100.00
u_sealing_sw_binding_2 100.00 100.00 100.00 100.00
u_sealing_sw_binding_3 100.00 100.00 100.00 100.00
u_sealing_sw_binding_4 100.00 100.00 100.00 100.00
u_sealing_sw_binding_5 100.00 100.00 100.00 100.00
u_sealing_sw_binding_6 100.00 100.00 100.00 100.00
u_sealing_sw_binding_7 100.00 100.00 100.00 100.00
u_sideload_clear 100.00 100.00 100.00 100.00
u_start 100.00 100.00 100.00 100.00
u_sw_binding_regwen 100.00 100.00
u_sw_share0_output_0 100.00 100.00 100.00 100.00
u_sw_share0_output_1 100.00 100.00 100.00 100.00
u_sw_share0_output_2 100.00 100.00 100.00 100.00
u_sw_share0_output_3 100.00 100.00 100.00 100.00
u_sw_share0_output_4 100.00 100.00 100.00 100.00
u_sw_share0_output_5 100.00 100.00 100.00 100.00
u_sw_share0_output_6 100.00 100.00 100.00 100.00
u_sw_share0_output_7 100.00 100.00 100.00 100.00
u_sw_share1_output_0 100.00 100.00 100.00 100.00
u_sw_share1_output_1 100.00 100.00 100.00 100.00
u_sw_share1_output_2 100.00 100.00 100.00 100.00
u_sw_share1_output_3 100.00 100.00 100.00 100.00
u_sw_share1_output_4 100.00 100.00 100.00 100.00
u_sw_share1_output_5 100.00 100.00 100.00 100.00
u_sw_share1_output_6 100.00 100.00 100.00 100.00
u_sw_share1_output_7 100.00 100.00 100.00 100.00
u_working_state 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_reg_top
Line No.TotalCoveredPercent
TOTAL401401100.00
ALWAYS7244100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
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CONT_ASSIGN149911100.00
CONT_ASSIGN153111100.00
CONT_ASSIGN159011100.00
CONT_ASSIGN165911100.00
CONT_ASSIGN172811100.00
ALWAYS29436464100.00
CONT_ASSIGN300911100.00
ALWAYS301311100.00
CONT_ASSIGN308011100.00
CONT_ASSIGN308211100.00
CONT_ASSIGN308311100.00
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CONT_ASSIGN308611100.00
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CONT_ASSIGN328011100.00
CONT_ASSIGN328211100.00
CONT_ASSIGN328411100.00
CONT_ASSIGN328611100.00
CONT_ASSIGN328811100.00
ALWAYS32926464100.00
ALWAYS33608989100.00
ALWAYS364933100.00
ALWAYS365733100.00
CONT_ASSIGN366511100.00
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Click here to see the source line report.

Cond Coverage for Module : keymgr_reg_top
TotalCoveredPercent
Conditions76876599.61
Logical76876599.61
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
62-3013100.00
3013-3177100.00
3180-366597.78

Branch Coverage for Module : keymgr_reg_top
Line No.TotalCoveredPercent
Branches 73 73 100.00
TERNARY 3009 2 2 100.00
IF 72 3 3 100.00
CASE 3361 64 64 100.00
IF 3649 2 2 100.00
IF 3657 2 2 100.00


3009 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


72 if (!rst_ni) begin -1- 73 err_q <= '0; ==> 74 end else if (intg_err || reg_we_err) begin -2- 75 err_q <= 1'b1; ==> 76 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T37,T10,T40
0 0 Covered T1,T2,T3


3361 unique case (1'b1) -1- 3362 addr_hit[0]: begin 3363 reg_rdata_next[0] = intr_state_qs; ==> 3364 end 3365 3366 addr_hit[1]: begin 3367 reg_rdata_next[0] = intr_enable_qs; ==> 3368 end 3369 3370 addr_hit[2]: begin 3371 reg_rdata_next[0] = '0; ==> 3372 end 3373 3374 addr_hit[3]: begin 3375 reg_rdata_next[0] = '0; ==> 3376 reg_rdata_next[1] = '0; 3377 end 3378 3379 addr_hit[4]: begin 3380 reg_rdata_next[0] = cfg_regwen_qs; ==> 3381 end 3382 3383 addr_hit[5]: begin 3384 reg_rdata_next[0] = start_qs; ==> 3385 end 3386 3387 addr_hit[6]: begin 3388 reg_rdata_next[6:4] = control_shadowed_operation_qs; ==> 3389 reg_rdata_next[7] = control_shadowed_cdi_sel_qs; 3390 reg_rdata_next[13:12] = control_shadowed_dest_sel_qs; 3391 end 3392 3393 addr_hit[7]: begin 3394 reg_rdata_next[2:0] = sideload_clear_qs; ==> 3395 end 3396 3397 addr_hit[8]: begin 3398 reg_rdata_next[0] = reseed_interval_regwen_qs; ==> 3399 end 3400 3401 addr_hit[9]: begin 3402 reg_rdata_next[15:0] = reseed_interval_shadowed_qs; ==> 3403 end 3404 3405 addr_hit[10]: begin 3406 reg_rdata_next[0] = sw_binding_regwen_qs; ==> 3407 end 3408 3409 addr_hit[11]: begin 3410 reg_rdata_next[31:0] = sealing_sw_binding_0_qs; ==> 3411 end 3412 3413 addr_hit[12]: begin 3414 reg_rdata_next[31:0] = sealing_sw_binding_1_qs; ==> 3415 end 3416 3417 addr_hit[13]: begin 3418 reg_rdata_next[31:0] = sealing_sw_binding_2_qs; ==> 3419 end 3420 3421 addr_hit[14]: begin 3422 reg_rdata_next[31:0] = sealing_sw_binding_3_qs; ==> 3423 end 3424 3425 addr_hit[15]: begin 3426 reg_rdata_next[31:0] = sealing_sw_binding_4_qs; ==> 3427 end 3428 3429 addr_hit[16]: begin 3430 reg_rdata_next[31:0] = sealing_sw_binding_5_qs; ==> 3431 end 3432 3433 addr_hit[17]: begin 3434 reg_rdata_next[31:0] = sealing_sw_binding_6_qs; ==> 3435 end 3436 3437 addr_hit[18]: begin 3438 reg_rdata_next[31:0] = sealing_sw_binding_7_qs; ==> 3439 end 3440 3441 addr_hit[19]: begin 3442 reg_rdata_next[31:0] = attest_sw_binding_0_qs; ==> 3443 end 3444 3445 addr_hit[20]: begin 3446 reg_rdata_next[31:0] = attest_sw_binding_1_qs; ==> 3447 end 3448 3449 addr_hit[21]: begin 3450 reg_rdata_next[31:0] = attest_sw_binding_2_qs; ==> 3451 end 3452 3453 addr_hit[22]: begin 3454 reg_rdata_next[31:0] = attest_sw_binding_3_qs; ==> 3455 end 3456 3457 addr_hit[23]: begin 3458 reg_rdata_next[31:0] = attest_sw_binding_4_qs; ==> 3459 end 3460 3461 addr_hit[24]: begin 3462 reg_rdata_next[31:0] = attest_sw_binding_5_qs; ==> 3463 end 3464 3465 addr_hit[25]: begin 3466 reg_rdata_next[31:0] = attest_sw_binding_6_qs; ==> 3467 end 3468 3469 addr_hit[26]: begin 3470 reg_rdata_next[31:0] = attest_sw_binding_7_qs; ==> 3471 end 3472 3473 addr_hit[27]: begin 3474 reg_rdata_next[31:0] = salt_0_qs; ==> 3475 end 3476 3477 addr_hit[28]: begin 3478 reg_rdata_next[31:0] = salt_1_qs; ==> 3479 end 3480 3481 addr_hit[29]: begin 3482 reg_rdata_next[31:0] = salt_2_qs; ==> 3483 end 3484 3485 addr_hit[30]: begin 3486 reg_rdata_next[31:0] = salt_3_qs; ==> 3487 end 3488 3489 addr_hit[31]: begin 3490 reg_rdata_next[31:0] = salt_4_qs; ==> 3491 end 3492 3493 addr_hit[32]: begin 3494 reg_rdata_next[31:0] = salt_5_qs; ==> 3495 end 3496 3497 addr_hit[33]: begin 3498 reg_rdata_next[31:0] = salt_6_qs; ==> 3499 end 3500 3501 addr_hit[34]: begin 3502 reg_rdata_next[31:0] = salt_7_qs; ==> 3503 end 3504 3505 addr_hit[35]: begin 3506 reg_rdata_next[31:0] = key_version_qs; ==> 3507 end 3508 3509 addr_hit[36]: begin 3510 reg_rdata_next[0] = max_creator_key_ver_regwen_qs; ==> 3511 end 3512 3513 addr_hit[37]: begin 3514 reg_rdata_next[31:0] = max_creator_key_ver_shadowed_qs; ==> 3515 end 3516 3517 addr_hit[38]: begin 3518 reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs; ==> 3519 end 3520 3521 addr_hit[39]: begin 3522 reg_rdata_next[31:0] = max_owner_int_key_ver_shadowed_qs; ==> 3523 end 3524 3525 addr_hit[40]: begin 3526 reg_rdata_next[0] = max_owner_key_ver_regwen_qs; ==> 3527 end 3528 3529 addr_hit[41]: begin 3530 reg_rdata_next[31:0] = max_owner_key_ver_shadowed_qs; ==> 3531 end 3532 3533 addr_hit[42]: begin 3534 reg_rdata_next[31:0] = sw_share0_output_0_qs; ==> 3535 end 3536 3537 addr_hit[43]: begin 3538 reg_rdata_next[31:0] = sw_share0_output_1_qs; ==> 3539 end 3540 3541 addr_hit[44]: begin 3542 reg_rdata_next[31:0] = sw_share0_output_2_qs; ==> 3543 end 3544 3545 addr_hit[45]: begin 3546 reg_rdata_next[31:0] = sw_share0_output_3_qs; ==> 3547 end 3548 3549 addr_hit[46]: begin 3550 reg_rdata_next[31:0] = sw_share0_output_4_qs; ==> 3551 end 3552 3553 addr_hit[47]: begin 3554 reg_rdata_next[31:0] = sw_share0_output_5_qs; ==> 3555 end 3556 3557 addr_hit[48]: begin 3558 reg_rdata_next[31:0] = sw_share0_output_6_qs; ==> 3559 end 3560 3561 addr_hit[49]: begin 3562 reg_rdata_next[31:0] = sw_share0_output_7_qs; ==> 3563 end 3564 3565 addr_hit[50]: begin 3566 reg_rdata_next[31:0] = sw_share1_output_0_qs; ==> 3567 end 3568 3569 addr_hit[51]: begin 3570 reg_rdata_next[31:0] = sw_share1_output_1_qs; ==> 3571 end 3572 3573 addr_hit[52]: begin 3574 reg_rdata_next[31:0] = sw_share1_output_2_qs; ==> 3575 end 3576 3577 addr_hit[53]: begin 3578 reg_rdata_next[31:0] = sw_share1_output_3_qs; ==> 3579 end 3580 3581 addr_hit[54]: begin 3582 reg_rdata_next[31:0] = sw_share1_output_4_qs; ==> 3583 end 3584 3585 addr_hit[55]: begin 3586 reg_rdata_next[31:0] = sw_share1_output_5_qs; ==> 3587 end 3588 3589 addr_hit[56]: begin 3590 reg_rdata_next[31:0] = sw_share1_output_6_qs; ==> 3591 end 3592 3593 addr_hit[57]: begin 3594 reg_rdata_next[31:0] = sw_share1_output_7_qs; ==> 3595 end 3596 3597 addr_hit[58]: begin 3598 reg_rdata_next[2:0] = working_state_qs; ==> 3599 end 3600 3601 addr_hit[59]: begin 3602 reg_rdata_next[1:0] = op_status_qs; ==> 3603 end 3604 3605 addr_hit[60]: begin 3606 reg_rdata_next[0] = err_code_invalid_op_qs; ==> 3607 reg_rdata_next[1] = err_code_invalid_kmac_input_qs; 3608 reg_rdata_next[2] = err_code_invalid_shadow_update_qs; 3609 end 3610 3611 addr_hit[61]: begin 3612 reg_rdata_next[0] = fault_status_cmd_qs; ==> 3613 reg_rdata_next[1] = fault_status_kmac_fsm_qs; 3614 reg_rdata_next[2] = fault_status_kmac_done_qs; 3615 reg_rdata_next[3] = fault_status_kmac_op_qs; 3616 reg_rdata_next[4] = fault_status_kmac_out_qs; 3617 reg_rdata_next[5] = fault_status_regfile_intg_qs; 3618 reg_rdata_next[6] = fault_status_shadow_qs; 3619 reg_rdata_next[7] = fault_status_ctrl_fsm_intg_qs; 3620 reg_rdata_next[8] = fault_status_ctrl_fsm_chk_qs; 3621 reg_rdata_next[9] = fault_status_ctrl_fsm_cnt_qs; 3622 reg_rdata_next[10] = fault_status_reseed_cnt_qs; 3623 reg_rdata_next[11] = fault_status_side_ctrl_fsm_qs; 3624 reg_rdata_next[12] = fault_status_side_ctrl_sel_qs; 3625 reg_rdata_next[13] = fault_status_key_ecc_qs; 3626 end 3627 3628 addr_hit[62]: begin 3629 reg_rdata_next[0] = debug_invalid_creator_seed_qs; ==> 3630 reg_rdata_next[1] = debug_invalid_owner_seed_qs; 3631 reg_rdata_next[2] = debug_invalid_dev_id_qs; 3632 reg_rdata_next[3] = debug_invalid_health_state_qs; 3633 reg_rdata_next[4] = debug_invalid_key_version_qs; 3634 reg_rdata_next[5] = debug_invalid_key_qs; 3635 reg_rdata_next[6] = debug_invalid_digest_qs; 3636 end 3637 3638 default: begin 3639 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
addr_hit[35] Covered T1,T2,T3
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T1,T2,T3
addr_hit[38] Covered T1,T2,T3
addr_hit[39] Covered T1,T2,T3
addr_hit[40] Covered T1,T2,T3
addr_hit[41] Covered T1,T2,T3
addr_hit[42] Covered T1,T2,T3
addr_hit[43] Covered T1,T2,T3
addr_hit[44] Covered T1,T2,T3
addr_hit[45] Covered T1,T2,T3
addr_hit[46] Covered T1,T2,T3
addr_hit[47] Covered T1,T2,T3
addr_hit[48] Covered T1,T2,T3
addr_hit[49] Covered T1,T2,T3
addr_hit[50] Covered T1,T2,T3
addr_hit[51] Covered T1,T2,T3
addr_hit[52] Covered T1,T2,T3
addr_hit[53] Covered T1,T2,T3
addr_hit[54] Covered T1,T2,T3
addr_hit[55] Covered T1,T2,T3
addr_hit[56] Covered T1,T2,T3
addr_hit[57] Covered T1,T2,T3
addr_hit[58] Covered T1,T2,T3
addr_hit[59] Covered T1,T2,T3
addr_hit[60] Covered T1,T2,T3
addr_hit[61] Covered T1,T2,T3
addr_hit[62] Covered T1,T2,T3
default Covered T1,T2,T3


3649 if (!rst_ni) begin -1- 3650 rst_done <= '0; ==> 3651 end else begin 3652 rst_done <= 1'b1; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


3657 if (!rst_shadowed_ni) begin -1- 3658 shadow_rst_done <= '0; ==> 3659 end else begin 3660 shadow_rst_done <= 1'b1; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : keymgr_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 23397362 3696179 0 0
reAfterRv 23397362 3696179 0 0
rePulse 23397362 3314691 0 0
wePulse 23397362 381488 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 23397362 3696179 0 0
T1 5456 481 0 0
T2 18058 1972 0 0
T3 17046 1484 0 0
T4 5438 1148 0 0
T13 1307 11 0 0
T14 4324 531 0 0
T15 4964 1416 0 0
T16 4832 542 0 0
T17 9788 752 0 0
T18 11952 955 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 23397362 3696179 0 0
T1 5456 481 0 0
T2 18058 1972 0 0
T3 17046 1484 0 0
T4 5438 1148 0 0
T13 1307 11 0 0
T14 4324 531 0 0
T15 4964 1416 0 0
T16 4832 542 0 0
T17 9788 752 0 0
T18 11952 955 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 23397362 3314691 0 0
T1 5456 395 0 0
T2 18058 1895 0 0
T3 17046 1399 0 0
T4 5438 955 0 0
T13 1307 1 0 0
T14 4324 330 0 0
T15 4964 919 0 0
T16 4832 444 0 0
T17 9788 622 0 0
T18 11952 774 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 23397362 381488 0 0
T1 5456 86 0 0
T2 18058 77 0 0
T3 17046 85 0 0
T4 5438 193 0 0
T13 1307 10 0 0
T14 4324 201 0 0
T15 4964 497 0 0
T16 4832 98 0 0
T17 9788 130 0 0
T18 11952 181 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%