Module Definition
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Module : prim_generic_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_ctrl.u_hw_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_ctrl.u_op_state.u_state_regs.u_state_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_ctrl.u_data_en.u_state_regs.u_state_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_kmac_if.u_state_regs.u_state_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sideload_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.u_hw_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.u_op_state.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ctrl.u_data_en.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_kmac_if.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sideload_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_ctrl.u_key_valid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_hw_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_ctrl.u_hw_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_op_state.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_ctrl.u_op_state.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctrl.u_data_en.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_ctrl.u_data_en.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_kmac_if.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_kmac_if.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%