Module Definition
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Module : keymgr_err
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.81 100.00 84.44 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_err.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl.u_err 94.81 100.00 84.44 100.00



Module Instance : tb.dut.u_ctrl.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.81 100.00 84.44 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.81 100.00 84.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.62 100.00 98.11 100.00 100.00 100.00 u_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_err
Line No.TotalCoveredPercent
TOTAL5353100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7511100.00
ALWAYS7866100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
ALWAYS9666100.00
CONT_ASSIGN10411100.00
ALWAYS10933100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00

65 logic err_vld; 66 1/1 assign err_vld = op_update_i | op_done_i; Tests: T1 T2 T3  67 68 // sync errors 69 // When an operation encounters a fault, the operation is always rejected as the FSM 70 // transitions to wipe. When an operation is ongoing and en drops, it is also rejected. 71 1/1 assign sync_err_d[SyncErrInvalidOp] = err_vld & (invalid_op_i | Tests: T1 T2 T3  72 disabled_i | 73 invalid_i | 74 (|fault_o)); 75 1/1 assign sync_err_d[SyncErrInvalidIn] = err_vld & kmac_input_invalid_i; Tests: T1 T2 T3  76 77 always_ff @(posedge clk_i or negedge rst_ni) begin 78 1/1 if (!rst_ni) begin Tests: T1 T2 T3  79 1/1 sync_err_q <= '0; Tests: T1 T2 T3  80 1/1 end else if (op_done_i) begin Tests: T1 T2 T3  81 1/1 sync_err_q <= '0; Tests: T1 T2 T3  82 1/1 end else if (op_update_i) begin Tests: T1 T2 T3  83 1/1 sync_err_q <= sync_err_d; Tests: T1 T2 T3  84 end MISSING_ELSE 85 end 86 1/1 assign sync_err_o = sync_err_q | sync_err_d; Tests: T1 T2 T3  87 88 // async errors 89 1/1 assign async_err_o[AsyncErrShadowUpdate] = shadowed_update_err_i; Tests: T1 T2 T3  90 91 // sync faults 92 1/1 assign sync_fault_d[SyncFaultKmacOp] = err_vld & kmac_op_err_i; Tests: T1 T2 T3  93 1/1 assign sync_fault_d[SyncFaultKmacOut] = err_vld & invalid_kmac_out_i; Tests: T1 T2 T3  94 1/1 assign sync_fault_d[SyncFaultSideSel] = err_vld & sideload_sel_err_i; Tests: T1 T2 T3  95 always_ff @(posedge clk_i or negedge rst_ni) begin 96 1/1 if (!rst_ni) begin Tests: T1 T2 T3  97 1/1 sync_fault_q <= '0; Tests: T1 T2 T3  98 1/1 end else if (op_done_i) begin Tests: T1 T2 T3  99 1/1 sync_fault_q <= '0; Tests: T1 T2 T3  100 1/1 end else if (op_update_i) begin Tests: T1 T2 T3  101 1/1 sync_fault_q <= sync_fault_d; Tests: T1 T2 T3  102 end MISSING_ELSE 103 end 104 1/1 assign sync_fault_o = sync_fault_q | sync_fault_d; Tests: T1 T2 T3  105 106 // async faults 107 logic [AsyncFaultLastIdx-1:0] async_fault_q, async_fault_d; 108 always_ff @(posedge clk_i or negedge rst_ni) begin 109 1/1 if (!rst_ni) begin Tests: T1 T2 T3  110 1/1 async_fault_q <= '0; Tests: T1 T2 T3  111 end else begin 112 1/1 async_fault_q <= async_fault_o; Tests: T1 T2 T3  113 end 114 end 115 1/1 assign async_fault_o = async_fault_q | async_fault_d; Tests: T1 T2 T3  116 1/1 assign async_fault_d[AsyncFaultKmacCmd] = kmac_cmd_err_i; Tests: T1 T2 T3  117 1/1 assign async_fault_d[AsyncFaultKmacFsm] = kmac_fsm_err_i; Tests: T1 T2 T3  118 1/1 assign async_fault_d[AsyncFaultKmacDone] = kmac_done_err_i; Tests: T1 T2 T3  119 1/1 assign async_fault_d[AsyncFaultRegIntg] = regfile_intg_err_i; Tests: T1 T2 T3  120 1/1 assign async_fault_d[AsyncFaultShadow ] = shadowed_storage_err_i; Tests: T1 T2 T3  121 1/1 assign async_fault_d[AsyncFaultFsmIntg] = ctrl_fsm_err_i | data_fsm_err_i | op_fsm_err_i; Tests: T1 T2 T3  122 1/1 assign async_fault_d[AsyncFaultKeyEcc] = ecc_err_i; Tests: T1 T2 T3  123 124 // SEC_CM: CTRL.FSM.CONSISTENCY 125 1/1 assign async_fault_d[AsyncFaultFsmChk] = state_change_err_i | op_state_cmd_err_i; Tests: T1 T2 T3  126 1/1 assign async_fault_d[AsyncFaultCntErr ] = cnt_err_i; Tests: T1 T2 T3  127 1/1 assign async_fault_d[AsyncFaultRCntErr] = reseed_cnt_err_i; Tests: T1 T2 T3  128 1/1 assign async_fault_d[AsyncFaultSideErr] = sideload_fsm_err_i; Tests: T1 T2 T3  129 130 // certain errors/faults can only happen when there's an actual kmac transaction, 131 // others can happen with or without. 132 1/1 assign error_o[ErrInvalidOp] = op_done_i & sync_err_o[SyncErrInvalidOp]; Tests: T1 T2 T3  133 1/1 assign error_o[ErrInvalidIn] = op_done_i & sync_err_o[SyncErrInvalidIn]; Tests: T1 T2 T3  134 1/1 assign error_o[ErrShadowUpdate] = async_err_o[AsyncErrShadowUpdate]; Tests: T1 T2 T3  135 136 // output to fault code register 137 1/1 assign fault_o[FaultKmacOp] = op_done_i & sync_fault_o[SyncFaultKmacOp]; Tests: T1 T2 T3  138 1/1 assign fault_o[FaultKmacOut] = op_done_i & sync_fault_o[SyncFaultKmacOut]; Tests: T1 T2 T3  139 1/1 assign fault_o[FaultSideSel] = op_done_i & sync_fault_o[SyncFaultSideSel]; Tests: T1 T2 T3  140 1/1 assign fault_o[FaultKmacCmd] = async_fault_o[AsyncFaultKmacCmd]; Tests: T1 T2 T3  141 1/1 assign fault_o[FaultKmacFsm] = async_fault_o[AsyncFaultKmacFsm]; Tests: T1 T2 T3  142 1/1 assign fault_o[FaultKmacDone] = async_fault_o[AsyncFaultKmacDone]; Tests: T1 T2 T3  143 1/1 assign fault_o[FaultRegIntg] = async_fault_o[AsyncFaultRegIntg]; Tests: T1 T2 T3  144 1/1 assign fault_o[FaultShadow] = async_fault_o[AsyncFaultShadow]; Tests: T1 T2 T3  145 1/1 assign fault_o[FaultCtrlFsm] = async_fault_o[AsyncFaultFsmIntg]; Tests: T1 T2 T3  146 1/1 assign fault_o[FaultCtrlFsmChk] = async_fault_o[AsyncFaultFsmChk]; Tests: T1 T2 T3  147 1/1 assign fault_o[FaultCtrlCnt] = async_fault_o[AsyncFaultCntErr]; Tests: T1 T2 T3  148 1/1 assign fault_o[FaultReseedCnt] = async_fault_o[AsyncFaultRCntErr]; Tests: T1 T2 T3  149 1/1 assign fault_o[FaultSideFsm] = async_fault_o[AsyncFaultSideErr]; Tests: T1 T2 T3  150 1/1 assign fault_o[FaultKeyEcc] = async_fault_o[AsyncFaultKeyEcc]; Tests: T1 T2 T3 

Cond Coverage for Module : keymgr_err
TotalCoveredPercent
Conditions453884.44
Logical453884.44
Non-Logical00
Event00

 LINE       66
 EXPRESSION (op_update_i | op_done_i)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       71
 EXPRESSION (err_vld & (invalid_op_i | disabled_i | invalid_i | ((|fault_o))))
             ---1---   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (invalid_op_i | disabled_i | invalid_i | ((|fault_o)))
                 ------1-----   -----2----   ----3----   ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT15,T37,T10
0010CoveredT14,T38,T39
0100CoveredT1,T2,T3
1000CoveredT1,T2,T3

 LINE       75
 EXPRESSION (err_vld & kmac_input_invalid_i)
             ---1---   ----------2---------
-1--2-StatusTests
01CoveredT19,T5,T26
10CoveredT1,T2,T3
11CoveredT19,T5,T26

 LINE       92
 EXPRESSION (err_vld & kmac_op_err_i)
             ---1---   ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT37,T39,T40

 LINE       93
 EXPRESSION (err_vld & invalid_kmac_out_i)
             ---1---   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       94
 EXPRESSION (err_vld & sideload_sel_err_i)
             ---1---   ---------2--------
-1--2-StatusTests
01CoveredT41,T42,T43
10CoveredT1,T2,T3
11CoveredT41,T42,T43

 LINE       121
 EXPRESSION (ctrl_fsm_err_i | data_fsm_err_i | op_fsm_err_i)
             -------1------   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T12
010CoveredT10,T11,T12
100CoveredT10,T11,T12

 LINE       125
 EXPRESSION (state_change_err_i | op_state_cmd_err_i)
             ---------1--------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T27,T44
10Not Covered

 LINE       132
 EXPRESSION (op_done_i & sync_err_o[SyncErrInvalidOp])
             ----1----   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       133
 EXPRESSION (op_done_i & sync_err_o[SyncErrInvalidIn])
             ----1----   --------------2-------------
-1--2-StatusTests
01CoveredT23,T24,T21
10CoveredT1,T2,T3
11CoveredT19,T5,T26

 LINE       137
 EXPRESSION (op_done_i & sync_fault_o[SyncFaultKmacOp])
             ----1----   --------------2--------------
-1--2-StatusTests
01CoveredT37,T45,T46
10CoveredT1,T2,T3
11CoveredT37,T39,T40

 LINE       138
 EXPRESSION (op_done_i & sync_fault_o[SyncFaultKmacOut])
             ----1----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       139
 EXPRESSION (op_done_i & sync_fault_o[SyncFaultSideSel])
             ----1----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT41,T42,T43

Branch Coverage for Module : keymgr_err
Line No.TotalCoveredPercent
Branches 10 10 100.00
IF 78 4 4 100.00
IF 96 4 4 100.00
IF 109 2 2 100.00


78 if (!rst_ni) begin -1- 79 sync_err_q <= '0; ==> 80 end else if (op_done_i) begin -2- 81 sync_err_q <= '0; ==> 82 end else if (op_update_i) begin -3- 83 sync_err_q <= sync_err_d; ==> 84 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


96 if (!rst_ni) begin -1- 97 sync_fault_q <= '0; ==> 98 end else if (op_done_i) begin -2- 99 sync_fault_q <= '0; ==> 100 end else if (op_update_i) begin -3- 101 sync_fault_q <= sync_fault_d; ==> 102 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


109 if (!rst_ni) begin -1- 110 async_fault_q <= '0; ==> 111 end else begin 112 async_fault_q <= async_fault_o; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%