Module Definition
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Module Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.98 100.00 95.92 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.90 100.00 99.61 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
83.33 66.67
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 0/1 ==> assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 2160 2160 0 0
PayLoadWidthCheck 2160 2160 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2160 2160 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2160 2160 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 0/1 ==> assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1080 1080 0 0
PayLoadWidthCheck 1080 1080 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1080 1080 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1080 1080 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1080 1080 0 0
PayLoadWidthCheck 1080 1080 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1080 1080 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1080 1080 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

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