Module Definition
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Module Instance : tb.dut.u_checks.u_creator_seed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_checks


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_checks.u_owner_seed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_checks


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_checks.u_devid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_checks


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_checks.u_health_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_checks


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_checks.gen_key_chk[0].u_key_pad

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_checks


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_checks.gen_key_chk[1].u_key_pad

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_checks


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_msb_extend ( parameter InWidth=256,OutWidth=256,WidthDiff=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_checks.u_creator_seed

SCORELINE
100.00 100.00
tb.dut.u_checks.u_owner_seed

SCORELINE
100.00 100.00
tb.dut.u_checks.u_devid

SCORELINE
100.00 100.00
tb.dut.u_checks.gen_key_chk[0].u_key_pad

SCORELINE
100.00 100.00
tb.dut.u_checks.gen_key_chk[1].u_key_pad

Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2211100.00

21 if (WidthDiff == 0) begin : gen_feedthru 22 1/1 assign out_o = in_i; Tests: T1 T2 T3 

Line Coverage for Module : prim_msb_extend ( parameter InWidth=128,OutWidth=256,WidthDiff=128 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_checks.u_health_state

Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2411100.00

23 end else begin : gen_tieoff 24 1/1 assign out_o = {{WidthDiff{in_i[InWidth-1]}}, in_i}; Tests: T1 T2 T3 

Assert Coverage for Module : prim_msb_extend
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 5250 5250 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5250 5250 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T13 6 6 0 0
T14 6 6 0 0
T15 6 6 0 0
T16 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0

Line Coverage for Instance : tb.dut.u_checks.u_creator_seed
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2211100.00

21 if (WidthDiff == 0) begin : gen_feedthru 22 1/1 assign out_o = in_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_checks.u_creator_seed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 875 875 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_checks.u_owner_seed
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2211100.00

21 if (WidthDiff == 0) begin : gen_feedthru 22 1/1 assign out_o = in_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_checks.u_owner_seed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 875 875 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_checks.u_devid
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2211100.00

21 if (WidthDiff == 0) begin : gen_feedthru 22 1/1 assign out_o = in_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_checks.u_devid
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 875 875 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_checks.u_health_state
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2411100.00

23 end else begin : gen_tieoff 24 1/1 assign out_o = {{WidthDiff{in_i[InWidth-1]}}, in_i}; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_checks.u_health_state
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 875 875 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_checks.gen_key_chk[0].u_key_pad
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2211100.00

21 if (WidthDiff == 0) begin : gen_feedthru 22 1/1 assign out_o = in_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_checks.gen_key_chk[0].u_key_pad
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 875 875 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_checks.gen_key_chk[1].u_key_pad
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2211100.00

21 if (WidthDiff == 0) begin : gen_feedthru 22 1/1 assign out_o = in_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_checks.gen_key_chk[1].u_key_pad
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
WidthCheck_A 875 875 0 0


WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

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