Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_working_state 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_fault_status_kmac_out 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_start 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sideload_clear 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_salt_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_version 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_op_status 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_err_code_invalid_shadow_update 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_cmd 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_fsm 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_done 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_op 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_regfile_intg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_shadow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_reseed_cnt 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fault_status_key_ecc 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_key 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=16,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable

SCORELINE
100.00 100.00
tb.dut.u_reg.u_start

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sideload_clear

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6

SCORELINE
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_2

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_3

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_4

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_5

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_6

SCORELINE
100.00 100.00
tb.dut.u_reg.u_salt_7

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_version

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg

SCORELINE
65.24 85.71
tb.dut.u_reg.u_working_state

SCORELINE
100.00 100.00
tb.dut.u_reg.u_op_status

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_shadow_update

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_cmd

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_fsm

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_done

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_op

SCORELINE
65.24 85.71
tb.dut.u_reg.u_fault_status_kmac_out

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_regfile_intg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_shadow

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_reseed_cnt

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fault_status_key_ecc

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key

SCORELINE
100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest

Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7

Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 1/1 assign qs = de && we ? d : q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT10,T11,T12

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_salt_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_version

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T15

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_op_status

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sideload_clear

SCORECOND
65.24 50.00
tb.dut.u_reg.u_working_state

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state

SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op

SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input

SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_shadow_update

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_start

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key

SCORECOND
100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_cmd

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_fsm

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_done

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_op

SCORECOND
65.24 50.00
tb.dut.u_reg.u_fault_status_kmac_out

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_regfile_intg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_shadow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_reseed_cnt

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fault_status_key_ecc

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=16,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_op

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_err_code_invalid_shadow_update

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_start

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sideload_clear

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_reseed_interval_regwen

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_creator_seed

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_owner_seed

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_dev_id

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_health_state

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key_version

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_key

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_debug_invalid_digest

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_2

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_3

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_4

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_5

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_6

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sealing_sw_binding_7

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_2

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_3

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_4

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_5

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_6

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_attest_sw_binding_7

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_2

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_3

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_4

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_5

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_6

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_salt_7

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_key_version

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_working_state

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_op_status

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_cmd

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_fsm

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_done

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_kmac_op

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_fault_status_kmac_out

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_regfile_intg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_shadow

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_reseed_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_fsm

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_side_ctrl_sel

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fault_status_key_ecc

Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Branch Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=6,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_2

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_3

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_4

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_5

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_6

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share0_output_7

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_2

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_3

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_4

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_5

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_6

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_sw_share1_output_7

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 64 2 2 100.00
TERNARY 70 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


70 assign qs = de && we ? d : q; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T11,T12
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%